1185377Ssam/* 2187831Ssam * Copyright (c) 2002-2009 Sam Leffler, Errno Consulting 3185377Ssam * Copyright (c) 2002-2006 Atheros Communications, Inc. 4185377Ssam * 5185377Ssam * Permission to use, copy, modify, and/or distribute this software for any 6185377Ssam * purpose with or without fee is hereby granted, provided that the above 7185377Ssam * copyright notice and this permission notice appear in all copies. 8185377Ssam * 9185377Ssam * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES 10185377Ssam * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF 11185377Ssam * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR 12185377Ssam * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES 13185377Ssam * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN 14185377Ssam * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF 15185377Ssam * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. 16185377Ssam * 17187611Ssam * $FreeBSD$ 18185377Ssam */ 19185377Ssam#include "opt_ah.h" 20185377Ssam 21185377Ssam/* 22185377Ssam * Chips specific device attachment and device info collection 23185377Ssam * Connects Init Reg Vectors, EEPROM Data, and device Functions. 24185377Ssam */ 25185377Ssam#include "ah.h" 26185377Ssam#include "ah_internal.h" 27185377Ssam#include "ah_devid.h" 28185377Ssam 29185377Ssam#include "ar5211/ar5211.h" 30185377Ssam#include "ar5211/ar5211reg.h" 31185377Ssam#include "ar5211/ar5211phy.h" 32185377Ssam 33185377Ssam#include "ah_eeprom_v3.h" 34185377Ssam 35185377Ssam/* Add static register initialization vectors */ 36185377Ssam#include "ar5211/boss.ini" 37185377Ssam 38185377Ssam/* 39185377Ssam * Structure to hold 11b tuning information for Beanie/Sombrero 40185377Ssam * 16 MHz mode, divider ratio = 198 = NP+S. N=16, S=4 or 6, P=12 41185377Ssam */ 42185377Ssamtypedef struct { 43185377Ssam uint32_t refClkSel; /* reference clock, 1 for 16 MHz */ 44185377Ssam uint32_t channelSelect; /* P[7:4]S[3:0] bits */ 45185377Ssam uint16_t channel5111; /* 11a channel for 5111 */ 46185377Ssam} CHAN_INFO_2GHZ; 47185377Ssam 48185377Ssam#define CI_2GHZ_INDEX_CORRECTION 19 49208644Srpaulostatic const CHAN_INFO_2GHZ chan2GHzData[] = { 50185377Ssam { 1, 0x46, 96 }, /* 2312 -19 */ 51185377Ssam { 1, 0x46, 97 }, /* 2317 -18 */ 52185377Ssam { 1, 0x46, 98 }, /* 2322 -17 */ 53185377Ssam { 1, 0x46, 99 }, /* 2327 -16 */ 54185377Ssam { 1, 0x46, 100 }, /* 2332 -15 */ 55185377Ssam { 1, 0x46, 101 }, /* 2337 -14 */ 56185377Ssam { 1, 0x46, 102 }, /* 2342 -13 */ 57185377Ssam { 1, 0x46, 103 }, /* 2347 -12 */ 58185377Ssam { 1, 0x46, 104 }, /* 2352 -11 */ 59185377Ssam { 1, 0x46, 105 }, /* 2357 -10 */ 60185377Ssam { 1, 0x46, 106 }, /* 2362 -9 */ 61185377Ssam { 1, 0x46, 107 }, /* 2367 -8 */ 62185377Ssam { 1, 0x46, 108 }, /* 2372 -7 */ 63185377Ssam /* index -6 to 0 are pad to make this a nolookup table */ 64185377Ssam { 1, 0x46, 116 }, /* -6 */ 65185377Ssam { 1, 0x46, 116 }, /* -5 */ 66185377Ssam { 1, 0x46, 116 }, /* -4 */ 67185377Ssam { 1, 0x46, 116 }, /* -3 */ 68185377Ssam { 1, 0x46, 116 }, /* -2 */ 69185377Ssam { 1, 0x46, 116 }, /* -1 */ 70185377Ssam { 1, 0x46, 116 }, /* 0 */ 71185377Ssam { 1, 0x46, 116 }, /* 2412 1 */ 72185377Ssam { 1, 0x46, 117 }, /* 2417 2 */ 73185377Ssam { 1, 0x46, 118 }, /* 2422 3 */ 74185377Ssam { 1, 0x46, 119 }, /* 2427 4 */ 75185377Ssam { 1, 0x46, 120 }, /* 2432 5 */ 76185377Ssam { 1, 0x46, 121 }, /* 2437 6 */ 77185377Ssam { 1, 0x46, 122 }, /* 2442 7 */ 78185377Ssam { 1, 0x46, 123 }, /* 2447 8 */ 79185377Ssam { 1, 0x46, 124 }, /* 2452 9 */ 80185377Ssam { 1, 0x46, 125 }, /* 2457 10 */ 81185377Ssam { 1, 0x46, 126 }, /* 2462 11 */ 82185377Ssam { 1, 0x46, 127 }, /* 2467 12 */ 83185377Ssam { 1, 0x46, 128 }, /* 2472 13 */ 84185377Ssam { 1, 0x44, 124 }, /* 2484 14 */ 85185377Ssam { 1, 0x46, 136 }, /* 2512 15 */ 86185377Ssam { 1, 0x46, 140 }, /* 2532 16 */ 87185377Ssam { 1, 0x46, 144 }, /* 2552 17 */ 88185377Ssam { 1, 0x46, 148 }, /* 2572 18 */ 89185377Ssam { 1, 0x46, 152 }, /* 2592 19 */ 90185377Ssam { 1, 0x46, 156 }, /* 2612 20 */ 91185377Ssam { 1, 0x46, 160 }, /* 2632 21 */ 92185377Ssam { 1, 0x46, 164 }, /* 2652 22 */ 93185377Ssam { 1, 0x46, 168 }, /* 2672 23 */ 94185377Ssam { 1, 0x46, 172 }, /* 2692 24 */ 95185377Ssam { 1, 0x46, 176 }, /* 2712 25 */ 96185377Ssam { 1, 0x46, 180 } /* 2732 26 */ 97185377Ssam}; 98185377Ssam 99185377Ssam/* Power timeouts in usec to wait for chip to wake-up. */ 100185377Ssam#define POWER_UP_TIME 2000 101185377Ssam 102185377Ssam#define DELAY_PLL_SETTLE 300 /* 300 us */ 103185377Ssam#define DELAY_BASE_ACTIVATE 100 /* 100 us */ 104185377Ssam 105185377Ssam#define NUM_RATES 8 106185377Ssam 107185377Ssamstatic HAL_BOOL ar5211SetResetReg(struct ath_hal *ah, uint32_t resetMask); 108187831Ssamstatic HAL_BOOL ar5211SetChannel(struct ath_hal *, 109187831Ssam const struct ieee80211_channel *); 110185377Ssamstatic int16_t ar5211RunNoiseFloor(struct ath_hal *, 111185377Ssam uint8_t runTime, int16_t startingNF); 112187831Ssamstatic HAL_BOOL ar5211IsNfGood(struct ath_hal *, 113187831Ssam struct ieee80211_channel *chan); 114187831Ssamstatic HAL_BOOL ar5211SetRf6and7(struct ath_hal *, 115187831Ssam const struct ieee80211_channel *chan); 116187831Ssamstatic HAL_BOOL ar5211SetBoardValues(struct ath_hal *, 117187831Ssam const struct ieee80211_channel *chan); 118185377Ssamstatic void ar5211SetPowerTable(struct ath_hal *, 119185377Ssam PCDACS_EEPROM *pSrcStruct, uint16_t channel); 120187831Ssamstatic HAL_BOOL ar5211SetTransmitPower(struct ath_hal *, 121187831Ssam const struct ieee80211_channel *); 122185377Ssamstatic void ar5211SetRateTable(struct ath_hal *, 123185377Ssam RD_EDGES_POWER *pRdEdgesPower, TRGT_POWER_INFO *pPowerInfo, 124187831Ssam uint16_t numChannels, const struct ieee80211_channel *chan); 125185377Ssamstatic uint16_t ar5211GetScaledPower(uint16_t channel, uint16_t pcdacValue, 126185377Ssam const PCDACS_EEPROM *pSrcStruct); 127185377Ssamstatic HAL_BOOL ar5211FindValueInList(uint16_t channel, uint16_t pcdacValue, 128185377Ssam const PCDACS_EEPROM *pSrcStruct, uint16_t *powerValue); 129185377Ssamstatic uint16_t ar5211GetInterpolatedValue(uint16_t target, 130185377Ssam uint16_t srcLeft, uint16_t srcRight, 131185377Ssam uint16_t targetLeft, uint16_t targetRight, HAL_BOOL scaleUp); 132185377Ssamstatic void ar5211GetLowerUpperValues(uint16_t value, 133185377Ssam const uint16_t *pList, uint16_t listSize, 134185377Ssam uint16_t *pLowerValue, uint16_t *pUpperValue); 135185377Ssamstatic void ar5211GetLowerUpperPcdacs(uint16_t pcdac, 136185377Ssam uint16_t channel, const PCDACS_EEPROM *pSrcStruct, 137185377Ssam uint16_t *pLowerPcdac, uint16_t *pUpperPcdac); 138185377Ssam 139201758Smbrstatic void ar5211SetRfgain(struct ath_hal *, const GAIN_VALUES *); 140185377Ssamstatic void ar5211RequestRfgain(struct ath_hal *); 141185377Ssamstatic HAL_BOOL ar5211InvalidGainReadback(struct ath_hal *, GAIN_VALUES *); 142185377Ssamstatic HAL_BOOL ar5211IsGainAdjustNeeded(struct ath_hal *, const GAIN_VALUES *); 143185377Ssamstatic int32_t ar5211AdjustGain(struct ath_hal *, GAIN_VALUES *); 144185377Ssamstatic void ar5211SetOperatingMode(struct ath_hal *, int opmode); 145185377Ssam 146185377Ssam/* 147185377Ssam * Places the device in and out of reset and then places sane 148185377Ssam * values in the registers based on EEPROM config, initialization 149185377Ssam * vectors (as determined by the mode), and station configuration 150185377Ssam * 151185377Ssam * bChannelChange is used to preserve DMA/PCU registers across 152185377Ssam * a HW Reset during channel change. 153185377Ssam */ 154185377SsamHAL_BOOL 155185377Ssamar5211Reset(struct ath_hal *ah, HAL_OPMODE opmode, 156187831Ssam struct ieee80211_channel *chan, HAL_BOOL bChannelChange, 157290612Sadrian HAL_RESET_TYPE resetType, 158187831Ssam HAL_STATUS *status) 159185377Ssam{ 160185377Ssamuint32_t softLedCfg, softLedState; 161185377Ssam#define N(a) (sizeof (a) /sizeof (a[0])) 162185377Ssam#define FAIL(_code) do { ecode = _code; goto bad; } while (0) 163185377Ssam struct ath_hal_5211 *ahp = AH5211(ah); 164185377Ssam HAL_CHANNEL_INTERNAL *ichan; 165185377Ssam uint32_t i, ledstate; 166185377Ssam HAL_STATUS ecode; 167185377Ssam int q; 168185377Ssam 169185377Ssam uint32_t data, synthDelay; 170185377Ssam uint32_t macStaId1; 171185377Ssam uint16_t modesIndex = 0, freqIndex = 0; 172185377Ssam uint32_t saveFrameSeqCount[AR_NUM_DCU]; 173185377Ssam uint32_t saveTsfLow = 0, saveTsfHigh = 0; 174185377Ssam uint32_t saveDefAntenna; 175185377Ssam 176185377Ssam HALDEBUG(ah, HAL_DEBUG_RESET, 177185377Ssam "%s: opmode %u channel %u/0x%x %s channel\n", 178187831Ssam __func__, opmode, chan->ic_freq, chan->ic_flags, 179185377Ssam bChannelChange ? "change" : "same"); 180185377Ssam 181185377Ssam OS_MARK(ah, AH_MARK_RESET, bChannelChange); 182185377Ssam /* 183185377Ssam * Map public channel to private. 184185377Ssam */ 185185377Ssam ichan = ath_hal_checkchannel(ah, chan); 186187831Ssam if (ichan == AH_NULL) 187185377Ssam FAIL(HAL_EINVAL); 188185377Ssam switch (opmode) { 189185377Ssam case HAL_M_STA: 190185377Ssam case HAL_M_IBSS: 191185377Ssam case HAL_M_HOSTAP: 192185377Ssam case HAL_M_MONITOR: 193185377Ssam break; 194185377Ssam default: 195185377Ssam HALDEBUG(ah, HAL_DEBUG_ANY, 196185377Ssam "%s: invalid operating mode %u\n", __func__, opmode); 197185377Ssam FAIL(HAL_EINVAL); 198185377Ssam break; 199185377Ssam } 200185377Ssam HALASSERT(AH_PRIVATE(ah)->ah_eeversion >= AR_EEPROM_VER3); 201185377Ssam 202185377Ssam /* Preserve certain DMA hardware registers on a channel change */ 203185377Ssam if (bChannelChange) { 204185377Ssam /* 205185377Ssam * Need to save/restore the TSF because of an issue 206185377Ssam * that accelerates the TSF during a chip reset. 207185377Ssam * 208185377Ssam * We could use system timer routines to more 209185377Ssam * accurately restore the TSF, but 210185377Ssam * 1. Timer routines on certain platforms are 211185377Ssam * not accurate enough (e.g. 1 ms resolution). 212185377Ssam * 2. It would still not be accurate. 213185377Ssam * 214185380Ssam * The most important aspect of this workaround, 215185377Ssam * is that, after reset, the TSF is behind 216185377Ssam * other STAs TSFs. This will allow the STA to 217185377Ssam * properly resynchronize its TSF in adhoc mode. 218185377Ssam */ 219185377Ssam saveTsfLow = OS_REG_READ(ah, AR_TSF_L32); 220185377Ssam saveTsfHigh = OS_REG_READ(ah, AR_TSF_U32); 221185377Ssam 222185377Ssam /* Read frame sequence count */ 223185377Ssam if (AH_PRIVATE(ah)->ah_macVersion >= AR_SREV_VERSION_OAHU) { 224185377Ssam saveFrameSeqCount[0] = OS_REG_READ(ah, AR_D0_SEQNUM); 225185377Ssam } else { 226185377Ssam for (i = 0; i < AR_NUM_DCU; i++) 227185377Ssam saveFrameSeqCount[i] = OS_REG_READ(ah, AR_DSEQNUM(i)); 228185377Ssam } 229187831Ssam if (!IEEE80211_IS_CHAN_DFS(chan)) 230187831Ssam chan->ic_state &= ~IEEE80211_CHANSTATE_CWINT; 231185377Ssam } 232185377Ssam 233185377Ssam /* 234185377Ssam * Preserve the antenna on a channel change 235185377Ssam */ 236185377Ssam saveDefAntenna = OS_REG_READ(ah, AR_DEF_ANTENNA); 237185377Ssam if (saveDefAntenna == 0) 238185377Ssam saveDefAntenna = 1; 239185377Ssam 240185377Ssam /* Save hardware flag before chip reset clears the register */ 241185377Ssam macStaId1 = OS_REG_READ(ah, AR_STA_ID1) & AR_STA_ID1_BASE_RATE_11B; 242185377Ssam 243185377Ssam /* Save led state from pci config register */ 244185377Ssam ledstate = OS_REG_READ(ah, AR_PCICFG) & 245185377Ssam (AR_PCICFG_LEDCTL | AR_PCICFG_LEDMODE | AR_PCICFG_LEDBLINK | 246185377Ssam AR_PCICFG_LEDSLOW); 247185377Ssam softLedCfg = OS_REG_READ(ah, AR_GPIOCR); 248185377Ssam softLedState = OS_REG_READ(ah, AR_GPIODO); 249185377Ssam 250187831Ssam if (!ar5211ChipReset(ah, chan)) { 251185377Ssam HALDEBUG(ah, HAL_DEBUG_ANY, "%s: chip reset failed\n", __func__); 252185377Ssam FAIL(HAL_EIO); 253185377Ssam } 254185377Ssam 255185377Ssam /* Setup the indices for the next set of register array writes */ 256187831Ssam if (IEEE80211_IS_CHAN_5GHZ(chan)) { 257187831Ssam freqIndex = 1; 258187831Ssam if (IEEE80211_IS_CHAN_TURBO(chan)) 259187831Ssam modesIndex = 2; 260187831Ssam else if (IEEE80211_IS_CHAN_A(chan)) 261187831Ssam modesIndex = 1; 262187831Ssam else { 263187831Ssam HALDEBUG(ah, HAL_DEBUG_ANY, 264187831Ssam "%s: invalid channel %u/0x%x\n", 265187831Ssam __func__, chan->ic_freq, chan->ic_flags); 266187831Ssam FAIL(HAL_EINVAL); 267187831Ssam } 268187831Ssam } else { 269187831Ssam freqIndex = 2; 270187831Ssam if (IEEE80211_IS_CHAN_B(chan)) 271187831Ssam modesIndex = 3; 272187831Ssam else if (IEEE80211_IS_CHAN_PUREG(chan)) 273187831Ssam modesIndex = 4; 274187831Ssam else { 275187831Ssam HALDEBUG(ah, HAL_DEBUG_ANY, 276187831Ssam "%s: invalid channel %u/0x%x\n", 277187831Ssam __func__, chan->ic_freq, chan->ic_flags); 278187831Ssam FAIL(HAL_EINVAL); 279187831Ssam } 280185377Ssam } 281185377Ssam 282185377Ssam /* Set correct Baseband to analog shift setting to access analog chips. */ 283185377Ssam if (AH_PRIVATE(ah)->ah_macVersion >= AR_SREV_VERSION_OAHU) { 284185377Ssam OS_REG_WRITE(ah, AR_PHY_BASE, 0x00000007); 285185377Ssam } else { 286185377Ssam OS_REG_WRITE(ah, AR_PHY_BASE, 0x00000047); 287185377Ssam } 288185377Ssam 289185377Ssam /* Write parameters specific to AR5211 */ 290185377Ssam if (AH_PRIVATE(ah)->ah_macVersion >= AR_SREV_VERSION_OAHU) { 291187831Ssam if (IEEE80211_IS_CHAN_2GHZ(chan) && 292185377Ssam AH_PRIVATE(ah)->ah_eeversion >= AR_EEPROM_VER3_1) { 293185377Ssam HAL_EEPROM *ee = AH_PRIVATE(ah)->ah_eeprom; 294185377Ssam uint32_t ob2GHz, db2GHz; 295185377Ssam 296187831Ssam if (IEEE80211_IS_CHAN_CCK(chan)) { 297185377Ssam ob2GHz = ee->ee_ob2GHz[0]; 298185377Ssam db2GHz = ee->ee_db2GHz[0]; 299185377Ssam } else { 300185377Ssam ob2GHz = ee->ee_ob2GHz[1]; 301185377Ssam db2GHz = ee->ee_db2GHz[1]; 302185377Ssam } 303185377Ssam ob2GHz = ath_hal_reverseBits(ob2GHz, 3); 304185377Ssam db2GHz = ath_hal_reverseBits(db2GHz, 3); 305185377Ssam ar5211Mode2_4[25][freqIndex] = 306185377Ssam (ar5211Mode2_4[25][freqIndex] & ~0xC0) | 307185377Ssam ((ob2GHz << 6) & 0xC0); 308185377Ssam ar5211Mode2_4[26][freqIndex] = 309185377Ssam (ar5211Mode2_4[26][freqIndex] & ~0x0F) | 310185377Ssam (((ob2GHz >> 2) & 0x1) | 311185377Ssam ((db2GHz << 1) & 0x0E)); 312185377Ssam } 313185377Ssam for (i = 0; i < N(ar5211Mode2_4); i++) 314185377Ssam OS_REG_WRITE(ah, ar5211Mode2_4[i][0], 315185377Ssam ar5211Mode2_4[i][freqIndex]); 316185377Ssam } 317185377Ssam 318185377Ssam /* Write the analog registers 6 and 7 before other config */ 319185377Ssam ar5211SetRf6and7(ah, chan); 320185377Ssam 321185377Ssam /* Write registers that vary across all modes */ 322185377Ssam for (i = 0; i < N(ar5211Modes); i++) 323185377Ssam OS_REG_WRITE(ah, ar5211Modes[i][0], ar5211Modes[i][modesIndex]); 324185377Ssam 325185377Ssam /* Write RFGain Parameters that differ between 2.4 and 5 GHz */ 326185377Ssam for (i = 0; i < N(ar5211BB_RfGain); i++) 327185377Ssam OS_REG_WRITE(ah, ar5211BB_RfGain[i][0], ar5211BB_RfGain[i][freqIndex]); 328185377Ssam 329185377Ssam /* Write Common Array Parameters */ 330185377Ssam for (i = 0; i < N(ar5211Common); i++) { 331185377Ssam uint32_t reg = ar5211Common[i][0]; 332185377Ssam /* On channel change, don't reset the PCU registers */ 333185377Ssam if (!(bChannelChange && (0x8000 <= reg && reg < 0x9000))) 334185377Ssam OS_REG_WRITE(ah, reg, ar5211Common[i][1]); 335185377Ssam } 336185377Ssam 337185377Ssam /* Fix pre-AR5211 register values, this includes AR5311s. */ 338185377Ssam if (AH_PRIVATE(ah)->ah_macVersion < AR_SREV_VERSION_OAHU) { 339185377Ssam /* 340185377Ssam * The TX and RX latency values have changed locations 341185377Ssam * within the USEC register in AR5211. Since they're 342185377Ssam * set via the .ini, for both AR5211 and AR5311, they 343185377Ssam * are written properly here for AR5311. 344185377Ssam */ 345185377Ssam data = OS_REG_READ(ah, AR_USEC); 346185377Ssam /* Must be 0 for proper write in AR5311 */ 347185377Ssam HALASSERT((data & 0x00700000) == 0); 348185377Ssam OS_REG_WRITE(ah, AR_USEC, 349185377Ssam (data & (AR_USEC_M | AR_USEC_32_M | AR5311_USEC_TX_LAT_M)) | 350185377Ssam ((29 << AR5311_USEC_RX_LAT_S) & AR5311_USEC_RX_LAT_M)); 351185377Ssam /* The following registers exist only on AR5311. */ 352185377Ssam OS_REG_WRITE(ah, AR5311_QDCLKGATE, 0); 353185377Ssam 354185377Ssam /* Set proper ADC & DAC delays for AR5311. */ 355185377Ssam OS_REG_WRITE(ah, 0x00009878, 0x00000008); 356185377Ssam 357185377Ssam /* Enable the PCU FIFO corruption ECO on AR5311. */ 358185377Ssam OS_REG_WRITE(ah, AR_DIAG_SW, 359185377Ssam OS_REG_READ(ah, AR_DIAG_SW) | AR5311_DIAG_SW_USE_ECO); 360185377Ssam } 361185377Ssam 362185377Ssam /* Restore certain DMA hardware registers on a channel change */ 363185377Ssam if (bChannelChange) { 364185377Ssam /* Restore TSF */ 365185377Ssam OS_REG_WRITE(ah, AR_TSF_L32, saveTsfLow); 366185377Ssam OS_REG_WRITE(ah, AR_TSF_U32, saveTsfHigh); 367185377Ssam 368185377Ssam if (AH_PRIVATE(ah)->ah_macVersion >= AR_SREV_VERSION_OAHU) { 369185377Ssam OS_REG_WRITE(ah, AR_D0_SEQNUM, saveFrameSeqCount[0]); 370185377Ssam } else { 371185377Ssam for (i = 0; i < AR_NUM_DCU; i++) 372185377Ssam OS_REG_WRITE(ah, AR_DSEQNUM(i), saveFrameSeqCount[i]); 373185377Ssam } 374185377Ssam } 375185377Ssam 376185377Ssam OS_REG_WRITE(ah, AR_STA_ID0, LE_READ_4(ahp->ah_macaddr)); 377185377Ssam OS_REG_WRITE(ah, AR_STA_ID1, LE_READ_2(ahp->ah_macaddr + 4) 378185377Ssam | macStaId1 379185377Ssam ); 380185377Ssam ar5211SetOperatingMode(ah, opmode); 381185377Ssam 382185377Ssam /* Restore previous led state */ 383185377Ssam OS_REG_WRITE(ah, AR_PCICFG, OS_REG_READ(ah, AR_PCICFG) | ledstate); 384185377Ssam OS_REG_WRITE(ah, AR_GPIOCR, softLedCfg); 385185377Ssam OS_REG_WRITE(ah, AR_GPIODO, softLedState); 386185377Ssam 387185377Ssam /* Restore previous antenna */ 388185377Ssam OS_REG_WRITE(ah, AR_DEF_ANTENNA, saveDefAntenna); 389185377Ssam 390185377Ssam OS_REG_WRITE(ah, AR_BSS_ID0, LE_READ_4(ahp->ah_bssid)); 391185377Ssam OS_REG_WRITE(ah, AR_BSS_ID1, LE_READ_2(ahp->ah_bssid + 4)); 392185377Ssam 393185377Ssam /* Restore bmiss rssi & count thresholds */ 394185377Ssam OS_REG_WRITE(ah, AR_RSSI_THR, ahp->ah_rssiThr); 395185377Ssam 396185377Ssam OS_REG_WRITE(ah, AR_ISR, ~0); /* cleared on write */ 397185377Ssam 398185377Ssam /* 399185377Ssam * for pre-Production Oahu only. 400185377Ssam * Disable clock gating in all DMA blocks. Helps when using 401185380Ssam * 11B and AES but results in higher power consumption. 402185377Ssam */ 403185377Ssam if (AH_PRIVATE(ah)->ah_macVersion == AR_SREV_VERSION_OAHU && 404185377Ssam AH_PRIVATE(ah)->ah_macRev < AR_SREV_OAHU_PROD) { 405185377Ssam OS_REG_WRITE(ah, AR_CFG, 406185377Ssam OS_REG_READ(ah, AR_CFG) | AR_CFG_CLK_GATE_DIS); 407185377Ssam } 408185377Ssam 409185377Ssam /* Setup the transmit power values. */ 410185377Ssam if (!ar5211SetTransmitPower(ah, chan)) { 411185377Ssam HALDEBUG(ah, HAL_DEBUG_ANY, 412185377Ssam "%s: error init'ing transmit power\n", __func__); 413185377Ssam FAIL(HAL_EIO); 414185377Ssam } 415185377Ssam 416185377Ssam /* 417185377Ssam * Configurable OFDM spoofing for 11n compatibility; used 418185377Ssam * only when operating in station mode. 419185377Ssam */ 420185377Ssam if (opmode != HAL_M_HOSTAP && 421185377Ssam (AH_PRIVATE(ah)->ah_11nCompat & HAL_DIAG_11N_SERVICES) != 0) { 422185377Ssam /* NB: override the .ini setting */ 423185377Ssam OS_REG_RMW_FIELD(ah, AR_PHY_FRAME_CTL, 424185377Ssam AR_PHY_FRAME_CTL_ERR_SERV, 425185377Ssam MS(AH_PRIVATE(ah)->ah_11nCompat, HAL_DIAG_11N_SERVICES)&1); 426185377Ssam } 427185377Ssam 428185377Ssam /* Setup board specific options for EEPROM version 3 */ 429185377Ssam ar5211SetBoardValues(ah, chan); 430185377Ssam 431187831Ssam if (!ar5211SetChannel(ah, chan)) { 432185377Ssam HALDEBUG(ah, HAL_DEBUG_ANY, "%s: unable to set channel\n", 433185377Ssam __func__); 434185377Ssam FAIL(HAL_EIO); 435185377Ssam } 436185377Ssam 437185377Ssam /* Activate the PHY */ 438187831Ssam if (AH_PRIVATE(ah)->ah_devid == AR5211_FPGA11B && 439187831Ssam IEEE80211_IS_CHAN_2GHZ(chan)) 440185377Ssam OS_REG_WRITE(ah, 0xd808, 0x502); /* required for FPGA */ 441185377Ssam OS_REG_WRITE(ah, AR_PHY_ACTIVE, AR_PHY_ACTIVE_EN); 442185377Ssam 443185377Ssam /* 444185377Ssam * Wait for the frequency synth to settle (synth goes on 445185377Ssam * via AR_PHY_ACTIVE_EN). Read the phy active delay register. 446185377Ssam * Value is in 100ns increments. 447185377Ssam */ 448185377Ssam data = OS_REG_READ(ah, AR_PHY_RX_DELAY) & AR_PHY_RX_DELAY_M; 449187831Ssam if (IEEE80211_IS_CHAN_CCK(chan)) { 450185377Ssam synthDelay = (4 * data) / 22; 451185377Ssam } else { 452185377Ssam synthDelay = data / 10; 453185377Ssam } 454185377Ssam /* 455185377Ssam * There is an issue if the AP starts the calibration before 456185377Ssam * the baseband timeout completes. This could result in the 457185377Ssam * rxclear false triggering. Add an extra delay to ensure this 458185377Ssam * this does not happen. 459185377Ssam */ 460185377Ssam OS_DELAY(synthDelay + DELAY_BASE_ACTIVATE); 461185377Ssam 462185377Ssam /* Calibrate the AGC and wait for completion. */ 463185377Ssam OS_REG_WRITE(ah, AR_PHY_AGC_CONTROL, 464185377Ssam OS_REG_READ(ah, AR_PHY_AGC_CONTROL) | AR_PHY_AGC_CONTROL_CAL); 465185377Ssam (void) ath_hal_wait(ah, AR_PHY_AGC_CONTROL, AR_PHY_AGC_CONTROL_CAL, 0); 466185377Ssam 467185377Ssam /* Perform noise floor and set status */ 468187831Ssam if (!ar5211CalNoiseFloor(ah, chan)) { 469187831Ssam if (!IEEE80211_IS_CHAN_CCK(chan)) 470187831Ssam chan->ic_state |= IEEE80211_CHANSTATE_CWINT; 471185377Ssam HALDEBUG(ah, HAL_DEBUG_ANY, 472185377Ssam "%s: noise floor calibration failed\n", __func__); 473185377Ssam FAIL(HAL_EIO); 474185377Ssam } 475185377Ssam 476185377Ssam /* Start IQ calibration w/ 2^(INIT_IQCAL_LOG_COUNT_MAX+1) samples */ 477185377Ssam if (ahp->ah_calibrationTime != 0) { 478185377Ssam OS_REG_WRITE(ah, AR_PHY_TIMING_CTRL4, 479185377Ssam AR_PHY_TIMING_CTRL4_DO_IQCAL | (INIT_IQCAL_LOG_COUNT_MAX << AR_PHY_TIMING_CTRL4_IQCAL_LOG_COUNT_MAX_S)); 480185377Ssam ahp->ah_bIQCalibration = AH_TRUE; 481185377Ssam } 482185377Ssam 483185377Ssam /* set 1:1 QCU to DCU mapping for all queues */ 484185377Ssam for (q = 0; q < AR_NUM_DCU; q++) 485185377Ssam OS_REG_WRITE(ah, AR_DQCUMASK(q), 1<<q); 486185377Ssam 487185377Ssam for (q = 0; q < HAL_NUM_TX_QUEUES; q++) 488185377Ssam ar5211ResetTxQueue(ah, q); 489185377Ssam 490185377Ssam /* Setup QCU0 transmit interrupt masks (TX_ERR, TX_OK, TX_DESC, TX_URN) */ 491185377Ssam OS_REG_WRITE(ah, AR_IMR_S0, 492185377Ssam (AR_IMR_S0_QCU_TXOK & AR_QCU_0) | 493185377Ssam (AR_IMR_S0_QCU_TXDESC & (AR_QCU_0<<AR_IMR_S0_QCU_TXDESC_S))); 494185377Ssam OS_REG_WRITE(ah, AR_IMR_S1, (AR_IMR_S1_QCU_TXERR & AR_QCU_0)); 495185377Ssam OS_REG_WRITE(ah, AR_IMR_S2, (AR_IMR_S2_QCU_TXURN & AR_QCU_0)); 496185377Ssam 497185377Ssam /* 498185377Ssam * GBL_EIFS must always be written after writing 499185377Ssam * to any QCUMASK register. 500185377Ssam */ 501185377Ssam OS_REG_WRITE(ah, AR_D_GBL_IFS_EIFS, OS_REG_READ(ah, AR_D_GBL_IFS_EIFS)); 502185377Ssam 503185377Ssam /* Now set up the Interrupt Mask Register and save it for future use */ 504185377Ssam OS_REG_WRITE(ah, AR_IMR, INIT_INTERRUPT_MASK); 505185377Ssam ahp->ah_maskReg = INIT_INTERRUPT_MASK; 506185377Ssam 507185377Ssam /* Enable bus error interrupts */ 508185377Ssam OS_REG_WRITE(ah, AR_IMR_S2, OS_REG_READ(ah, AR_IMR_S2) | 509185377Ssam AR_IMR_S2_MCABT | AR_IMR_S2_SSERR | AR_IMR_S2_DPERR); 510185377Ssam 511185377Ssam /* Enable interrupts specific to AP */ 512185377Ssam if (opmode == HAL_M_HOSTAP) { 513185377Ssam OS_REG_WRITE(ah, AR_IMR, OS_REG_READ(ah, AR_IMR) | AR_IMR_MIB); 514185377Ssam ahp->ah_maskReg |= AR_IMR_MIB; 515185377Ssam } 516185377Ssam 517185377Ssam if (AH_PRIVATE(ah)->ah_rfkillEnabled) 518185377Ssam ar5211EnableRfKill(ah); 519185377Ssam 520185377Ssam /* 521185377Ssam * Writing to AR_BEACON will start timers. Hence it should 522185377Ssam * be the last register to be written. Do not reset tsf, do 523185377Ssam * not enable beacons at this point, but preserve other values 524185377Ssam * like beaconInterval. 525185377Ssam */ 526185377Ssam OS_REG_WRITE(ah, AR_BEACON, 527185377Ssam (OS_REG_READ(ah, AR_BEACON) &~ (AR_BEACON_EN | AR_BEACON_RESET_TSF))); 528185377Ssam 529185377Ssam /* Restore user-specified slot time and timeouts */ 530185377Ssam if (ahp->ah_sifstime != (u_int) -1) 531185377Ssam ar5211SetSifsTime(ah, ahp->ah_sifstime); 532185377Ssam if (ahp->ah_slottime != (u_int) -1) 533185377Ssam ar5211SetSlotTime(ah, ahp->ah_slottime); 534185377Ssam if (ahp->ah_acktimeout != (u_int) -1) 535185377Ssam ar5211SetAckTimeout(ah, ahp->ah_acktimeout); 536185377Ssam if (ahp->ah_ctstimeout != (u_int) -1) 537185377Ssam ar5211SetCTSTimeout(ah, ahp->ah_ctstimeout); 538185377Ssam if (AH_PRIVATE(ah)->ah_diagreg != 0) 539185377Ssam OS_REG_WRITE(ah, AR_DIAG_SW, AH_PRIVATE(ah)->ah_diagreg); 540185377Ssam 541185377Ssam AH_PRIVATE(ah)->ah_opmode = opmode; /* record operating mode */ 542185377Ssam 543185377Ssam HALDEBUG(ah, HAL_DEBUG_RESET, "%s: done\n", __func__); 544185377Ssam 545185377Ssam return AH_TRUE; 546185377Ssambad: 547187611Ssam if (status != AH_NULL) 548185377Ssam *status = ecode; 549185377Ssam return AH_FALSE; 550185377Ssam#undef FAIL 551185377Ssam#undef N 552185377Ssam} 553185377Ssam 554185377Ssam/* 555185377Ssam * Places the PHY and Radio chips into reset. A full reset 556185377Ssam * must be called to leave this state. The PCI/MAC/PCU are 557185377Ssam * not placed into reset as we must receive interrupt to 558185377Ssam * re-enable the hardware. 559185377Ssam */ 560185377SsamHAL_BOOL 561185377Ssamar5211PhyDisable(struct ath_hal *ah) 562185377Ssam{ 563185377Ssam return ar5211SetResetReg(ah, AR_RC_BB); 564185377Ssam} 565185377Ssam 566185377Ssam/* 567185377Ssam * Places all of hardware into reset 568185377Ssam */ 569185377SsamHAL_BOOL 570185377Ssamar5211Disable(struct ath_hal *ah) 571185377Ssam{ 572185377Ssam if (!ar5211SetPowerMode(ah, HAL_PM_AWAKE, AH_TRUE)) 573185377Ssam return AH_FALSE; 574185377Ssam /* 575185377Ssam * Reset the HW - PCI must be reset after the rest of the 576185377Ssam * device has been reset. 577185377Ssam */ 578185377Ssam if (!ar5211SetResetReg(ah, AR_RC_MAC | AR_RC_BB | AR_RC_PCI)) 579185377Ssam return AH_FALSE; 580185377Ssam OS_DELAY(2100); /* 8245 @ 96Mhz hangs with 2000us. */ 581185377Ssam 582185377Ssam return AH_TRUE; 583185377Ssam} 584185377Ssam 585185377Ssam/* 586185377Ssam * Places the hardware into reset and then pulls it out of reset 587185377Ssam * 588185377Ssam * Only write the PLL if we're changing to or from CCK mode 589185377Ssam * 590185377Ssam * Attach calls with channelFlags = 0, as the coldreset should have 591185377Ssam * us in the correct mode and we cannot check the hwchannel flags. 592185377Ssam */ 593185377SsamHAL_BOOL 594187831Ssamar5211ChipReset(struct ath_hal *ah, const struct ieee80211_channel *chan) 595185377Ssam{ 596185377Ssam if (!ar5211SetPowerMode(ah, HAL_PM_AWAKE, AH_TRUE)) 597185377Ssam return AH_FALSE; 598185377Ssam 599187831Ssam /* NB: called from attach with chan null */ 600187831Ssam if (chan != AH_NULL) { 601187831Ssam /* Set CCK and Turbo modes correctly */ 602187831Ssam OS_REG_WRITE(ah, AR_PHY_TURBO, IEEE80211_IS_CHAN_TURBO(chan) ? 603187831Ssam AR_PHY_FC_TURBO_MODE | AR_PHY_FC_TURBO_SHORT : 0); 604187831Ssam if (IEEE80211_IS_CHAN_B(chan)) { 605187831Ssam OS_REG_WRITE(ah, AR5211_PHY_MODE, 606187831Ssam AR5211_PHY_MODE_CCK | AR5211_PHY_MODE_RF2GHZ); 607187831Ssam OS_REG_WRITE(ah, AR_PHY_PLL_CTL, AR_PHY_PLL_CTL_44); 608187831Ssam /* Wait for the PLL to settle */ 609185377Ssam OS_DELAY(DELAY_PLL_SETTLE); 610187831Ssam } else if (AH_PRIVATE(ah)->ah_devid == AR5211_DEVID) { 611185377Ssam OS_REG_WRITE(ah, AR_PHY_PLL_CTL, AR_PHY_PLL_CTL_40); 612185377Ssam OS_DELAY(DELAY_PLL_SETTLE); 613185377Ssam OS_REG_WRITE(ah, AR5211_PHY_MODE, 614187831Ssam AR5211_PHY_MODE_OFDM | (IEEE80211_IS_CHAN_2GHZ(chan) ? 615187831Ssam AR5211_PHY_MODE_RF2GHZ : 616187831Ssam AR5211_PHY_MODE_RF5GHZ)); 617185377Ssam } 618185377Ssam } 619185377Ssam 620185377Ssam /* 621185377Ssam * Reset the HW - PCI must be reset after the rest of the 622185377Ssam * device has been reset 623185377Ssam */ 624185377Ssam if (!ar5211SetResetReg(ah, AR_RC_MAC | AR_RC_BB | AR_RC_PCI)) 625185377Ssam return AH_FALSE; 626185377Ssam OS_DELAY(2100); /* 8245 @ 96Mhz hangs with 2000us. */ 627185377Ssam 628185377Ssam /* Bring out of sleep mode (AGAIN) */ 629185377Ssam if (!ar5211SetPowerMode(ah, HAL_PM_AWAKE, AH_TRUE)) 630185377Ssam return AH_FALSE; 631185377Ssam 632185377Ssam /* Clear warm reset register */ 633185377Ssam return ar5211SetResetReg(ah, 0); 634185377Ssam} 635185377Ssam 636185377Ssam/* 637185377Ssam * Recalibrate the lower PHY chips to account for temperature/environment 638185377Ssam * changes. 639185377Ssam */ 640185377SsamHAL_BOOL 641187831Ssamar5211PerCalibrationN(struct ath_hal *ah, struct ieee80211_channel *chan, 642187831Ssam u_int chainMask, HAL_BOOL longCal, HAL_BOOL *isCalDone) 643185377Ssam{ 644185377Ssam struct ath_hal_5211 *ahp = AH5211(ah); 645185377Ssam HAL_CHANNEL_INTERNAL *ichan; 646185377Ssam int32_t qCoff, qCoffDenom; 647185377Ssam uint32_t data; 648185377Ssam int32_t iqCorrMeas; 649185377Ssam int32_t iCoff, iCoffDenom; 650185377Ssam uint32_t powerMeasQ, powerMeasI; 651185377Ssam 652185377Ssam ichan = ath_hal_checkchannel(ah, chan); 653185377Ssam if (ichan == AH_NULL) { 654185377Ssam HALDEBUG(ah, HAL_DEBUG_ANY, 655185377Ssam "%s: invalid channel %u/0x%x; no mapping\n", 656187831Ssam __func__, chan->ic_freq, chan->ic_flags); 657185377Ssam return AH_FALSE; 658185377Ssam } 659185377Ssam /* IQ calibration in progress. Check to see if it has finished. */ 660185377Ssam if (ahp->ah_bIQCalibration && 661185377Ssam !(OS_REG_READ(ah, AR_PHY_TIMING_CTRL4) & AR_PHY_TIMING_CTRL4_DO_IQCAL)) { 662185377Ssam /* IQ Calibration has finished. */ 663185377Ssam ahp->ah_bIQCalibration = AH_FALSE; 664185377Ssam 665185377Ssam /* Read calibration results. */ 666185377Ssam powerMeasI = OS_REG_READ(ah, AR_PHY_IQCAL_RES_PWR_MEAS_I); 667185377Ssam powerMeasQ = OS_REG_READ(ah, AR_PHY_IQCAL_RES_PWR_MEAS_Q); 668185377Ssam iqCorrMeas = OS_REG_READ(ah, AR_PHY_IQCAL_RES_IQ_CORR_MEAS); 669185377Ssam 670185377Ssam /* 671185377Ssam * Prescale these values to remove 64-bit operation requirement at the loss 672185377Ssam * of a little precision. 673185377Ssam */ 674185377Ssam iCoffDenom = (powerMeasI / 2 + powerMeasQ / 2) / 128; 675185377Ssam qCoffDenom = powerMeasQ / 64; 676185377Ssam 677185377Ssam /* Protect against divide-by-0. */ 678185377Ssam if (iCoffDenom != 0 && qCoffDenom != 0) { 679185377Ssam iCoff = (-iqCorrMeas) / iCoffDenom; 680185377Ssam /* IQCORR_Q_I_COFF is a signed 6 bit number */ 681185377Ssam iCoff = iCoff & 0x3f; 682185377Ssam 683185377Ssam qCoff = ((int32_t)powerMeasI / qCoffDenom) - 64; 684185377Ssam /* IQCORR_Q_Q_COFF is a signed 5 bit number */ 685185377Ssam qCoff = qCoff & 0x1f; 686185377Ssam 687185377Ssam HALDEBUG(ah, HAL_DEBUG_PERCAL, "powerMeasI = 0x%08x\n", 688185377Ssam powerMeasI); 689185377Ssam HALDEBUG(ah, HAL_DEBUG_PERCAL, "powerMeasQ = 0x%08x\n", 690185377Ssam powerMeasQ); 691185377Ssam HALDEBUG(ah, HAL_DEBUG_PERCAL, "iqCorrMeas = 0x%08x\n", 692185377Ssam iqCorrMeas); 693185377Ssam HALDEBUG(ah, HAL_DEBUG_PERCAL, "iCoff = %d\n", 694185377Ssam iCoff); 695185377Ssam HALDEBUG(ah, HAL_DEBUG_PERCAL, "qCoff = %d\n", 696185377Ssam qCoff); 697185377Ssam 698185377Ssam /* Write IQ */ 699185377Ssam data = OS_REG_READ(ah, AR_PHY_TIMING_CTRL4) | 700185377Ssam AR_PHY_TIMING_CTRL4_IQCORR_ENABLE | 701185377Ssam (((uint32_t)iCoff) << AR_PHY_TIMING_CTRL4_IQCORR_Q_I_COFF_S) | 702185377Ssam ((uint32_t)qCoff); 703185377Ssam OS_REG_WRITE(ah, AR_PHY_TIMING_CTRL4, data); 704185377Ssam } 705185377Ssam } 706185380Ssam *isCalDone = !ahp->ah_bIQCalibration; 707185377Ssam 708185380Ssam if (longCal) { 709185380Ssam /* Perform noise floor and set status */ 710187831Ssam if (!ar5211IsNfGood(ah, chan)) { 711185380Ssam /* report up and clear internal state */ 712187831Ssam chan->ic_state |= IEEE80211_CHANSTATE_CWINT; 713185377Ssam return AH_FALSE; 714185377Ssam } 715187831Ssam if (!ar5211CalNoiseFloor(ah, chan)) { 716185380Ssam /* 717185380Ssam * Delay 5ms before retrying the noise floor 718185380Ssam * just to make sure, as we are in an error 719185380Ssam * condition here. 720185380Ssam */ 721185380Ssam OS_DELAY(5000); 722187831Ssam if (!ar5211CalNoiseFloor(ah, chan)) { 723187831Ssam if (!IEEE80211_IS_CHAN_CCK(chan)) 724187831Ssam chan->ic_state |= IEEE80211_CHANSTATE_CWINT; 725185380Ssam return AH_FALSE; 726185380Ssam } 727185380Ssam } 728185380Ssam ar5211RequestRfgain(ah); 729185377Ssam } 730185380Ssam return AH_TRUE; 731185380Ssam} 732185377Ssam 733185380SsamHAL_BOOL 734187831Ssamar5211PerCalibration(struct ath_hal *ah, struct ieee80211_channel *chan, 735187831Ssam HAL_BOOL *isIQdone) 736185380Ssam{ 737185380Ssam return ar5211PerCalibrationN(ah, chan, 0x1, AH_TRUE, isIQdone); 738185380Ssam} 739185377Ssam 740185380SsamHAL_BOOL 741187831Ssamar5211ResetCalValid(struct ath_hal *ah, const struct ieee80211_channel *chan) 742185380Ssam{ 743185380Ssam /* XXX */ 744185377Ssam return AH_TRUE; 745185377Ssam} 746185377Ssam 747185377Ssam/* 748185377Ssam * Writes the given reset bit mask into the reset register 749185377Ssam */ 750185377Ssamstatic HAL_BOOL 751185377Ssamar5211SetResetReg(struct ath_hal *ah, uint32_t resetMask) 752185377Ssam{ 753185377Ssam uint32_t mask = resetMask ? resetMask : ~0; 754185377Ssam HAL_BOOL rt; 755185377Ssam 756185377Ssam (void) OS_REG_READ(ah, AR_RXDP);/* flush any pending MMR writes */ 757185377Ssam OS_REG_WRITE(ah, AR_RC, resetMask); 758185377Ssam 759185377Ssam /* need to wait at least 128 clocks when reseting PCI before read */ 760185377Ssam OS_DELAY(15); 761185377Ssam 762185377Ssam resetMask &= AR_RC_MAC | AR_RC_BB; 763185377Ssam mask &= AR_RC_MAC | AR_RC_BB; 764185377Ssam rt = ath_hal_wait(ah, AR_RC, mask, resetMask); 765185377Ssam if ((resetMask & AR_RC_MAC) == 0) { 766185377Ssam if (isBigEndian()) { 767185377Ssam /* 768234450Sadrian * Set CFG, little-endian for descriptor accesses. 769185377Ssam */ 770234450Sadrian mask = INIT_CONFIG_STATUS | AR_CFG_SWTD | AR_CFG_SWRD; 771234450Sadrian OS_REG_WRITE(ah, AR_CFG, mask); 772185377Ssam } else 773185377Ssam OS_REG_WRITE(ah, AR_CFG, INIT_CONFIG_STATUS); 774185377Ssam } 775185377Ssam return rt; 776185377Ssam} 777185377Ssam 778185377Ssam/* 779185377Ssam * Takes the MHz channel value and sets the Channel value 780185377Ssam * 781185377Ssam * ASSUMES: Writes enabled to analog bus before AGC is active 782185377Ssam * or by disabling the AGC. 783185377Ssam */ 784185377Ssamstatic HAL_BOOL 785187831Ssamar5211SetChannel(struct ath_hal *ah, const struct ieee80211_channel *chan) 786185377Ssam{ 787185377Ssam uint32_t refClk, reg32, data2111; 788185377Ssam int16_t chan5111, chanIEEE; 789185377Ssam 790187831Ssam chanIEEE = chan->ic_ieee; 791187831Ssam if (IEEE80211_IS_CHAN_2GHZ(chan)) { 792185377Ssam const CHAN_INFO_2GHZ* ci = 793185377Ssam &chan2GHzData[chanIEEE + CI_2GHZ_INDEX_CORRECTION]; 794185377Ssam 795185377Ssam data2111 = ((ath_hal_reverseBits(ci->channelSelect, 8) & 0xff) 796185377Ssam << 5) 797185377Ssam | (ci->refClkSel << 4); 798185377Ssam chan5111 = ci->channel5111; 799185377Ssam } else { 800185377Ssam data2111 = 0; 801185377Ssam chan5111 = chanIEEE; 802185377Ssam } 803185377Ssam 804185377Ssam /* Rest of the code is common for 5 GHz and 2.4 GHz. */ 805185377Ssam if (chan5111 >= 145 || (chan5111 & 0x1)) { 806185377Ssam reg32 = ath_hal_reverseBits(chan5111 - 24, 8) & 0xFF; 807185377Ssam refClk = 1; 808185377Ssam } else { 809185377Ssam reg32 = ath_hal_reverseBits(((chan5111 - 24) / 2), 8) & 0xFF; 810185377Ssam refClk = 0; 811185377Ssam } 812185377Ssam 813185377Ssam reg32 = (reg32 << 2) | (refClk << 1) | (1 << 10) | 0x1; 814185377Ssam OS_REG_WRITE(ah, AR_PHY(0x27), ((data2111 & 0xff) << 8) | (reg32 & 0xff)); 815185377Ssam reg32 >>= 8; 816185377Ssam OS_REG_WRITE(ah, AR_PHY(0x34), (data2111 & 0xff00) | (reg32 & 0xff)); 817185377Ssam 818185377Ssam AH_PRIVATE(ah)->ah_curchan = chan; 819185377Ssam return AH_TRUE; 820185377Ssam} 821185377Ssam 822185377Ssamstatic int16_t 823185377Ssamar5211GetNoiseFloor(struct ath_hal *ah) 824185377Ssam{ 825185377Ssam int16_t nf; 826185377Ssam 827185377Ssam nf = (OS_REG_READ(ah, AR_PHY(25)) >> 19) & 0x1ff; 828185377Ssam if (nf & 0x100) 829185377Ssam nf = 0 - ((nf ^ 0x1ff) + 1); 830185377Ssam return nf; 831185377Ssam} 832185377Ssam 833185377Ssam/* 834185377Ssam * Peform the noisefloor calibration for the length of time set 835185377Ssam * in runTime (valid values 1 to 7) 836185377Ssam * 837185377Ssam * Returns: The NF value at the end of the given time (or 0 for failure) 838185377Ssam */ 839185377Ssamint16_t 840185377Ssamar5211RunNoiseFloor(struct ath_hal *ah, uint8_t runTime, int16_t startingNF) 841185377Ssam{ 842185377Ssam int i, searchTime; 843185377Ssam 844185377Ssam HALASSERT(runTime <= 7); 845185377Ssam 846185377Ssam /* Setup noise floor run time and starting value */ 847185377Ssam OS_REG_WRITE(ah, AR_PHY(25), 848185377Ssam (OS_REG_READ(ah, AR_PHY(25)) & ~0xFFF) | 849185377Ssam ((runTime << 9) & 0xE00) | (startingNF & 0x1FF)); 850185377Ssam /* Calibrate the noise floor */ 851185377Ssam OS_REG_WRITE(ah, AR_PHY_AGC_CONTROL, 852185377Ssam OS_REG_READ(ah, AR_PHY_AGC_CONTROL) | AR_PHY_AGC_CONTROL_NF); 853185377Ssam 854185377Ssam /* Compute the required amount of searchTime needed to finish NF */ 855185377Ssam if (runTime == 0) { 856185377Ssam /* 8 search windows * 6.4us each */ 857185377Ssam searchTime = 8 * 7; 858185377Ssam } else { 859185377Ssam /* 512 * runtime search windows * 6.4us each */ 860185377Ssam searchTime = (runTime * 512) * 7; 861185377Ssam } 862185377Ssam 863185377Ssam /* 864185377Ssam * Do not read noise floor until it has been updated 865185377Ssam * 866185377Ssam * As a guesstimate - we may only get 1/60th the time on 867185377Ssam * the air to see search windows in a heavily congested 868185377Ssam * network (40 us every 2400 us of time) 869185377Ssam */ 870185377Ssam for (i = 0; i < 60; i++) { 871185377Ssam if ((OS_REG_READ(ah, AR_PHY_AGC_CONTROL) & AR_PHY_AGC_CONTROL_NF) == 0) 872185377Ssam break; 873185377Ssam OS_DELAY(searchTime); 874185377Ssam } 875185377Ssam if (i >= 60) { 876185377Ssam HALDEBUG(ah, HAL_DEBUG_NFCAL, 877185377Ssam "NF with runTime %d failed to end on channel %d\n", 878187831Ssam runTime, AH_PRIVATE(ah)->ah_curchan->ic_freq); 879185377Ssam HALDEBUG(ah, HAL_DEBUG_NFCAL, 880185377Ssam " PHY NF Reg state: 0x%x\n", 881185377Ssam OS_REG_READ(ah, AR_PHY_AGC_CONTROL)); 882185377Ssam HALDEBUG(ah, HAL_DEBUG_NFCAL, 883185377Ssam " PHY Active Reg state: 0x%x\n", 884185377Ssam OS_REG_READ(ah, AR_PHY_ACTIVE)); 885185377Ssam return 0; 886185377Ssam } 887185377Ssam 888185377Ssam return ar5211GetNoiseFloor(ah); 889185377Ssam} 890185377Ssam 891185377Ssamstatic HAL_BOOL 892187831SsamgetNoiseFloorThresh(struct ath_hal *ah, const struct ieee80211_channel *chan, 893187831Ssam int16_t *nft) 894185377Ssam{ 895185377Ssam HAL_EEPROM *ee = AH_PRIVATE(ah)->ah_eeprom; 896185377Ssam 897187831Ssam switch (chan->ic_flags & IEEE80211_CHAN_ALLFULL) { 898187831Ssam case IEEE80211_CHAN_A: 899185377Ssam *nft = ee->ee_noiseFloorThresh[0]; 900185377Ssam break; 901187831Ssam case IEEE80211_CHAN_B: 902185377Ssam *nft = ee->ee_noiseFloorThresh[1]; 903185377Ssam break; 904187831Ssam case IEEE80211_CHAN_PUREG: 905185377Ssam *nft = ee->ee_noiseFloorThresh[2]; 906185377Ssam break; 907185377Ssam default: 908185377Ssam HALDEBUG(ah, HAL_DEBUG_ANY, "%s: invalid channel flags 0x%x\n", 909187831Ssam __func__, chan->ic_flags); 910185377Ssam return AH_FALSE; 911185377Ssam } 912185377Ssam return AH_TRUE; 913185377Ssam} 914185377Ssam 915185377Ssam/* 916298939Spfg * Read the NF and check it against the noise floor threshold 917185377Ssam * 918185377Ssam * Returns: TRUE if the NF is good 919185377Ssam */ 920185377Ssamstatic HAL_BOOL 921187831Ssamar5211IsNfGood(struct ath_hal *ah, struct ieee80211_channel *chan) 922185377Ssam{ 923187831Ssam HAL_CHANNEL_INTERNAL *ichan = ath_hal_checkchannel(ah, chan); 924185377Ssam int16_t nf, nfThresh; 925185377Ssam 926185377Ssam if (!getNoiseFloorThresh(ah, chan, &nfThresh)) 927185377Ssam return AH_FALSE; 928208644Srpaulo if (OS_REG_READ(ah, AR_PHY_AGC_CONTROL) & AR_PHY_AGC_CONTROL_NF) { 929185377Ssam HALDEBUG(ah, HAL_DEBUG_ANY, 930185377Ssam "%s: NF did not complete in calibration window\n", __func__); 931208644Srpaulo } 932185377Ssam nf = ar5211GetNoiseFloor(ah); 933185377Ssam if (nf > nfThresh) { 934185377Ssam HALDEBUG(ah, HAL_DEBUG_ANY, 935185377Ssam "%s: noise floor failed; detected %u, threshold %u\n", 936185377Ssam __func__, nf, nfThresh); 937185377Ssam /* 938185377Ssam * NB: Don't discriminate 2.4 vs 5Ghz, if this 939185377Ssam * happens it indicates a problem regardless 940185377Ssam * of the band. 941185377Ssam */ 942187831Ssam chan->ic_state |= IEEE80211_CHANSTATE_CWINT; 943185377Ssam } 944187831Ssam ichan->rawNoiseFloor = nf; 945185377Ssam return (nf <= nfThresh); 946185377Ssam} 947185377Ssam 948185377Ssam/* 949185377Ssam * Peform the noisefloor calibration and check for any constant channel 950185377Ssam * interference. 951185377Ssam * 952185377Ssam * NOTE: preAR5211 have a lengthy carrier wave detection process - hence 953185377Ssam * it is if'ed for MKK regulatory domain only. 954185377Ssam * 955185377Ssam * Returns: TRUE for a successful noise floor calibration; else FALSE 956185377Ssam */ 957185377SsamHAL_BOOL 958187831Ssamar5211CalNoiseFloor(struct ath_hal *ah, const struct ieee80211_channel *chan) 959185377Ssam{ 960185377Ssam#define N(a) (sizeof (a) / sizeof (a[0])) 961185377Ssam /* Check for Carrier Wave interference in MKK regulatory zone */ 962185377Ssam if (AH_PRIVATE(ah)->ah_macVersion < AR_SREV_VERSION_OAHU && 963187831Ssam (chan->ic_flags & CHANNEL_NFCREQUIRED)) { 964185377Ssam static const uint8_t runtime[3] = { 0, 2, 7 }; 965187831Ssam HAL_CHANNEL_INTERNAL *ichan = ath_hal_checkchannel(ah, chan); 966185377Ssam int16_t nf, nfThresh; 967185377Ssam int i; 968185377Ssam 969185377Ssam if (!getNoiseFloorThresh(ah, chan, &nfThresh)) 970185377Ssam return AH_FALSE; 971185377Ssam /* 972185377Ssam * Run a quick noise floor that will hopefully 973185377Ssam * complete (decrease delay time). 974185377Ssam */ 975185377Ssam for (i = 0; i < N(runtime); i++) { 976185377Ssam nf = ar5211RunNoiseFloor(ah, runtime[i], 0); 977185377Ssam if (nf > nfThresh) { 978185377Ssam HALDEBUG(ah, HAL_DEBUG_ANY, 979185377Ssam "%s: run failed with %u > threshold %u " 980185377Ssam "(runtime %u)\n", __func__, 981185377Ssam nf, nfThresh, runtime[i]); 982187831Ssam ichan->rawNoiseFloor = 0; 983185377Ssam } else 984187831Ssam ichan->rawNoiseFloor = nf; 985185377Ssam } 986185377Ssam return (i <= N(runtime)); 987185377Ssam } else { 988185377Ssam /* Calibrate the noise floor */ 989185377Ssam OS_REG_WRITE(ah, AR_PHY_AGC_CONTROL, 990185377Ssam OS_REG_READ(ah, AR_PHY_AGC_CONTROL) | 991185377Ssam AR_PHY_AGC_CONTROL_NF); 992185377Ssam } 993185377Ssam return AH_TRUE; 994185377Ssam#undef N 995185377Ssam} 996185377Ssam 997185377Ssam/* 998185377Ssam * Adjust NF based on statistical values for 5GHz frequencies. 999185377Ssam */ 1000185377Ssamint16_t 1001185377Ssamar5211GetNfAdjust(struct ath_hal *ah, const HAL_CHANNEL_INTERNAL *c) 1002185377Ssam{ 1003185377Ssam static const struct { 1004185377Ssam uint16_t freqLow; 1005185377Ssam int16_t adjust; 1006185377Ssam } adjust5111[] = { 1007185377Ssam { 5790, 11 }, /* NB: ordered high -> low */ 1008185377Ssam { 5730, 10 }, 1009185377Ssam { 5690, 9 }, 1010185377Ssam { 5660, 8 }, 1011185377Ssam { 5610, 7 }, 1012185377Ssam { 5530, 5 }, 1013185377Ssam { 5450, 4 }, 1014185377Ssam { 5379, 2 }, 1015185377Ssam { 5209, 0 }, /* XXX? bogus but doesn't matter */ 1016185377Ssam { 0, 1 }, 1017185377Ssam }; 1018185377Ssam int i; 1019185377Ssam 1020185377Ssam for (i = 0; c->channel <= adjust5111[i].freqLow; i++) 1021185377Ssam ; 1022185377Ssam /* NB: placeholder for 5111's less severe requirement */ 1023185377Ssam return adjust5111[i].adjust / 3; 1024185377Ssam} 1025185377Ssam 1026185377Ssam/* 1027185377Ssam * Reads EEPROM header info from device structure and programs 1028185377Ssam * analog registers 6 and 7 1029185377Ssam * 1030185377Ssam * REQUIRES: Access to the analog device 1031185377Ssam */ 1032185377Ssamstatic HAL_BOOL 1033187831Ssamar5211SetRf6and7(struct ath_hal *ah, const struct ieee80211_channel *chan) 1034185377Ssam{ 1035185377Ssam#define N(a) (sizeof (a) / sizeof (a[0])) 1036187831Ssam uint16_t freq = ath_hal_gethwchannel(ah, chan); 1037185377Ssam HAL_EEPROM *ee = AH_PRIVATE(ah)->ah_eeprom; 1038185377Ssam struct ath_hal_5211 *ahp = AH5211(ah); 1039185377Ssam uint16_t rfXpdGain, rfPloSel, rfPwdXpd; 1040185377Ssam uint16_t tempOB, tempDB; 1041185377Ssam uint16_t freqIndex; 1042185377Ssam int i; 1043185377Ssam 1044187831Ssam freqIndex = IEEE80211_IS_CHAN_2GHZ(chan) ? 2 : 1; 1045185377Ssam 1046185377Ssam /* 1047185377Ssam * TODO: This array mode correspondes with the index used 1048185377Ssam * during the read. 1049185377Ssam * For readability, this should be changed to an enum or #define 1050185377Ssam */ 1051187831Ssam switch (chan->ic_flags & IEEE80211_CHAN_ALLFULL) { 1052187831Ssam case IEEE80211_CHAN_A: 1053187831Ssam if (freq > 4000 && freq < 5260) { 1054185377Ssam tempOB = ee->ee_ob1; 1055185377Ssam tempDB = ee->ee_db1; 1056187831Ssam } else if (freq >= 5260 && freq < 5500) { 1057185377Ssam tempOB = ee->ee_ob2; 1058185377Ssam tempDB = ee->ee_db2; 1059187831Ssam } else if (freq >= 5500 && freq < 5725) { 1060185377Ssam tempOB = ee->ee_ob3; 1061185377Ssam tempDB = ee->ee_db3; 1062187831Ssam } else if (freq >= 5725) { 1063185377Ssam tempOB = ee->ee_ob4; 1064185377Ssam tempDB = ee->ee_db4; 1065185377Ssam } else { 1066185377Ssam /* XXX panic?? */ 1067185377Ssam tempOB = tempDB = 0; 1068185377Ssam } 1069185377Ssam 1070185377Ssam rfXpdGain = ee->ee_xgain[0]; 1071185377Ssam rfPloSel = ee->ee_xpd[0]; 1072185377Ssam rfPwdXpd = !ee->ee_xpd[0]; 1073185377Ssam 1074185377Ssam ar5211Rf6n7[5][freqIndex] = 1075185377Ssam (ar5211Rf6n7[5][freqIndex] & ~0x10000000) | 1076185377Ssam (ee->ee_cornerCal.pd84<< 28); 1077185377Ssam ar5211Rf6n7[6][freqIndex] = 1078185377Ssam (ar5211Rf6n7[6][freqIndex] & ~0x04000000) | 1079185377Ssam (ee->ee_cornerCal.pd90 << 26); 1080185377Ssam ar5211Rf6n7[21][freqIndex] = 1081185377Ssam (ar5211Rf6n7[21][freqIndex] & ~0x08) | 1082185377Ssam (ee->ee_cornerCal.gSel << 3); 1083185377Ssam break; 1084187831Ssam case IEEE80211_CHAN_B: 1085185377Ssam tempOB = ee->ee_obFor24; 1086185377Ssam tempDB = ee->ee_dbFor24; 1087185377Ssam rfXpdGain = ee->ee_xgain[1]; 1088185377Ssam rfPloSel = ee->ee_xpd[1]; 1089185377Ssam rfPwdXpd = !ee->ee_xpd[1]; 1090185377Ssam break; 1091187831Ssam case IEEE80211_CHAN_PUREG: 1092185377Ssam tempOB = ee->ee_obFor24g; 1093185377Ssam tempDB = ee->ee_dbFor24g; 1094185377Ssam rfXpdGain = ee->ee_xgain[2]; 1095185377Ssam rfPloSel = ee->ee_xpd[2]; 1096185377Ssam rfPwdXpd = !ee->ee_xpd[2]; 1097185377Ssam break; 1098185377Ssam default: 1099185377Ssam HALDEBUG(ah, HAL_DEBUG_ANY, "%s: invalid channel flags 0x%x\n", 1100187831Ssam __func__, chan->ic_flags); 1101185377Ssam return AH_FALSE; 1102185377Ssam } 1103185377Ssam 1104185377Ssam HALASSERT(1 <= tempOB && tempOB <= 5); 1105185377Ssam HALASSERT(1 <= tempDB && tempDB <= 5); 1106185377Ssam 1107185377Ssam /* Set rfXpdGain and rfPwdXpd */ 1108185377Ssam ar5211Rf6n7[11][freqIndex] = (ar5211Rf6n7[11][freqIndex] & ~0xC0) | 1109185377Ssam (((ath_hal_reverseBits(rfXpdGain, 4) << 7) | (rfPwdXpd << 6)) & 0xC0); 1110185377Ssam ar5211Rf6n7[12][freqIndex] = (ar5211Rf6n7[12][freqIndex] & ~0x07) | 1111185377Ssam ((ath_hal_reverseBits(rfXpdGain, 4) >> 1) & 0x07); 1112185377Ssam 1113185377Ssam /* Set OB */ 1114185377Ssam ar5211Rf6n7[12][freqIndex] = (ar5211Rf6n7[12][freqIndex] & ~0x80) | 1115185377Ssam ((ath_hal_reverseBits(tempOB, 3) << 7) & 0x80); 1116185377Ssam ar5211Rf6n7[13][freqIndex] = (ar5211Rf6n7[13][freqIndex] & ~0x03) | 1117185377Ssam ((ath_hal_reverseBits(tempOB, 3) >> 1) & 0x03); 1118185377Ssam 1119185377Ssam /* Set DB */ 1120185377Ssam ar5211Rf6n7[13][freqIndex] = (ar5211Rf6n7[13][freqIndex] & ~0x1C) | 1121185377Ssam ((ath_hal_reverseBits(tempDB, 3) << 2) & 0x1C); 1122185377Ssam 1123185377Ssam /* Set rfPloSel */ 1124185377Ssam ar5211Rf6n7[17][freqIndex] = (ar5211Rf6n7[17][freqIndex] & ~0x08) | 1125185377Ssam ((rfPloSel << 3) & 0x08); 1126185377Ssam 1127185377Ssam /* Write the Rf registers 6 & 7 */ 1128185377Ssam for (i = 0; i < N(ar5211Rf6n7); i++) 1129185377Ssam OS_REG_WRITE(ah, ar5211Rf6n7[i][0], ar5211Rf6n7[i][freqIndex]); 1130185377Ssam 1131185377Ssam /* Now that we have reprogrammed rfgain value, clear the flag. */ 1132185377Ssam ahp->ah_rfgainState = RFGAIN_INACTIVE; 1133185377Ssam 1134185377Ssam return AH_TRUE; 1135185377Ssam#undef N 1136185377Ssam} 1137185377Ssam 1138185377SsamHAL_BOOL 1139185377Ssamar5211SetAntennaSwitchInternal(struct ath_hal *ah, HAL_ANT_SETTING settings, 1140187831Ssam const struct ieee80211_channel *chan) 1141185377Ssam{ 1142185377Ssam#define ANT_SWITCH_TABLE1 0x9960 1143185377Ssam#define ANT_SWITCH_TABLE2 0x9964 1144185377Ssam HAL_EEPROM *ee = AH_PRIVATE(ah)->ah_eeprom; 1145185377Ssam struct ath_hal_5211 *ahp = AH5211(ah); 1146185377Ssam uint32_t antSwitchA, antSwitchB; 1147185377Ssam int ix; 1148185377Ssam 1149187831Ssam switch (chan->ic_flags & IEEE80211_CHAN_ALLFULL) { 1150187831Ssam case IEEE80211_CHAN_A: ix = 0; break; 1151187831Ssam case IEEE80211_CHAN_B: ix = 1; break; 1152187831Ssam case IEEE80211_CHAN_PUREG: ix = 2; break; 1153185377Ssam default: 1154185377Ssam HALDEBUG(ah, HAL_DEBUG_ANY, "%s: invalid channel flags 0x%x\n", 1155187831Ssam __func__, chan->ic_flags); 1156185377Ssam return AH_FALSE; 1157185377Ssam } 1158185377Ssam 1159185377Ssam antSwitchA = ee->ee_antennaControl[1][ix] 1160185377Ssam | (ee->ee_antennaControl[2][ix] << 6) 1161185377Ssam | (ee->ee_antennaControl[3][ix] << 12) 1162185377Ssam | (ee->ee_antennaControl[4][ix] << 18) 1163185377Ssam | (ee->ee_antennaControl[5][ix] << 24) 1164185377Ssam ; 1165185377Ssam antSwitchB = ee->ee_antennaControl[6][ix] 1166185377Ssam | (ee->ee_antennaControl[7][ix] << 6) 1167185377Ssam | (ee->ee_antennaControl[8][ix] << 12) 1168185377Ssam | (ee->ee_antennaControl[9][ix] << 18) 1169185377Ssam | (ee->ee_antennaControl[10][ix] << 24) 1170185377Ssam ; 1171185377Ssam /* 1172185377Ssam * For fixed antenna, give the same setting for both switch banks 1173185377Ssam */ 1174185377Ssam switch (settings) { 1175185377Ssam case HAL_ANT_FIXED_A: 1176185377Ssam antSwitchB = antSwitchA; 1177185377Ssam break; 1178185377Ssam case HAL_ANT_FIXED_B: 1179185377Ssam antSwitchA = antSwitchB; 1180185377Ssam break; 1181185377Ssam case HAL_ANT_VARIABLE: 1182185377Ssam break; 1183185377Ssam default: 1184185377Ssam HALDEBUG(ah, HAL_DEBUG_ANY, "%s: bad antenna setting %u\n", 1185185377Ssam __func__, settings); 1186185377Ssam return AH_FALSE; 1187185377Ssam } 1188185377Ssam ahp->ah_diversityControl = settings; 1189185377Ssam 1190185377Ssam OS_REG_WRITE(ah, ANT_SWITCH_TABLE1, antSwitchA); 1191185377Ssam OS_REG_WRITE(ah, ANT_SWITCH_TABLE2, antSwitchB); 1192185377Ssam 1193185377Ssam return AH_TRUE; 1194185377Ssam#undef ANT_SWITCH_TABLE1 1195185377Ssam#undef ANT_SWITCH_TABLE2 1196185377Ssam} 1197185377Ssam 1198185377Ssam/* 1199185377Ssam * Reads EEPROM header info and programs the device for correct operation 1200185377Ssam * given the channel value 1201185377Ssam */ 1202185377Ssamstatic HAL_BOOL 1203187831Ssamar5211SetBoardValues(struct ath_hal *ah, const struct ieee80211_channel *chan) 1204185377Ssam{ 1205185377Ssam HAL_EEPROM *ee = AH_PRIVATE(ah)->ah_eeprom; 1206185377Ssam struct ath_hal_5211 *ahp = AH5211(ah); 1207185377Ssam int arrayMode, falseDectectBackoff; 1208185377Ssam 1209187831Ssam switch (chan->ic_flags & IEEE80211_CHAN_ALLFULL) { 1210187831Ssam case IEEE80211_CHAN_A: 1211185377Ssam arrayMode = 0; 1212185377Ssam OS_REG_RMW_FIELD(ah, AR_PHY_FRAME_CTL, 1213185377Ssam AR_PHY_FRAME_CTL_TX_CLIP, ee->ee_cornerCal.clip); 1214185377Ssam break; 1215187831Ssam case IEEE80211_CHAN_B: 1216185377Ssam arrayMode = 1; 1217185377Ssam break; 1218187831Ssam case IEEE80211_CHAN_PUREG: 1219185377Ssam arrayMode = 2; 1220185377Ssam break; 1221185377Ssam default: 1222185377Ssam HALDEBUG(ah, HAL_DEBUG_ANY, "%s: invalid channel flags 0x%x\n", 1223187831Ssam __func__, chan->ic_flags); 1224185377Ssam return AH_FALSE; 1225185377Ssam } 1226185377Ssam 1227185377Ssam /* Set the antenna register(s) correctly for the chip revision */ 1228185377Ssam if (AH_PRIVATE(ah)->ah_macVersion < AR_SREV_VERSION_OAHU) { 1229185377Ssam OS_REG_WRITE(ah, AR_PHY(68), 1230185377Ssam (OS_REG_READ(ah, AR_PHY(68)) & 0xFFFFFFFC) | 0x3); 1231185377Ssam } else { 1232185377Ssam OS_REG_WRITE(ah, AR_PHY(68), 1233185377Ssam (OS_REG_READ(ah, AR_PHY(68)) & 0xFFFFFC06) | 1234185377Ssam (ee->ee_antennaControl[0][arrayMode] << 4) | 0x1); 1235185377Ssam 1236185377Ssam ar5211SetAntennaSwitchInternal(ah, 1237185377Ssam ahp->ah_diversityControl, chan); 1238185377Ssam 1239185377Ssam /* Set the Noise Floor Thresh on ar5211 devices */ 1240185377Ssam OS_REG_WRITE(ah, AR_PHY_BASE + (90 << 2), 1241185377Ssam (ee->ee_noiseFloorThresh[arrayMode] & 0x1FF) | (1<<9)); 1242185377Ssam } 1243185377Ssam OS_REG_WRITE(ah, AR_PHY_BASE + (17 << 2), 1244185377Ssam (OS_REG_READ(ah, AR_PHY_BASE + (17 << 2)) & 0xFFFFC07F) | 1245185377Ssam ((ee->ee_switchSettling[arrayMode] << 7) & 0x3F80)); 1246185377Ssam OS_REG_WRITE(ah, AR_PHY_BASE + (18 << 2), 1247185377Ssam (OS_REG_READ(ah, AR_PHY_BASE + (18 << 2)) & 0xFFFC0FFF) | 1248185377Ssam ((ee->ee_txrxAtten[arrayMode] << 12) & 0x3F000)); 1249185377Ssam OS_REG_WRITE(ah, AR_PHY_BASE + (20 << 2), 1250185377Ssam (OS_REG_READ(ah, AR_PHY_BASE + (20 << 2)) & 0xFFFF0000) | 1251185377Ssam ((ee->ee_pgaDesiredSize[arrayMode] << 8) & 0xFF00) | 1252185377Ssam (ee->ee_adcDesiredSize[arrayMode] & 0x00FF)); 1253185377Ssam OS_REG_WRITE(ah, AR_PHY_BASE + (13 << 2), 1254185377Ssam (ee->ee_txEndToXPAOff[arrayMode] << 24) | 1255185377Ssam (ee->ee_txEndToXPAOff[arrayMode] << 16) | 1256185377Ssam (ee->ee_txFrameToXPAOn[arrayMode] << 8) | 1257185377Ssam ee->ee_txFrameToXPAOn[arrayMode]); 1258185377Ssam OS_REG_WRITE(ah, AR_PHY_BASE + (10 << 2), 1259185377Ssam (OS_REG_READ(ah, AR_PHY_BASE + (10 << 2)) & 0xFFFF00FF) | 1260185377Ssam (ee->ee_txEndToXLNAOn[arrayMode] << 8)); 1261185377Ssam OS_REG_WRITE(ah, AR_PHY_BASE + (25 << 2), 1262185377Ssam (OS_REG_READ(ah, AR_PHY_BASE + (25 << 2)) & 0xFFF80FFF) | 1263185377Ssam ((ee->ee_thresh62[arrayMode] << 12) & 0x7F000)); 1264185377Ssam 1265185377Ssam#define NO_FALSE_DETECT_BACKOFF 2 1266185377Ssam#define CB22_FALSE_DETECT_BACKOFF 6 1267185377Ssam /* 1268185377Ssam * False detect backoff - suspected 32 MHz spur causes 1269185377Ssam * false detects in OFDM, causing Tx Hangs. Decrease 1270185377Ssam * weak signal sensitivity for this card. 1271185377Ssam */ 1272185377Ssam falseDectectBackoff = NO_FALSE_DETECT_BACKOFF; 1273185377Ssam if (AH_PRIVATE(ah)->ah_eeversion < AR_EEPROM_VER3_3) { 1274185377Ssam if (AH_PRIVATE(ah)->ah_subvendorid == 0x1022 && 1275187831Ssam IEEE80211_IS_CHAN_OFDM(chan)) 1276185377Ssam falseDectectBackoff += CB22_FALSE_DETECT_BACKOFF; 1277185377Ssam } else { 1278187831Ssam uint16_t freq = ath_hal_gethwchannel(ah, chan); 1279187831Ssam uint32_t remainder = freq % 32; 1280185377Ssam 1281185377Ssam if (remainder && (remainder < 10 || remainder > 22)) 1282185377Ssam falseDectectBackoff += ee->ee_falseDetectBackoff[arrayMode]; 1283185377Ssam } 1284185377Ssam OS_REG_WRITE(ah, 0x9924, 1285185377Ssam (OS_REG_READ(ah, 0x9924) & 0xFFFFFF01) 1286185377Ssam | ((falseDectectBackoff << 1) & 0xF7)); 1287185377Ssam 1288185377Ssam return AH_TRUE; 1289185377Ssam#undef NO_FALSE_DETECT_BACKOFF 1290185377Ssam#undef CB22_FALSE_DETECT_BACKOFF 1291185377Ssam} 1292185377Ssam 1293185377Ssam/* 1294185377Ssam * Set the limit on the overall output power. Used for dynamic 1295185377Ssam * transmit power control and the like. 1296185377Ssam * 1297185377Ssam * NOTE: The power is passed in is in units of 0.5 dBm. 1298185377Ssam */ 1299185377SsamHAL_BOOL 1300185377Ssamar5211SetTxPowerLimit(struct ath_hal *ah, uint32_t limit) 1301185377Ssam{ 1302185377Ssam 1303185377Ssam AH_PRIVATE(ah)->ah_powerLimit = AH_MIN(limit, MAX_RATE_POWER); 1304185377Ssam OS_REG_WRITE(ah, AR_PHY_POWER_TX_RATE_MAX, limit); 1305185377Ssam return AH_TRUE; 1306185377Ssam} 1307185377Ssam 1308185377Ssam/* 1309185377Ssam * Sets the transmit power in the baseband for the given 1310185377Ssam * operating channel and mode. 1311185377Ssam */ 1312187831Ssamstatic HAL_BOOL 1313187831Ssamar5211SetTransmitPower(struct ath_hal *ah, const struct ieee80211_channel *chan) 1314185377Ssam{ 1315187831Ssam uint16_t freq = ath_hal_gethwchannel(ah, chan); 1316185377Ssam HAL_EEPROM *ee = AH_PRIVATE(ah)->ah_eeprom; 1317185377Ssam TRGT_POWER_INFO *pi; 1318185377Ssam RD_EDGES_POWER *rep; 1319185377Ssam PCDACS_EEPROM eepromPcdacs; 1320185377Ssam u_int nchan, cfgCtl; 1321185377Ssam int i; 1322185377Ssam 1323185377Ssam /* setup the pcdac struct to point to the correct info, based on mode */ 1324187831Ssam switch (chan->ic_flags & IEEE80211_CHAN_ALLFULL) { 1325187831Ssam case IEEE80211_CHAN_A: 1326185377Ssam eepromPcdacs.numChannels = ee->ee_numChannels11a; 1327185377Ssam eepromPcdacs.pChannelList= ee->ee_channels11a; 1328185377Ssam eepromPcdacs.pDataPerChannel = ee->ee_dataPerChannel11a; 1329185377Ssam nchan = ee->ee_numTargetPwr_11a; 1330185377Ssam pi = ee->ee_trgtPwr_11a; 1331185377Ssam break; 1332187831Ssam case IEEE80211_CHAN_PUREG: 1333185377Ssam eepromPcdacs.numChannels = ee->ee_numChannels2_4; 1334185377Ssam eepromPcdacs.pChannelList= ee->ee_channels11g; 1335185377Ssam eepromPcdacs.pDataPerChannel = ee->ee_dataPerChannel11g; 1336185377Ssam nchan = ee->ee_numTargetPwr_11g; 1337185377Ssam pi = ee->ee_trgtPwr_11g; 1338185377Ssam break; 1339187831Ssam case IEEE80211_CHAN_B: 1340185377Ssam eepromPcdacs.numChannels = ee->ee_numChannels2_4; 1341185377Ssam eepromPcdacs.pChannelList= ee->ee_channels11b; 1342185377Ssam eepromPcdacs.pDataPerChannel = ee->ee_dataPerChannel11b; 1343185377Ssam nchan = ee->ee_numTargetPwr_11b; 1344185377Ssam pi = ee->ee_trgtPwr_11b; 1345185377Ssam break; 1346185377Ssam default: 1347185377Ssam HALDEBUG(ah, HAL_DEBUG_ANY, "%s: invalid channel flags 0x%x\n", 1348187831Ssam __func__, chan->ic_flags); 1349185377Ssam return AH_FALSE; 1350185377Ssam } 1351185377Ssam 1352187831Ssam ar5211SetPowerTable(ah, &eepromPcdacs, freq); 1353185377Ssam 1354185377Ssam rep = AH_NULL; 1355185377Ssam /* Match CTL to EEPROM value */ 1356185377Ssam cfgCtl = ath_hal_getctl(ah, chan); 1357185377Ssam for (i = 0; i < ee->ee_numCtls; i++) 1358185377Ssam if (ee->ee_ctl[i] != 0 && ee->ee_ctl[i] == cfgCtl) { 1359185377Ssam rep = &ee->ee_rdEdgesPower[i * NUM_EDGES]; 1360185377Ssam break; 1361185377Ssam } 1362185377Ssam ar5211SetRateTable(ah, rep, pi, nchan, chan); 1363185377Ssam 1364185377Ssam return AH_TRUE; 1365185377Ssam} 1366185377Ssam 1367185377Ssam/* 1368185377Ssam * Read the transmit power levels from the structures taken 1369185377Ssam * from EEPROM. Interpolate read transmit power values for 1370185377Ssam * this channel. Organize the transmit power values into a 1371185377Ssam * table for writing into the hardware. 1372185377Ssam */ 1373185377Ssamvoid 1374187831Ssamar5211SetPowerTable(struct ath_hal *ah, PCDACS_EEPROM *pSrcStruct, 1375187831Ssam uint16_t channel) 1376185377Ssam{ 1377185377Ssam static FULL_PCDAC_STRUCT pcdacStruct; 1378185377Ssam static uint16_t pcdacTable[PWR_TABLE_SIZE]; 1379185377Ssam 1380185377Ssam uint16_t i, j; 1381185377Ssam uint16_t *pPcdacValues; 1382185377Ssam int16_t *pScaledUpDbm; 1383185377Ssam int16_t minScaledPwr; 1384185377Ssam int16_t maxScaledPwr; 1385185377Ssam int16_t pwr; 1386185377Ssam uint16_t pcdacMin = 0; 1387185377Ssam uint16_t pcdacMax = 63; 1388185377Ssam uint16_t pcdacTableIndex; 1389185377Ssam uint16_t scaledPcdac; 1390185377Ssam uint32_t addr; 1391185377Ssam uint32_t temp32; 1392185377Ssam 1393185377Ssam OS_MEMZERO(&pcdacStruct, sizeof(FULL_PCDAC_STRUCT)); 1394185377Ssam OS_MEMZERO(pcdacTable, sizeof(uint16_t) * PWR_TABLE_SIZE); 1395185377Ssam pPcdacValues = pcdacStruct.PcdacValues; 1396185377Ssam pScaledUpDbm = pcdacStruct.PwrValues; 1397185377Ssam 1398185377Ssam /* Initialize the pcdacs to dBM structs pcdacs to be 1 to 63 */ 1399185377Ssam for (i = PCDAC_START, j = 0; i <= PCDAC_STOP; i+= PCDAC_STEP, j++) 1400185377Ssam pPcdacValues[j] = i; 1401185377Ssam 1402185377Ssam pcdacStruct.numPcdacValues = j; 1403185377Ssam pcdacStruct.pcdacMin = PCDAC_START; 1404185377Ssam pcdacStruct.pcdacMax = PCDAC_STOP; 1405185377Ssam 1406185377Ssam /* Fill out the power values for this channel */ 1407185377Ssam for (j = 0; j < pcdacStruct.numPcdacValues; j++ ) 1408185377Ssam pScaledUpDbm[j] = ar5211GetScaledPower(channel, pPcdacValues[j], pSrcStruct); 1409185377Ssam 1410185377Ssam /* Now scale the pcdac values to fit in the 64 entry power table */ 1411185377Ssam minScaledPwr = pScaledUpDbm[0]; 1412185377Ssam maxScaledPwr = pScaledUpDbm[pcdacStruct.numPcdacValues - 1]; 1413185377Ssam 1414185377Ssam /* find minimum and make monotonic */ 1415185377Ssam for (j = 0; j < pcdacStruct.numPcdacValues; j++) { 1416185377Ssam if (minScaledPwr >= pScaledUpDbm[j]) { 1417185377Ssam minScaledPwr = pScaledUpDbm[j]; 1418185377Ssam pcdacMin = j; 1419185377Ssam } 1420185377Ssam /* 1421185377Ssam * Make the full_hsh monotonically increasing otherwise 1422185377Ssam * interpolation algorithm will get fooled gotta start 1423185377Ssam * working from the top, hence i = 63 - j. 1424185377Ssam */ 1425185377Ssam i = (uint16_t)(pcdacStruct.numPcdacValues - 1 - j); 1426185377Ssam if (i == 0) 1427185377Ssam break; 1428185377Ssam if (pScaledUpDbm[i-1] > pScaledUpDbm[i]) { 1429185377Ssam /* 1430185377Ssam * It could be a glitch, so make the power for 1431185377Ssam * this pcdac the same as the power from the 1432185377Ssam * next highest pcdac. 1433185377Ssam */ 1434185377Ssam pScaledUpDbm[i - 1] = pScaledUpDbm[i]; 1435185377Ssam } 1436185377Ssam } 1437185377Ssam 1438185377Ssam for (j = 0; j < pcdacStruct.numPcdacValues; j++) 1439185377Ssam if (maxScaledPwr < pScaledUpDbm[j]) { 1440185377Ssam maxScaledPwr = pScaledUpDbm[j]; 1441185377Ssam pcdacMax = j; 1442185377Ssam } 1443185377Ssam 1444185377Ssam /* Find the first power level with a pcdac */ 1445185377Ssam pwr = (uint16_t)(PWR_STEP * ((minScaledPwr - PWR_MIN + PWR_STEP / 2) / PWR_STEP) + PWR_MIN); 1446185377Ssam 1447185377Ssam /* Write all the first pcdac entries based off the pcdacMin */ 1448185377Ssam pcdacTableIndex = 0; 1449185377Ssam for (i = 0; i < (2 * (pwr - PWR_MIN) / EEP_SCALE + 1); i++) 1450185377Ssam pcdacTable[pcdacTableIndex++] = pcdacMin; 1451185377Ssam 1452185377Ssam i = 0; 1453185377Ssam while (pwr < pScaledUpDbm[pcdacStruct.numPcdacValues - 1]) { 1454185377Ssam pwr += PWR_STEP; 1455185377Ssam /* stop if dbM > max_power_possible */ 1456185377Ssam while (pwr < pScaledUpDbm[pcdacStruct.numPcdacValues - 1] && 1457185377Ssam (pwr - pScaledUpDbm[i])*(pwr - pScaledUpDbm[i+1]) > 0) 1458185377Ssam i++; 1459185377Ssam /* scale by 2 and add 1 to enable round up or down as needed */ 1460185377Ssam scaledPcdac = (uint16_t)(ar5211GetInterpolatedValue(pwr, 1461185377Ssam pScaledUpDbm[i], pScaledUpDbm[i+1], 1462185377Ssam (uint16_t)(pPcdacValues[i] * 2), 1463185377Ssam (uint16_t)(pPcdacValues[i+1] * 2), 0) + 1); 1464185377Ssam 1465185377Ssam pcdacTable[pcdacTableIndex] = scaledPcdac / 2; 1466185377Ssam if (pcdacTable[pcdacTableIndex] > pcdacMax) 1467185377Ssam pcdacTable[pcdacTableIndex] = pcdacMax; 1468185377Ssam pcdacTableIndex++; 1469185377Ssam } 1470185377Ssam 1471185377Ssam /* Write all the last pcdac entries based off the last valid pcdac */ 1472185377Ssam while (pcdacTableIndex < PWR_TABLE_SIZE) { 1473185377Ssam pcdacTable[pcdacTableIndex] = pcdacTable[pcdacTableIndex - 1]; 1474185377Ssam pcdacTableIndex++; 1475185377Ssam } 1476185377Ssam 1477185377Ssam /* Finally, write the power values into the baseband power table */ 1478185377Ssam addr = AR_PHY_BASE + (608 << 2); 1479185377Ssam for (i = 0; i < 32; i++) { 1480185377Ssam temp32 = 0xffff & ((pcdacTable[2 * i + 1] << 8) | 0xff); 1481185377Ssam temp32 = (temp32 << 16) | (0xffff & ((pcdacTable[2 * i] << 8) | 0xff)); 1482185377Ssam OS_REG_WRITE(ah, addr, temp32); 1483185377Ssam addr += 4; 1484185377Ssam } 1485185377Ssam 1486185377Ssam} 1487185377Ssam 1488185377Ssam/* 1489185377Ssam * Set the transmit power in the baseband for the given 1490185377Ssam * operating channel and mode. 1491185377Ssam */ 1492187831Ssamstatic void 1493185377Ssamar5211SetRateTable(struct ath_hal *ah, RD_EDGES_POWER *pRdEdgesPower, 1494185377Ssam TRGT_POWER_INFO *pPowerInfo, uint16_t numChannels, 1495187831Ssam const struct ieee80211_channel *chan) 1496185377Ssam{ 1497187831Ssam uint16_t freq = ath_hal_gethwchannel(ah, chan); 1498185377Ssam HAL_EEPROM *ee = AH_PRIVATE(ah)->ah_eeprom; 1499185377Ssam struct ath_hal_5211 *ahp = AH5211(ah); 1500185377Ssam static uint16_t ratesArray[NUM_RATES]; 1501185377Ssam static const uint16_t tpcScaleReductionTable[5] = 1502185377Ssam { 0, 3, 6, 9, MAX_RATE_POWER }; 1503185377Ssam 1504185377Ssam uint16_t *pRatesPower; 1505185377Ssam uint16_t lowerChannel, lowerIndex=0, lowerPower=0; 1506185377Ssam uint16_t upperChannel, upperIndex=0, upperPower=0; 1507185377Ssam uint16_t twiceMaxEdgePower=63; 1508185377Ssam uint16_t twicePower = 0; 1509185377Ssam uint16_t i, numEdges; 1510185377Ssam uint16_t tempChannelList[NUM_EDGES]; /* temp array for holding edge channels */ 1511185377Ssam uint16_t twiceMaxRDPower; 1512185377Ssam int16_t scaledPower = 0; /* for gcc -O2 */ 1513185377Ssam uint16_t mask = 0x3f; 1514185377Ssam HAL_BOOL paPreDEnable = 0; 1515185377Ssam int8_t twiceAntennaGain, twiceAntennaReduction = 0; 1516185377Ssam 1517185377Ssam pRatesPower = ratesArray; 1518187831Ssam twiceMaxRDPower = chan->ic_maxregpower * 2; 1519185377Ssam 1520187831Ssam if (IEEE80211_IS_CHAN_5GHZ(chan)) { 1521185377Ssam twiceAntennaGain = ee->ee_antennaGainMax[0]; 1522185377Ssam } else { 1523185377Ssam twiceAntennaGain = ee->ee_antennaGainMax[1]; 1524185377Ssam } 1525185377Ssam 1526185377Ssam twiceAntennaReduction = ath_hal_getantennareduction(ah, chan, twiceAntennaGain); 1527185377Ssam 1528185377Ssam if (pRdEdgesPower) { 1529185377Ssam /* Get the edge power */ 1530185377Ssam for (i = 0; i < NUM_EDGES; i++) { 1531185377Ssam if (pRdEdgesPower[i].rdEdge == 0) 1532185377Ssam break; 1533185377Ssam tempChannelList[i] = pRdEdgesPower[i].rdEdge; 1534185377Ssam } 1535185377Ssam numEdges = i; 1536185377Ssam 1537187831Ssam ar5211GetLowerUpperValues(freq, tempChannelList, 1538185377Ssam numEdges, &lowerChannel, &upperChannel); 1539185377Ssam /* Get the index for this channel */ 1540185377Ssam for (i = 0; i < numEdges; i++) 1541185377Ssam if (lowerChannel == tempChannelList[i]) 1542185377Ssam break; 1543185377Ssam HALASSERT(i != numEdges); 1544185377Ssam 1545185377Ssam if ((lowerChannel == upperChannel && 1546187831Ssam lowerChannel == freq) || 1547185377Ssam pRdEdgesPower[i].flag) { 1548185377Ssam twiceMaxEdgePower = pRdEdgesPower[i].twice_rdEdgePower; 1549185377Ssam HALASSERT(twiceMaxEdgePower > 0); 1550185377Ssam } 1551185377Ssam } 1552185377Ssam 1553185377Ssam /* extrapolate the power values for the test Groups */ 1554185377Ssam for (i = 0; i < numChannels; i++) 1555185377Ssam tempChannelList[i] = pPowerInfo[i].testChannel; 1556185377Ssam 1557187831Ssam ar5211GetLowerUpperValues(freq, tempChannelList, 1558185377Ssam numChannels, &lowerChannel, &upperChannel); 1559185377Ssam 1560185377Ssam /* get the index for the channel */ 1561185377Ssam for (i = 0; i < numChannels; i++) { 1562185377Ssam if (lowerChannel == tempChannelList[i]) 1563185377Ssam lowerIndex = i; 1564185377Ssam if (upperChannel == tempChannelList[i]) { 1565185377Ssam upperIndex = i; 1566185377Ssam break; 1567185377Ssam } 1568185377Ssam } 1569185377Ssam 1570185377Ssam for (i = 0; i < NUM_RATES; i++) { 1571187831Ssam if (IEEE80211_IS_CHAN_OFDM(chan)) { 1572185377Ssam /* power for rates 6,9,12,18,24 is all the same */ 1573185377Ssam if (i < 5) { 1574185377Ssam lowerPower = pPowerInfo[lowerIndex].twicePwr6_24; 1575185377Ssam upperPower = pPowerInfo[upperIndex].twicePwr6_24; 1576185377Ssam } else if (i == 5) { 1577185377Ssam lowerPower = pPowerInfo[lowerIndex].twicePwr36; 1578185377Ssam upperPower = pPowerInfo[upperIndex].twicePwr36; 1579185377Ssam } else if (i == 6) { 1580185377Ssam lowerPower = pPowerInfo[lowerIndex].twicePwr48; 1581185377Ssam upperPower = pPowerInfo[upperIndex].twicePwr48; 1582185377Ssam } else if (i == 7) { 1583185377Ssam lowerPower = pPowerInfo[lowerIndex].twicePwr54; 1584185377Ssam upperPower = pPowerInfo[upperIndex].twicePwr54; 1585185377Ssam } 1586185377Ssam } else { 1587185377Ssam switch (i) { 1588185377Ssam case 0: 1589185377Ssam case 1: 1590185377Ssam lowerPower = pPowerInfo[lowerIndex].twicePwr6_24; 1591185377Ssam upperPower = pPowerInfo[upperIndex].twicePwr6_24; 1592185377Ssam break; 1593185377Ssam case 2: 1594185377Ssam case 3: 1595185377Ssam lowerPower = pPowerInfo[lowerIndex].twicePwr36; 1596185377Ssam upperPower = pPowerInfo[upperIndex].twicePwr36; 1597185377Ssam break; 1598185377Ssam case 4: 1599185377Ssam case 5: 1600185377Ssam lowerPower = pPowerInfo[lowerIndex].twicePwr48; 1601185377Ssam upperPower = pPowerInfo[upperIndex].twicePwr48; 1602185377Ssam break; 1603185377Ssam case 6: 1604185377Ssam case 7: 1605185377Ssam lowerPower = pPowerInfo[lowerIndex].twicePwr54; 1606185377Ssam upperPower = pPowerInfo[upperIndex].twicePwr54; 1607185377Ssam break; 1608185377Ssam } 1609185377Ssam } 1610185377Ssam 1611187831Ssam twicePower = ar5211GetInterpolatedValue(freq, 1612185377Ssam lowerChannel, upperChannel, lowerPower, upperPower, 0); 1613185377Ssam 1614185377Ssam /* Reduce power by band edge restrictions */ 1615185377Ssam twicePower = AH_MIN(twicePower, twiceMaxEdgePower); 1616185377Ssam 1617185377Ssam /* 1618185377Ssam * If turbo is set, reduce power to keep power 1619185377Ssam * consumption under 2 Watts. Note that we always do 1620185377Ssam * this unless specially configured. Then we limit 1621185377Ssam * power only for non-AP operation. 1622185377Ssam */ 1623187831Ssam if (IEEE80211_IS_CHAN_TURBO(chan) && 1624185377Ssam AH_PRIVATE(ah)->ah_eeversion >= AR_EEPROM_VER3_1 1625185377Ssam#ifdef AH_ENABLE_AP_SUPPORT 1626185377Ssam && AH_PRIVATE(ah)->ah_opmode != HAL_M_HOSTAP 1627185377Ssam#endif 1628185377Ssam ) { 1629185377Ssam twicePower = AH_MIN(twicePower, ee->ee_turbo2WMaxPower5); 1630185377Ssam } 1631185377Ssam 1632185377Ssam /* Reduce power by max regulatory domain allowed restrictions */ 1633185377Ssam pRatesPower[i] = AH_MIN(twicePower, twiceMaxRDPower - twiceAntennaReduction); 1634185377Ssam 1635185377Ssam /* Use 6 Mb power level for transmit power scaling reduction */ 1636185377Ssam /* We don't want to reduce higher rates if its not needed */ 1637185377Ssam if (i == 0) { 1638185377Ssam scaledPower = pRatesPower[0] - 1639185377Ssam (tpcScaleReductionTable[AH_PRIVATE(ah)->ah_tpScale] * 2); 1640185377Ssam if (scaledPower < 1) 1641185377Ssam scaledPower = 1; 1642185377Ssam } 1643185377Ssam 1644185377Ssam pRatesPower[i] = AH_MIN(pRatesPower[i], scaledPower); 1645185377Ssam } 1646185377Ssam 1647185377Ssam /* Record txPower at Rate 6 for info gathering */ 1648185377Ssam ahp->ah_tx6PowerInHalfDbm = pRatesPower[0]; 1649185377Ssam 1650185377Ssam#ifdef AH_DEBUG 1651185377Ssam HALDEBUG(ah, HAL_DEBUG_RESET, 1652185377Ssam "%s: final output power setting %d MHz:\n", 1653187831Ssam __func__, chan->ic_freq); 1654185377Ssam HALDEBUG(ah, HAL_DEBUG_RESET, 1655185377Ssam "6 Mb %d dBm, MaxRD: %d dBm, MaxEdge %d dBm\n", 1656185377Ssam scaledPower / 2, twiceMaxRDPower / 2, twiceMaxEdgePower / 2); 1657185377Ssam HALDEBUG(ah, HAL_DEBUG_RESET, "TPC Scale %d dBm - Ant Red %d dBm\n", 1658185377Ssam tpcScaleReductionTable[AH_PRIVATE(ah)->ah_tpScale] * 2, 1659185377Ssam twiceAntennaReduction / 2); 1660187831Ssam if (IEEE80211_IS_CHAN_TURBO(chan) && 1661185377Ssam AH_PRIVATE(ah)->ah_eeversion >= AR_EEPROM_VER3_1) 1662185377Ssam HALDEBUG(ah, HAL_DEBUG_RESET, "Max Turbo %d dBm\n", 1663185377Ssam ee->ee_turbo2WMaxPower5); 1664185377Ssam HALDEBUG(ah, HAL_DEBUG_RESET, 1665185377Ssam " %2d | %2d | %2d | %2d | %2d | %2d | %2d | %2d dBm\n", 1666185377Ssam pRatesPower[0] / 2, pRatesPower[1] / 2, pRatesPower[2] / 2, 1667185377Ssam pRatesPower[3] / 2, pRatesPower[4] / 2, pRatesPower[5] / 2, 1668185377Ssam pRatesPower[6] / 2, pRatesPower[7] / 2); 1669185377Ssam#endif /* AH_DEBUG */ 1670185377Ssam 1671185377Ssam /* Write the power table into the hardware */ 1672185377Ssam OS_REG_WRITE(ah, AR_PHY_POWER_TX_RATE1, 1673185377Ssam ((paPreDEnable & 1)<< 30) | ((pRatesPower[3] & mask) << 24) | 1674185377Ssam ((paPreDEnable & 1)<< 22) | ((pRatesPower[2] & mask) << 16) | 1675185377Ssam ((paPreDEnable & 1)<< 14) | ((pRatesPower[1] & mask) << 8) | 1676185377Ssam ((paPreDEnable & 1)<< 6 ) | (pRatesPower[0] & mask)); 1677185377Ssam OS_REG_WRITE(ah, AR_PHY_POWER_TX_RATE2, 1678185377Ssam ((paPreDEnable & 1)<< 30) | ((pRatesPower[7] & mask) << 24) | 1679185377Ssam ((paPreDEnable & 1)<< 22) | ((pRatesPower[6] & mask) << 16) | 1680185377Ssam ((paPreDEnable & 1)<< 14) | ((pRatesPower[5] & mask) << 8) | 1681185377Ssam ((paPreDEnable & 1)<< 6 ) | (pRatesPower[4] & mask)); 1682185377Ssam 1683185377Ssam /* set max power to the power value at rate 6 */ 1684185377Ssam ar5211SetTxPowerLimit(ah, pRatesPower[0]); 1685185377Ssam 1686185377Ssam AH_PRIVATE(ah)->ah_maxPowerLevel = pRatesPower[0]; 1687185377Ssam} 1688185377Ssam 1689185377Ssam/* 1690185377Ssam * Get or interpolate the pcdac value from the calibrated data 1691185377Ssam */ 1692185377Ssamuint16_t 1693187831Ssamar5211GetScaledPower(uint16_t channel, uint16_t pcdacValue, 1694187831Ssam const PCDACS_EEPROM *pSrcStruct) 1695185377Ssam{ 1696185377Ssam uint16_t powerValue; 1697185377Ssam uint16_t lFreq, rFreq; /* left and right frequency values */ 1698185377Ssam uint16_t llPcdac, ulPcdac; /* lower and upper left pcdac values */ 1699185377Ssam uint16_t lrPcdac, urPcdac; /* lower and upper right pcdac values */ 1700185377Ssam uint16_t lPwr, uPwr; /* lower and upper temp pwr values */ 1701185377Ssam uint16_t lScaledPwr, rScaledPwr; /* left and right scaled power */ 1702185377Ssam 1703185377Ssam if (ar5211FindValueInList(channel, pcdacValue, pSrcStruct, &powerValue)) 1704185377Ssam /* value was copied from srcStruct */ 1705185377Ssam return powerValue; 1706185377Ssam 1707185377Ssam ar5211GetLowerUpperValues(channel, pSrcStruct->pChannelList, 1708185377Ssam pSrcStruct->numChannels, &lFreq, &rFreq); 1709185377Ssam ar5211GetLowerUpperPcdacs(pcdacValue, lFreq, pSrcStruct, 1710185377Ssam &llPcdac, &ulPcdac); 1711185377Ssam ar5211GetLowerUpperPcdacs(pcdacValue, rFreq, pSrcStruct, 1712185377Ssam &lrPcdac, &urPcdac); 1713185377Ssam 1714185377Ssam /* get the power index for the pcdac value */ 1715185377Ssam ar5211FindValueInList(lFreq, llPcdac, pSrcStruct, &lPwr); 1716185377Ssam ar5211FindValueInList(lFreq, ulPcdac, pSrcStruct, &uPwr); 1717185377Ssam lScaledPwr = ar5211GetInterpolatedValue(pcdacValue, 1718185377Ssam llPcdac, ulPcdac, lPwr, uPwr, 0); 1719185377Ssam 1720185377Ssam ar5211FindValueInList(rFreq, lrPcdac, pSrcStruct, &lPwr); 1721185377Ssam ar5211FindValueInList(rFreq, urPcdac, pSrcStruct, &uPwr); 1722185377Ssam rScaledPwr = ar5211GetInterpolatedValue(pcdacValue, 1723185377Ssam lrPcdac, urPcdac, lPwr, uPwr, 0); 1724185377Ssam 1725185377Ssam return ar5211GetInterpolatedValue(channel, lFreq, rFreq, 1726185377Ssam lScaledPwr, rScaledPwr, 0); 1727185377Ssam} 1728185377Ssam 1729185377Ssam/* 1730185377Ssam * Find the value from the calibrated source data struct 1731185377Ssam */ 1732185377SsamHAL_BOOL 1733185377Ssamar5211FindValueInList(uint16_t channel, uint16_t pcdacValue, 1734185377Ssam const PCDACS_EEPROM *pSrcStruct, uint16_t *powerValue) 1735185377Ssam{ 1736185377Ssam const DATA_PER_CHANNEL *pChannelData; 1737185377Ssam const uint16_t *pPcdac; 1738185377Ssam uint16_t i, j; 1739185377Ssam 1740185377Ssam pChannelData = pSrcStruct->pDataPerChannel; 1741185377Ssam for (i = 0; i < pSrcStruct->numChannels; i++ ) { 1742185377Ssam if (pChannelData->channelValue == channel) { 1743185377Ssam pPcdac = pChannelData->PcdacValues; 1744185377Ssam for (j = 0; j < pChannelData->numPcdacValues; j++ ) { 1745185377Ssam if (*pPcdac == pcdacValue) { 1746185377Ssam *powerValue = pChannelData->PwrValues[j]; 1747185377Ssam return AH_TRUE; 1748185377Ssam } 1749185377Ssam pPcdac++; 1750185377Ssam } 1751185377Ssam } 1752185377Ssam pChannelData++; 1753185377Ssam } 1754185377Ssam return AH_FALSE; 1755185377Ssam} 1756185377Ssam 1757185377Ssam/* 1758185377Ssam * Returns interpolated or the scaled up interpolated value 1759185377Ssam */ 1760185377Ssamuint16_t 1761185377Ssamar5211GetInterpolatedValue(uint16_t target, 1762185377Ssam uint16_t srcLeft, uint16_t srcRight, 1763185377Ssam uint16_t targetLeft, uint16_t targetRight, 1764185377Ssam HAL_BOOL scaleUp) 1765185377Ssam{ 1766185377Ssam uint16_t rv; 1767185377Ssam int16_t lRatio; 1768185377Ssam uint16_t scaleValue = EEP_SCALE; 1769185377Ssam 1770185377Ssam /* to get an accurate ratio, always scale, if want to scale, then don't scale back down */ 1771185377Ssam if ((targetLeft * targetRight) == 0) 1772185377Ssam return 0; 1773185377Ssam if (scaleUp) 1774185377Ssam scaleValue = 1; 1775185377Ssam 1776185377Ssam if (srcRight != srcLeft) { 1777185377Ssam /* 1778185377Ssam * Note the ratio always need to be scaled, 1779185377Ssam * since it will be a fraction. 1780185377Ssam */ 1781185377Ssam lRatio = (target - srcLeft) * EEP_SCALE / (srcRight - srcLeft); 1782185377Ssam if (lRatio < 0) { 1783185377Ssam /* Return as Left target if value would be negative */ 1784185377Ssam rv = targetLeft * (scaleUp ? EEP_SCALE : 1); 1785185377Ssam } else if (lRatio > EEP_SCALE) { 1786185377Ssam /* Return as Right target if Ratio is greater than 100% (SCALE) */ 1787185377Ssam rv = targetRight * (scaleUp ? EEP_SCALE : 1); 1788185377Ssam } else { 1789185377Ssam rv = (lRatio * targetRight + (EEP_SCALE - lRatio) * 1790185377Ssam targetLeft) / scaleValue; 1791185377Ssam } 1792185377Ssam } else { 1793185377Ssam rv = targetLeft; 1794185377Ssam if (scaleUp) 1795185377Ssam rv *= EEP_SCALE; 1796185377Ssam } 1797185377Ssam return rv; 1798185377Ssam} 1799185377Ssam 1800185377Ssam/* 1801185377Ssam * Look for value being within 0.1 of the search values 1802185377Ssam * however, NDIS can't do float calculations, so multiply everything 1803185377Ssam * up by EEP_SCALE so can do integer arithmatic 1804185377Ssam * 1805185377Ssam * INPUT value -value to search for 1806185377Ssam * INPUT pList -ptr to the list to search 1807185377Ssam * INPUT listSize -number of entries in list 1808185377Ssam * OUTPUT pLowerValue -return the lower value 1809185377Ssam * OUTPUT pUpperValue -return the upper value 1810185377Ssam */ 1811185377Ssamvoid 1812185377Ssamar5211GetLowerUpperValues(uint16_t value, 1813185377Ssam const uint16_t *pList, uint16_t listSize, 1814185377Ssam uint16_t *pLowerValue, uint16_t *pUpperValue) 1815185377Ssam{ 1816185377Ssam const uint16_t listEndValue = *(pList + listSize - 1); 1817185377Ssam uint32_t target = value * EEP_SCALE; 1818185377Ssam int i; 1819185377Ssam 1820185377Ssam /* 1821185377Ssam * See if value is lower than the first value in the list 1822185377Ssam * if so return first value 1823185377Ssam */ 1824185377Ssam if (target < (uint32_t)(*pList * EEP_SCALE - EEP_DELTA)) { 1825185377Ssam *pLowerValue = *pList; 1826185377Ssam *pUpperValue = *pList; 1827185377Ssam return; 1828185377Ssam } 1829185377Ssam 1830185377Ssam /* 1831185377Ssam * See if value is greater than last value in list 1832185377Ssam * if so return last value 1833185377Ssam */ 1834185377Ssam if (target > (uint32_t)(listEndValue * EEP_SCALE + EEP_DELTA)) { 1835185377Ssam *pLowerValue = listEndValue; 1836185377Ssam *pUpperValue = listEndValue; 1837185377Ssam return; 1838185377Ssam } 1839185377Ssam 1840185377Ssam /* look for value being near or between 2 values in list */ 1841185377Ssam for (i = 0; i < listSize; i++) { 1842185377Ssam /* 1843185377Ssam * If value is close to the current value of the list 1844185377Ssam * then target is not between values, it is one of the values 1845185377Ssam */ 1846185377Ssam if (abs(pList[i] * EEP_SCALE - (int32_t) target) < EEP_DELTA) { 1847185377Ssam *pLowerValue = pList[i]; 1848185377Ssam *pUpperValue = pList[i]; 1849185377Ssam return; 1850185377Ssam } 1851185377Ssam 1852185377Ssam /* 1853185377Ssam * Look for value being between current value and next value 1854185377Ssam * if so return these 2 values 1855185377Ssam */ 1856185377Ssam if (target < (uint32_t)(pList[i + 1] * EEP_SCALE - EEP_DELTA)) { 1857185377Ssam *pLowerValue = pList[i]; 1858185377Ssam *pUpperValue = pList[i + 1]; 1859185377Ssam return; 1860185377Ssam } 1861185377Ssam } 1862185377Ssam} 1863185377Ssam 1864185377Ssam/* 1865185377Ssam * Get the upper and lower pcdac given the channel and the pcdac 1866185377Ssam * used in the search 1867185377Ssam */ 1868185377Ssamvoid 1869185377Ssamar5211GetLowerUpperPcdacs(uint16_t pcdac, uint16_t channel, 1870185377Ssam const PCDACS_EEPROM *pSrcStruct, 1871185377Ssam uint16_t *pLowerPcdac, uint16_t *pUpperPcdac) 1872185377Ssam{ 1873185377Ssam const DATA_PER_CHANNEL *pChannelData; 1874185377Ssam int i; 1875185377Ssam 1876185377Ssam /* Find the channel information */ 1877185377Ssam pChannelData = pSrcStruct->pDataPerChannel; 1878185377Ssam for (i = 0; i < pSrcStruct->numChannels; i++) { 1879185377Ssam if (pChannelData->channelValue == channel) 1880185377Ssam break; 1881185377Ssam pChannelData++; 1882185377Ssam } 1883185377Ssam ar5211GetLowerUpperValues(pcdac, pChannelData->PcdacValues, 1884185377Ssam pChannelData->numPcdacValues, pLowerPcdac, pUpperPcdac); 1885185377Ssam} 1886185377Ssam 1887185377Ssam#define DYN_ADJ_UP_MARGIN 15 1888185377Ssam#define DYN_ADJ_LO_MARGIN 20 1889185377Ssam 1890185377Ssamstatic const GAIN_OPTIMIZATION_LADDER gainLadder = { 1891185377Ssam 9, /* numStepsInLadder */ 1892185377Ssam 4, /* defaultStepNum */ 1893185377Ssam { { {4, 1, 1, 1}, 6, "FG8"}, 1894185377Ssam { {4, 0, 1, 1}, 4, "FG7"}, 1895185377Ssam { {3, 1, 1, 1}, 3, "FG6"}, 1896185377Ssam { {4, 0, 0, 1}, 1, "FG5"}, 1897185377Ssam { {4, 1, 1, 0}, 0, "FG4"}, /* noJack */ 1898185377Ssam { {4, 0, 1, 0}, -2, "FG3"}, /* halfJack */ 1899185377Ssam { {3, 1, 1, 0}, -3, "FG2"}, /* clip3 */ 1900185377Ssam { {4, 0, 0, 0}, -4, "FG1"}, /* noJack */ 1901185377Ssam { {2, 1, 1, 0}, -6, "FG0"} /* clip2 */ 1902185377Ssam } 1903185377Ssam}; 1904185377Ssam 1905185377Ssam/* 1906185377Ssam * Initialize the gain structure to good values 1907185377Ssam */ 1908185377Ssamvoid 1909185377Ssamar5211InitializeGainValues(struct ath_hal *ah) 1910185377Ssam{ 1911185377Ssam struct ath_hal_5211 *ahp = AH5211(ah); 1912185377Ssam GAIN_VALUES *gv = &ahp->ah_gainValues; 1913185377Ssam 1914185377Ssam /* initialize gain optimization values */ 1915185377Ssam gv->currStepNum = gainLadder.defaultStepNum; 1916185377Ssam gv->currStep = &gainLadder.optStep[gainLadder.defaultStepNum]; 1917185377Ssam gv->active = AH_TRUE; 1918185377Ssam gv->loTrig = 20; 1919185377Ssam gv->hiTrig = 35; 1920185377Ssam} 1921185377Ssam 1922185377Ssamstatic HAL_BOOL 1923185377Ssamar5211InvalidGainReadback(struct ath_hal *ah, GAIN_VALUES *gv) 1924185377Ssam{ 1925187831Ssam const struct ieee80211_channel *chan = AH_PRIVATE(ah)->ah_curchan; 1926185377Ssam uint32_t gStep, g; 1927185377Ssam uint32_t L1, L2, L3, L4; 1928185377Ssam 1929187831Ssam if (IEEE80211_IS_CHAN_CCK(chan)) { 1930185377Ssam gStep = 0x18; 1931185377Ssam L1 = 0; 1932185377Ssam L2 = gStep + 4; 1933185377Ssam L3 = 0x40; 1934185377Ssam L4 = L3 + 50; 1935185377Ssam 1936185377Ssam gv->loTrig = L1; 1937185377Ssam gv->hiTrig = L4+5; 1938185377Ssam } else { 1939185377Ssam gStep = 0x3f; 1940185377Ssam L1 = 0; 1941185377Ssam L2 = 50; 1942185377Ssam L3 = L1; 1943185377Ssam L4 = L3 + 50; 1944185377Ssam 1945185377Ssam gv->loTrig = L1 + DYN_ADJ_LO_MARGIN; 1946185377Ssam gv->hiTrig = L4 - DYN_ADJ_UP_MARGIN; 1947185377Ssam } 1948185377Ssam g = gv->currGain; 1949185377Ssam 1950185377Ssam return !((g >= L1 && g<= L2) || (g >= L3 && g <= L4)); 1951185377Ssam} 1952185377Ssam 1953185377Ssam/* 1954185377Ssam * Enable the probe gain check on the next packet 1955185377Ssam */ 1956185377Ssamstatic void 1957185377Ssamar5211RequestRfgain(struct ath_hal *ah) 1958185377Ssam{ 1959185377Ssam struct ath_hal_5211 *ahp = AH5211(ah); 1960185377Ssam 1961185377Ssam /* Enable the gain readback probe */ 1962185377Ssam OS_REG_WRITE(ah, AR_PHY_PAPD_PROBE, 1963185377Ssam SM(ahp->ah_tx6PowerInHalfDbm, AR_PHY_PAPD_PROBE_POWERTX) 1964185377Ssam | AR_PHY_PAPD_PROBE_NEXT_TX); 1965185377Ssam 1966185377Ssam ahp->ah_rfgainState = HAL_RFGAIN_READ_REQUESTED; 1967185377Ssam} 1968185377Ssam 1969185377Ssam/* 1970185377Ssam * Exported call to check for a recent gain reading and return 1971185377Ssam * the current state of the thermal calibration gain engine. 1972185377Ssam */ 1973185377SsamHAL_RFGAIN 1974185377Ssamar5211GetRfgain(struct ath_hal *ah) 1975185377Ssam{ 1976185377Ssam struct ath_hal_5211 *ahp = AH5211(ah); 1977185377Ssam GAIN_VALUES *gv = &ahp->ah_gainValues; 1978185377Ssam uint32_t rddata; 1979185377Ssam 1980185377Ssam if (!gv->active) 1981185377Ssam return HAL_RFGAIN_INACTIVE; 1982185377Ssam 1983185377Ssam if (ahp->ah_rfgainState == HAL_RFGAIN_READ_REQUESTED) { 1984185377Ssam /* Caller had asked to setup a new reading. Check it. */ 1985185377Ssam rddata = OS_REG_READ(ah, AR_PHY_PAPD_PROBE); 1986185377Ssam 1987185377Ssam if ((rddata & AR_PHY_PAPD_PROBE_NEXT_TX) == 0) { 1988185377Ssam /* bit got cleared, we have a new reading. */ 1989185377Ssam gv->currGain = rddata >> AR_PHY_PAPD_PROBE_GAINF_S; 1990185377Ssam /* inactive by default */ 1991185377Ssam ahp->ah_rfgainState = HAL_RFGAIN_INACTIVE; 1992185377Ssam 1993185377Ssam if (!ar5211InvalidGainReadback(ah, gv) && 1994185377Ssam ar5211IsGainAdjustNeeded(ah, gv) && 1995185377Ssam ar5211AdjustGain(ah, gv) > 0) { 1996185377Ssam /* 1997185377Ssam * Change needed. Copy ladder info 1998185377Ssam * into eeprom info. 1999185377Ssam */ 2000185377Ssam ar5211SetRfgain(ah, gv); 2001185377Ssam ahp->ah_rfgainState = HAL_RFGAIN_NEED_CHANGE; 2002185377Ssam } 2003185377Ssam } 2004185377Ssam } 2005185377Ssam return ahp->ah_rfgainState; 2006185377Ssam} 2007185377Ssam 2008185377Ssam/* 2009185377Ssam * Check to see if our readback gain level sits within the linear 2010185377Ssam * region of our current variable attenuation window 2011185377Ssam */ 2012185377Ssamstatic HAL_BOOL 2013185377Ssamar5211IsGainAdjustNeeded(struct ath_hal *ah, const GAIN_VALUES *gv) 2014185377Ssam{ 2015185377Ssam return (gv->currGain <= gv->loTrig || gv->currGain >= gv->hiTrig); 2016185377Ssam} 2017185377Ssam 2018185377Ssam/* 2019185377Ssam * Move the rabbit ears in the correct direction. 2020185377Ssam */ 2021185377Ssamstatic int32_t 2022185377Ssamar5211AdjustGain(struct ath_hal *ah, GAIN_VALUES *gv) 2023185377Ssam{ 2024185377Ssam /* return > 0 for valid adjustments. */ 2025185377Ssam if (!gv->active) 2026185377Ssam return -1; 2027185377Ssam 2028185377Ssam gv->currStep = &gainLadder.optStep[gv->currStepNum]; 2029185377Ssam if (gv->currGain >= gv->hiTrig) { 2030185377Ssam if (gv->currStepNum == 0) { 2031185377Ssam HALDEBUG(ah, HAL_DEBUG_RFPARAM, 2032185377Ssam "%s: Max gain limit.\n", __func__); 2033185377Ssam return -1; 2034185377Ssam } 2035185377Ssam HALDEBUG(ah, HAL_DEBUG_RFPARAM, 2036185377Ssam "%s: Adding gain: currG=%d [%s] --> ", 2037185377Ssam __func__, gv->currGain, gv->currStep->stepName); 2038185377Ssam gv->targetGain = gv->currGain; 2039185377Ssam while (gv->targetGain >= gv->hiTrig && gv->currStepNum > 0) { 2040185377Ssam gv->targetGain -= 2 * (gainLadder.optStep[--(gv->currStepNum)].stepGain - 2041185377Ssam gv->currStep->stepGain); 2042185377Ssam gv->currStep = &gainLadder.optStep[gv->currStepNum]; 2043185377Ssam } 2044185377Ssam HALDEBUG(ah, HAL_DEBUG_RFPARAM, "targG=%d [%s]\n", 2045185377Ssam gv->targetGain, gv->currStep->stepName); 2046185377Ssam return 1; 2047185377Ssam } 2048185377Ssam if (gv->currGain <= gv->loTrig) { 2049185377Ssam if (gv->currStepNum == gainLadder.numStepsInLadder-1) { 2050185377Ssam HALDEBUG(ah, HAL_DEBUG_RFPARAM, 2051185377Ssam "%s: Min gain limit.\n", __func__); 2052185377Ssam return -2; 2053185377Ssam } 2054185377Ssam HALDEBUG(ah, HAL_DEBUG_RFPARAM, 2055185377Ssam "%s: Deducting gain: currG=%d [%s] --> ", 2056185377Ssam __func__, gv->currGain, gv->currStep->stepName); 2057185377Ssam gv->targetGain = gv->currGain; 2058185377Ssam while (gv->targetGain <= gv->loTrig && 2059185377Ssam gv->currStepNum < (gainLadder.numStepsInLadder - 1)) { 2060185377Ssam gv->targetGain -= 2 * 2061185377Ssam (gainLadder.optStep[++(gv->currStepNum)].stepGain - gv->currStep->stepGain); 2062185377Ssam gv->currStep = &gainLadder.optStep[gv->currStepNum]; 2063185377Ssam } 2064185377Ssam HALDEBUG(ah, HAL_DEBUG_RFPARAM, "targG=%d [%s]\n", 2065185377Ssam gv->targetGain, gv->currStep->stepName); 2066185377Ssam return 2; 2067185377Ssam } 2068185377Ssam return 0; /* caller didn't call needAdjGain first */ 2069185377Ssam} 2070185377Ssam 2071185377Ssam/* 2072185377Ssam * Adjust the 5GHz EEPROM information with the desired calibration values. 2073185377Ssam */ 2074185377Ssamstatic void 2075185377Ssamar5211SetRfgain(struct ath_hal *ah, const GAIN_VALUES *gv) 2076185377Ssam{ 2077185377Ssam HAL_EEPROM *ee = AH_PRIVATE(ah)->ah_eeprom; 2078185377Ssam 2079185377Ssam if (!gv->active) 2080185377Ssam return; 2081185377Ssam ee->ee_cornerCal.clip = gv->currStep->paramVal[0]; /* bb_tx_clip */ 2082185377Ssam ee->ee_cornerCal.pd90 = gv->currStep->paramVal[1]; /* rf_pwd_90 */ 2083185377Ssam ee->ee_cornerCal.pd84 = gv->currStep->paramVal[2]; /* rf_pwd_84 */ 2084185377Ssam ee->ee_cornerCal.gSel = gv->currStep->paramVal[3]; /* rf_rfgainsel */ 2085185377Ssam} 2086185377Ssam 2087185377Ssamstatic void 2088185377Ssamar5211SetOperatingMode(struct ath_hal *ah, int opmode) 2089185377Ssam{ 2090185377Ssam struct ath_hal_5211 *ahp = AH5211(ah); 2091185377Ssam uint32_t val; 2092185377Ssam 2093185377Ssam val = OS_REG_READ(ah, AR_STA_ID1) & 0xffff; 2094185377Ssam switch (opmode) { 2095185377Ssam case HAL_M_HOSTAP: 2096185377Ssam OS_REG_WRITE(ah, AR_STA_ID1, val 2097185377Ssam | AR_STA_ID1_STA_AP 2098185377Ssam | AR_STA_ID1_RTS_USE_DEF 2099185377Ssam | ahp->ah_staId1Defaults); 2100185377Ssam break; 2101185377Ssam case HAL_M_IBSS: 2102185377Ssam OS_REG_WRITE(ah, AR_STA_ID1, val 2103185377Ssam | AR_STA_ID1_ADHOC 2104185377Ssam | AR_STA_ID1_DESC_ANTENNA 2105185377Ssam | ahp->ah_staId1Defaults); 2106185377Ssam break; 2107185377Ssam case HAL_M_STA: 2108185377Ssam case HAL_M_MONITOR: 2109185377Ssam OS_REG_WRITE(ah, AR_STA_ID1, val 2110185377Ssam | AR_STA_ID1_DEFAULT_ANTENNA 2111185377Ssam | ahp->ah_staId1Defaults); 2112185377Ssam break; 2113185377Ssam } 2114185377Ssam} 2115185377Ssam 2116185377Ssamvoid 2117185377Ssamar5211SetPCUConfig(struct ath_hal *ah) 2118185377Ssam{ 2119185377Ssam ar5211SetOperatingMode(ah, AH_PRIVATE(ah)->ah_opmode); 2120185377Ssam} 2121