1293010Sadrian/* $OpenBSD: if_rtwn.c,v 1.6 2015/08/28 00:03:53 deraadt Exp $ */ 2293010Sadrian 3293010Sadrian/*- 4293010Sadrian * Copyright (c) 2010 Damien Bergamini <damien.bergamini@free.fr> 5293010Sadrian * Copyright (c) 2015 Stefan Sperling <stsp@openbsd.org> 6293010Sadrian * 7293010Sadrian * Permission to use, copy, modify, and distribute this software for any 8293010Sadrian * purpose with or without fee is hereby granted, provided that the above 9293010Sadrian * copyright notice and this permission notice appear in all copies. 10293010Sadrian * 11293010Sadrian * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES 12293010Sadrian * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF 13293010Sadrian * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR 14293010Sadrian * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES 15293010Sadrian * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN 16293010Sadrian * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF 17293010Sadrian * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. 18293010Sadrian */ 19293010Sadrian 20293010Sadrian#include <sys/cdefs.h> 21293010Sadrian__FBSDID("$FreeBSD: stable/11/sys/dev/rtwn/if_rtwn.c 345636 2019-03-28 09:50:25Z avos $"); 22293010Sadrian 23293010Sadrian/* 24293010Sadrian * Driver for Realtek RTL8188CE 25293010Sadrian */ 26293010Sadrian 27293010Sadrian#include <sys/param.h> 28293010Sadrian#include <sys/sysctl.h> 29293010Sadrian#include <sys/sockio.h> 30293010Sadrian#include <sys/mbuf.h> 31293010Sadrian#include <sys/kernel.h> 32293010Sadrian#include <sys/socket.h> 33293010Sadrian#include <sys/systm.h> 34293010Sadrian#include <sys/malloc.h> 35293010Sadrian#include <sys/lock.h> 36293010Sadrian#include <sys/mutex.h> 37293010Sadrian#include <sys/module.h> 38293010Sadrian#include <sys/bus.h> 39293010Sadrian#include <sys/endian.h> 40293010Sadrian#include <sys/firmware.h> 41293010Sadrian 42293010Sadrian#include <machine/bus.h> 43293010Sadrian#include <machine/resource.h> 44293010Sadrian#include <sys/rman.h> 45293010Sadrian 46293010Sadrian#include <dev/pci/pcireg.h> 47293010Sadrian#include <dev/pci/pcivar.h> 48293010Sadrian 49293010Sadrian#include <net/bpf.h> 50293010Sadrian#include <net/if.h> 51293010Sadrian#include <net/if_var.h> 52293010Sadrian#include <net/if_arp.h> 53293010Sadrian#include <net/ethernet.h> 54293010Sadrian#include <net/if_dl.h> 55293010Sadrian#include <net/if_media.h> 56293010Sadrian#include <net/if_types.h> 57293010Sadrian 58293010Sadrian#include <net80211/ieee80211_var.h> 59293010Sadrian#include <net80211/ieee80211_radiotap.h> 60293010Sadrian#include <net80211/ieee80211_regdomain.h> 61293010Sadrian#include <net80211/ieee80211_ratectl.h> 62293010Sadrian 63293010Sadrian#include <netinet/in.h> 64293010Sadrian#include <netinet/in_systm.h> 65293010Sadrian#include <netinet/in_var.h> 66293010Sadrian#include <netinet/ip.h> 67293010Sadrian#include <netinet/if_ether.h> 68293010Sadrian 69293010Sadrian#include <dev/rtwn/if_rtwnreg.h> 70293010Sadrian 71293010Sadrian#define RTWN_DEBUG 72293010Sadrian#ifdef RTWN_DEBUG 73293010Sadrian#define DPRINTF(x) do { if (sc->sc_debug > 0) printf x; } while (0) 74293010Sadrian#define DPRINTFN(n, x) do { if (sc->sc_debug >= (n)) printf x; } while (0) 75293010Sadrian#else 76293010Sadrian#define DPRINTF(x) 77293010Sadrian#define DPRINTFN(n, x) 78293010Sadrian#endif 79293010Sadrian 80293010Sadrian/* 81293010Sadrian * PCI configuration space registers. 82293010Sadrian */ 83293010Sadrian#define RTWN_PCI_IOBA 0x10 /* i/o mapped base */ 84293010Sadrian#define RTWN_PCI_MMBA 0x18 /* memory mapped base */ 85293010Sadrian 86293010Sadrian#define RTWN_INT_ENABLE (R92C_IMR_ROK | R92C_IMR_VODOK | R92C_IMR_VIDOK | \ 87293010Sadrian R92C_IMR_BEDOK | R92C_IMR_BKDOK | R92C_IMR_MGNTDOK | \ 88293010Sadrian R92C_IMR_HIGHDOK | R92C_IMR_BDOK | R92C_IMR_RDU | \ 89293010Sadrian R92C_IMR_RXFOVW) 90293010Sadrian 91293010Sadrianstruct rtwn_ident { 92293010Sadrian uint16_t vendor; 93293010Sadrian uint16_t device; 94293010Sadrian const char *name; 95293010Sadrian}; 96293010Sadrian 97293010Sadrian 98293010Sadrianstatic const struct rtwn_ident rtwn_ident_table[] = { 99293010Sadrian { 0x10ec, 0x8176, "Realtek RTL8188CE" }, 100293010Sadrian { 0, 0, NULL } 101293010Sadrian}; 102293010Sadrian 103293010Sadrian 104293010Sadrianstatic void rtwn_dma_map_addr(void *, bus_dma_segment_t *, int, int); 105293010Sadrianstatic void rtwn_setup_rx_desc(struct rtwn_softc *, struct r92c_rx_desc *, 106293010Sadrian bus_addr_t, size_t, int); 107293010Sadrianstatic int rtwn_alloc_rx_list(struct rtwn_softc *); 108293010Sadrianstatic void rtwn_reset_rx_list(struct rtwn_softc *); 109293010Sadrianstatic void rtwn_free_rx_list(struct rtwn_softc *); 110293010Sadrianstatic int rtwn_alloc_tx_list(struct rtwn_softc *, int); 111293010Sadrianstatic void rtwn_reset_tx_list(struct rtwn_softc *, int); 112293010Sadrianstatic void rtwn_free_tx_list(struct rtwn_softc *, int); 113293010Sadrianstatic struct ieee80211vap *rtwn_vap_create(struct ieee80211com *, 114293010Sadrian const char [IFNAMSIZ], int, enum ieee80211_opmode, int, 115293010Sadrian const uint8_t [IEEE80211_ADDR_LEN], 116293010Sadrian const uint8_t [IEEE80211_ADDR_LEN]); 117293010Sadrianstatic void rtwn_vap_delete(struct ieee80211vap *); 118293010Sadrianstatic void rtwn_write_1(struct rtwn_softc *, uint16_t, uint8_t); 119293010Sadrianstatic void rtwn_write_2(struct rtwn_softc *, uint16_t, uint16_t); 120293010Sadrianstatic void rtwn_write_4(struct rtwn_softc *, uint16_t, uint32_t); 121293010Sadrianstatic uint8_t rtwn_read_1(struct rtwn_softc *, uint16_t); 122293010Sadrianstatic uint16_t rtwn_read_2(struct rtwn_softc *, uint16_t); 123293010Sadrianstatic uint32_t rtwn_read_4(struct rtwn_softc *, uint16_t); 124293010Sadrianstatic int rtwn_fw_cmd(struct rtwn_softc *, uint8_t, const void *, int); 125293010Sadrianstatic void rtwn_rf_write(struct rtwn_softc *, int, uint8_t, uint32_t); 126293010Sadrianstatic uint32_t rtwn_rf_read(struct rtwn_softc *, int, uint8_t); 127293010Sadrianstatic int rtwn_llt_write(struct rtwn_softc *, uint32_t, uint32_t); 128293010Sadrianstatic uint8_t rtwn_efuse_read_1(struct rtwn_softc *, uint16_t); 129293010Sadrianstatic void rtwn_efuse_read(struct rtwn_softc *); 130293010Sadrianstatic int rtwn_read_chipid(struct rtwn_softc *); 131293010Sadrianstatic void rtwn_read_rom(struct rtwn_softc *); 132293010Sadrianstatic int rtwn_ra_init(struct rtwn_softc *); 133293010Sadrianstatic void rtwn_tsf_sync_enable(struct rtwn_softc *); 134293010Sadrianstatic void rtwn_set_led(struct rtwn_softc *, int, int); 135293010Sadrianstatic void rtwn_calib_to(void *); 136293010Sadrianstatic int rtwn_newstate(struct ieee80211vap *, enum ieee80211_state, int); 137293010Sadrianstatic int rtwn_updateedca(struct ieee80211com *); 138293010Sadrianstatic void rtwn_update_avgrssi(struct rtwn_softc *, int, int8_t); 139293010Sadrianstatic int8_t rtwn_get_rssi(struct rtwn_softc *, int, void *); 140293010Sadrianstatic void rtwn_rx_frame(struct rtwn_softc *, struct r92c_rx_desc *, 141293010Sadrian struct rtwn_rx_data *, int); 142293010Sadrianstatic int rtwn_tx(struct rtwn_softc *, struct mbuf *, 143293010Sadrian struct ieee80211_node *); 144293010Sadrianstatic void rtwn_tx_done(struct rtwn_softc *, int); 145293010Sadrianstatic int rtwn_raw_xmit(struct ieee80211_node *, struct mbuf *, 146293010Sadrian const struct ieee80211_bpf_params *); 147293010Sadrianstatic int rtwn_transmit(struct ieee80211com *, struct mbuf *); 148293010Sadrianstatic void rtwn_parent(struct ieee80211com *); 149293010Sadrianstatic void rtwn_start(struct rtwn_softc *sc); 150293010Sadrianstatic void rtwn_watchdog(void *); 151293010Sadrianstatic int rtwn_power_on(struct rtwn_softc *); 152293010Sadrianstatic int rtwn_llt_init(struct rtwn_softc *); 153293010Sadrianstatic void rtwn_fw_reset(struct rtwn_softc *); 154293010Sadrianstatic void rtwn_fw_loadpage(struct rtwn_softc *, int, const uint8_t *, 155293010Sadrian int); 156293010Sadrianstatic int rtwn_load_firmware(struct rtwn_softc *); 157293010Sadrianstatic int rtwn_dma_init(struct rtwn_softc *); 158293010Sadrianstatic void rtwn_mac_init(struct rtwn_softc *); 159293010Sadrianstatic void rtwn_bb_init(struct rtwn_softc *); 160293010Sadrianstatic void rtwn_rf_init(struct rtwn_softc *); 161293010Sadrianstatic void rtwn_cam_init(struct rtwn_softc *); 162293010Sadrianstatic void rtwn_pa_bias_init(struct rtwn_softc *); 163293010Sadrianstatic void rtwn_rxfilter_init(struct rtwn_softc *); 164293010Sadrianstatic void rtwn_edca_init(struct rtwn_softc *); 165293010Sadrianstatic void rtwn_write_txpower(struct rtwn_softc *, int, uint16_t[]); 166293010Sadrianstatic void rtwn_get_txpower(struct rtwn_softc *, int, 167293010Sadrian struct ieee80211_channel *, struct ieee80211_channel *, 168293010Sadrian uint16_t[]); 169293010Sadrianstatic void rtwn_set_txpower(struct rtwn_softc *, 170293010Sadrian struct ieee80211_channel *, struct ieee80211_channel *); 171295865Savosstatic void rtwn_set_rx_bssid_all(struct rtwn_softc *, int); 172295865Savosstatic void rtwn_set_gain(struct rtwn_softc *, uint8_t); 173293010Sadrianstatic void rtwn_scan_start(struct ieee80211com *); 174293010Sadrianstatic void rtwn_scan_end(struct ieee80211com *); 175300754Savosstatic void rtwn_getradiocaps(struct ieee80211com *, int, int *, 176300754Savos struct ieee80211_channel[]); 177293010Sadrianstatic void rtwn_set_channel(struct ieee80211com *); 178293010Sadrianstatic void rtwn_update_mcast(struct ieee80211com *); 179293010Sadrianstatic void rtwn_set_chan(struct rtwn_softc *, 180293010Sadrian struct ieee80211_channel *, struct ieee80211_channel *); 181293010Sadrianstatic int rtwn_iq_calib_chain(struct rtwn_softc *, int, uint16_t[2], 182293010Sadrian uint16_t[2]); 183293010Sadrianstatic void rtwn_iq_calib_run(struct rtwn_softc *, int, uint16_t[2][2], 184293010Sadrian uint16_t[2][2]); 185293010Sadrianstatic int rtwn_iq_calib_compare_results(uint16_t[2][2], uint16_t[2][2], 186293010Sadrian uint16_t[2][2], uint16_t[2][2], int); 187293010Sadrianstatic void rtwn_iq_calib_write_results(struct rtwn_softc *, uint16_t[2], 188293010Sadrian uint16_t[2], int); 189293010Sadrianstatic void rtwn_iq_calib(struct rtwn_softc *); 190293010Sadrianstatic void rtwn_lc_calib(struct rtwn_softc *); 191293010Sadrianstatic void rtwn_temp_calib(struct rtwn_softc *); 192294842Savosstatic int rtwn_init(struct rtwn_softc *); 193293010Sadrianstatic void rtwn_stop_locked(struct rtwn_softc *); 194293010Sadrianstatic void rtwn_stop(struct rtwn_softc *); 195293010Sadrianstatic void rtwn_intr(void *); 196293010Sadrian 197293010Sadrian/* Aliases. */ 198293010Sadrian#define rtwn_bb_write rtwn_write_4 199293010Sadrian#define rtwn_bb_read rtwn_read_4 200293010Sadrian 201293010Sadrianstatic int rtwn_probe(device_t); 202293010Sadrianstatic int rtwn_attach(device_t); 203293010Sadrianstatic int rtwn_detach(device_t); 204293010Sadrianstatic int rtwn_shutdown(device_t); 205293010Sadrianstatic int rtwn_suspend(device_t); 206293010Sadrianstatic int rtwn_resume(device_t); 207293010Sadrian 208293010Sadrianstatic device_method_t rtwn_methods[] = { 209293010Sadrian /* Device interface */ 210293010Sadrian DEVMETHOD(device_probe, rtwn_probe), 211293010Sadrian DEVMETHOD(device_attach, rtwn_attach), 212293010Sadrian DEVMETHOD(device_detach, rtwn_detach), 213293010Sadrian DEVMETHOD(device_shutdown, rtwn_shutdown), 214293010Sadrian DEVMETHOD(device_suspend, rtwn_suspend), 215293010Sadrian DEVMETHOD(device_resume, rtwn_resume), 216293010Sadrian 217293010Sadrian DEVMETHOD_END 218293010Sadrian}; 219293010Sadrian 220293010Sadrianstatic driver_t rtwn_driver = { 221293010Sadrian "rtwn", 222293010Sadrian rtwn_methods, 223293010Sadrian sizeof (struct rtwn_softc) 224293010Sadrian}; 225293010Sadrianstatic devclass_t rtwn_devclass; 226293010Sadrian 227293010SadrianDRIVER_MODULE(rtwn, pci, rtwn_driver, rtwn_devclass, NULL, NULL); 228293010Sadrian 229293010SadrianMODULE_VERSION(rtwn, 1); 230293010Sadrian 231293010SadrianMODULE_DEPEND(rtwn, pci, 1, 1, 1); 232293010SadrianMODULE_DEPEND(rtwn, wlan, 1, 1, 1); 233293010SadrianMODULE_DEPEND(rtwn, firmware, 1, 1, 1); 234293010Sadrian 235293010Sadrianstatic int 236293010Sadrianrtwn_probe(device_t dev) 237293010Sadrian{ 238293010Sadrian const struct rtwn_ident *ident; 239293010Sadrian 240293010Sadrian for (ident = rtwn_ident_table; ident->name != NULL; ident++) { 241293010Sadrian if (pci_get_vendor(dev) == ident->vendor && 242293010Sadrian pci_get_device(dev) == ident->device) { 243293010Sadrian device_set_desc(dev, ident->name); 244293010Sadrian return (BUS_PROBE_DEFAULT); 245293010Sadrian } 246293010Sadrian } 247293010Sadrian return (ENXIO); 248293010Sadrian} 249293010Sadrian 250293010Sadrianstatic int 251293010Sadrianrtwn_attach(device_t dev) 252293010Sadrian{ 253293010Sadrian struct rtwn_softc *sc = device_get_softc(dev); 254293010Sadrian struct ieee80211com *ic = &sc->sc_ic; 255293010Sadrian uint32_t lcsr; 256293010Sadrian int i, count, error, rid; 257293010Sadrian 258293010Sadrian sc->sc_dev = dev; 259293010Sadrian sc->sc_debug = 0; 260293010Sadrian 261293010Sadrian /* 262293010Sadrian * Get the offset of the PCI Express Capability Structure in PCI 263293010Sadrian * Configuration Space. 264293010Sadrian */ 265293010Sadrian error = pci_find_cap(dev, PCIY_EXPRESS, &sc->sc_cap_off); 266293010Sadrian if (error != 0) { 267293010Sadrian device_printf(dev, "PCIe capability structure not found!\n"); 268293010Sadrian return (error); 269293010Sadrian } 270293010Sadrian 271293010Sadrian /* Enable bus-mastering. */ 272293010Sadrian pci_enable_busmaster(dev); 273293010Sadrian 274293010Sadrian rid = PCIR_BAR(2); 275293010Sadrian sc->mem = bus_alloc_resource_any(dev, SYS_RES_MEMORY, &rid, 276293010Sadrian RF_ACTIVE); 277293010Sadrian if (sc->mem == NULL) { 278293010Sadrian device_printf(dev, "can't map mem space\n"); 279293010Sadrian return (ENOMEM); 280293010Sadrian } 281293010Sadrian sc->sc_st = rman_get_bustag(sc->mem); 282293010Sadrian sc->sc_sh = rman_get_bushandle(sc->mem); 283293010Sadrian 284293010Sadrian /* Install interrupt handler. */ 285293010Sadrian count = 1; 286293010Sadrian rid = 0; 287293010Sadrian if (pci_alloc_msi(dev, &count) == 0) 288293010Sadrian rid = 1; 289293010Sadrian sc->irq = bus_alloc_resource_any(dev, SYS_RES_IRQ, &rid, RF_ACTIVE | 290293010Sadrian (rid != 0 ? 0 : RF_SHAREABLE)); 291293010Sadrian if (sc->irq == NULL) { 292293010Sadrian device_printf(dev, "can't map interrupt\n"); 293293010Sadrian return (ENXIO); 294293010Sadrian } 295293010Sadrian 296293010Sadrian RTWN_LOCK_INIT(sc); 297293010Sadrian callout_init_mtx(&sc->calib_to, &sc->sc_mtx, 0); 298293010Sadrian callout_init_mtx(&sc->watchdog_to, &sc->sc_mtx, 0); 299293010Sadrian mbufq_init(&sc->sc_snd, ifqmaxlen); 300293010Sadrian 301293010Sadrian error = rtwn_read_chipid(sc); 302293010Sadrian if (error != 0) { 303293010Sadrian device_printf(dev, "unsupported test chip\n"); 304293010Sadrian goto fail; 305293010Sadrian } 306293010Sadrian 307293010Sadrian /* Disable PCIe Active State Power Management (ASPM). */ 308293010Sadrian lcsr = pci_read_config(sc->sc_dev, sc->sc_cap_off + PCIER_LINK_CTL, 4); 309293010Sadrian lcsr &= ~PCIEM_LINK_CTL_ASPMC; 310293010Sadrian pci_write_config(sc->sc_dev, sc->sc_cap_off + PCIER_LINK_CTL, lcsr, 4); 311293010Sadrian 312293010Sadrian /* Allocate Tx/Rx buffers. */ 313293010Sadrian error = rtwn_alloc_rx_list(sc); 314293010Sadrian if (error != 0) { 315293010Sadrian device_printf(dev, "could not allocate Rx buffers\n"); 316293010Sadrian goto fail; 317293010Sadrian } 318293010Sadrian for (i = 0; i < RTWN_NTXQUEUES; i++) { 319293010Sadrian error = rtwn_alloc_tx_list(sc, i); 320293010Sadrian if (error != 0) { 321293010Sadrian device_printf(dev, "could not allocate Tx buffers\n"); 322293010Sadrian goto fail; 323293010Sadrian } 324293010Sadrian } 325293010Sadrian 326293010Sadrian /* Determine number of Tx/Rx chains. */ 327293010Sadrian if (sc->chip & RTWN_CHIP_92C) { 328293010Sadrian sc->ntxchains = (sc->chip & RTWN_CHIP_92C_1T2R) ? 1 : 2; 329293010Sadrian sc->nrxchains = 2; 330293010Sadrian } else { 331293010Sadrian sc->ntxchains = 1; 332293010Sadrian sc->nrxchains = 1; 333293010Sadrian } 334293010Sadrian rtwn_read_rom(sc); 335293010Sadrian 336293010Sadrian device_printf(sc->sc_dev, "MAC/BB RTL%s, RF 6052 %dT%dR\n", 337293010Sadrian (sc->chip & RTWN_CHIP_92C) ? "8192CE" : "8188CE", 338293010Sadrian sc->ntxchains, sc->nrxchains); 339293010Sadrian 340293010Sadrian ic->ic_softc = sc; 341293010Sadrian ic->ic_name = device_get_nameunit(dev); 342293010Sadrian ic->ic_opmode = IEEE80211_M_STA; 343293010Sadrian ic->ic_phytype = IEEE80211_T_OFDM; /* not only, but not used */ 344293010Sadrian 345293010Sadrian /* set device capabilities */ 346293010Sadrian ic->ic_caps = 347293010Sadrian IEEE80211_C_STA /* station mode */ 348293010Sadrian | IEEE80211_C_MONITOR /* monitor mode */ 349293010Sadrian | IEEE80211_C_SHPREAMBLE /* short preamble supported */ 350293010Sadrian | IEEE80211_C_SHSLOT /* short slot time supported */ 351293010Sadrian | IEEE80211_C_WPA /* capable of WPA1+WPA2 */ 352293010Sadrian | IEEE80211_C_BGSCAN /* capable of bg scanning */ 353293010Sadrian | IEEE80211_C_WME /* 802.11e */ 354293010Sadrian ; 355293010Sadrian 356300754Savos /* XXX TODO: setup regdomain if R92C_CHANNEL_PLAN_BY_HW bit is set. */ 357293010Sadrian 358300754Savos rtwn_getradiocaps(ic, IEEE80211_CHAN_MAX, &ic->ic_nchans, 359300754Savos ic->ic_channels); 360300754Savos 361293010Sadrian ieee80211_ifattach(ic); 362293010Sadrian 363293010Sadrian ic->ic_wme.wme_update = rtwn_updateedca; 364293010Sadrian ic->ic_update_mcast = rtwn_update_mcast; 365300754Savos ic->ic_scan_start = rtwn_scan_start; 366293010Sadrian ic->ic_scan_end = rtwn_scan_end; 367300754Savos ic->ic_getradiocaps = rtwn_getradiocaps; 368293010Sadrian ic->ic_set_channel = rtwn_set_channel; 369293010Sadrian ic->ic_raw_xmit = rtwn_raw_xmit; 370293010Sadrian ic->ic_transmit = rtwn_transmit; 371293010Sadrian ic->ic_parent = rtwn_parent; 372293010Sadrian ic->ic_vap_create = rtwn_vap_create; 373293010Sadrian ic->ic_vap_delete = rtwn_vap_delete; 374293010Sadrian 375293010Sadrian ieee80211_radiotap_attach(ic, 376293010Sadrian &sc->sc_txtap.wt_ihdr, sizeof(sc->sc_txtap), 377293010Sadrian RTWN_TX_RADIOTAP_PRESENT, 378293010Sadrian &sc->sc_rxtap.wr_ihdr, sizeof(sc->sc_rxtap), 379293010Sadrian RTWN_RX_RADIOTAP_PRESENT); 380293010Sadrian 381293010Sadrian /* 382293010Sadrian * Hook our interrupt after all initialization is complete. 383293010Sadrian */ 384293010Sadrian error = bus_setup_intr(dev, sc->irq, INTR_TYPE_NET | INTR_MPSAFE, 385293010Sadrian NULL, rtwn_intr, sc, &sc->sc_ih); 386293010Sadrian if (error != 0) { 387293010Sadrian device_printf(dev, "can't establish interrupt, error %d\n", 388293010Sadrian error); 389293010Sadrian goto fail; 390293010Sadrian } 391293010Sadrian 392293010Sadrian if (bootverbose) 393293010Sadrian ieee80211_announce(ic); 394293010Sadrian 395293010Sadrian return (0); 396293010Sadrian 397293010Sadrianfail: 398293010Sadrian rtwn_detach(dev); 399293010Sadrian return (error); 400293010Sadrian} 401293010Sadrian 402293010Sadrian 403293010Sadrianstatic int 404293010Sadrianrtwn_detach(device_t dev) 405293010Sadrian{ 406293010Sadrian struct rtwn_softc *sc = device_get_softc(dev); 407293010Sadrian int i; 408293010Sadrian 409293010Sadrian if (sc->sc_ic.ic_softc != NULL) { 410293010Sadrian rtwn_stop(sc); 411293010Sadrian 412293010Sadrian callout_drain(&sc->calib_to); 413293010Sadrian callout_drain(&sc->watchdog_to); 414293010Sadrian ieee80211_ifdetach(&sc->sc_ic); 415293010Sadrian mbufq_drain(&sc->sc_snd); 416293010Sadrian } 417293010Sadrian 418293010Sadrian /* Uninstall interrupt handler. */ 419293010Sadrian if (sc->irq != NULL) { 420293010Sadrian bus_teardown_intr(dev, sc->irq, sc->sc_ih); 421293010Sadrian bus_release_resource(dev, SYS_RES_IRQ, rman_get_rid(sc->irq), 422293010Sadrian sc->irq); 423293010Sadrian pci_release_msi(dev); 424293010Sadrian } 425293010Sadrian 426293010Sadrian /* Free Tx/Rx buffers. */ 427293010Sadrian for (i = 0; i < RTWN_NTXQUEUES; i++) 428293010Sadrian rtwn_free_tx_list(sc, i); 429293010Sadrian rtwn_free_rx_list(sc); 430293010Sadrian 431293010Sadrian if (sc->mem != NULL) 432293010Sadrian bus_release_resource(dev, SYS_RES_MEMORY, 433293010Sadrian rman_get_rid(sc->mem), sc->mem); 434293010Sadrian 435293010Sadrian RTWN_LOCK_DESTROY(sc); 436293010Sadrian return (0); 437293010Sadrian} 438293010Sadrian 439293010Sadrianstatic int 440293010Sadrianrtwn_shutdown(device_t dev) 441293010Sadrian{ 442293010Sadrian 443293010Sadrian return (0); 444293010Sadrian} 445293010Sadrian 446293010Sadrianstatic int 447293010Sadrianrtwn_suspend(device_t dev) 448293010Sadrian{ 449293010Sadrian return (0); 450293010Sadrian} 451293010Sadrian 452293010Sadrianstatic int 453293010Sadrianrtwn_resume(device_t dev) 454293010Sadrian{ 455293010Sadrian 456293010Sadrian return (0); 457293010Sadrian} 458293010Sadrian 459293010Sadrianstatic void 460293010Sadrianrtwn_dma_map_addr(void *arg, bus_dma_segment_t *segs, int nsegs, int error) 461293010Sadrian{ 462293010Sadrian 463293010Sadrian if (error != 0) 464293010Sadrian return; 465293010Sadrian KASSERT(nsegs == 1, ("too many DMA segments, %d should be 1", nsegs)); 466293010Sadrian *(bus_addr_t *)arg = segs[0].ds_addr; 467293010Sadrian} 468293010Sadrian 469293010Sadrianstatic void 470293010Sadrianrtwn_setup_rx_desc(struct rtwn_softc *sc, struct r92c_rx_desc *desc, 471293010Sadrian bus_addr_t addr, size_t len, int idx) 472293010Sadrian{ 473293010Sadrian 474293010Sadrian memset(desc, 0, sizeof(*desc)); 475293010Sadrian desc->rxdw0 = htole32(SM(R92C_RXDW0_PKTLEN, len) | 476293010Sadrian ((idx == RTWN_RX_LIST_COUNT - 1) ? R92C_RXDW0_EOR : 0)); 477293010Sadrian desc->rxbufaddr = htole32(addr); 478293010Sadrian bus_space_barrier(sc->sc_st, sc->sc_sh, 0, sc->sc_mapsize, 479293010Sadrian BUS_SPACE_BARRIER_WRITE); 480293010Sadrian desc->rxdw0 |= htole32(R92C_RXDW0_OWN); 481293010Sadrian} 482293010Sadrian 483293010Sadrianstatic int 484293010Sadrianrtwn_alloc_rx_list(struct rtwn_softc *sc) 485293010Sadrian{ 486293010Sadrian struct rtwn_rx_ring *rx_ring = &sc->rx_ring; 487293010Sadrian struct rtwn_rx_data *rx_data; 488293010Sadrian bus_size_t size; 489293010Sadrian int i, error; 490293010Sadrian 491293010Sadrian /* Allocate Rx descriptors. */ 492293010Sadrian size = sizeof(struct r92c_rx_desc) * RTWN_RX_LIST_COUNT; 493293010Sadrian error = bus_dma_tag_create(bus_get_dma_tag(sc->sc_dev), 1, 0, 494293010Sadrian BUS_SPACE_MAXADDR_32BIT, BUS_SPACE_MAXADDR, NULL, NULL, 495293010Sadrian size, 1, size, 0, NULL, NULL, &rx_ring->desc_dmat); 496293010Sadrian if (error != 0) { 497293010Sadrian device_printf(sc->sc_dev, "could not create rx desc DMA tag\n"); 498293010Sadrian goto fail; 499293010Sadrian } 500293010Sadrian 501293010Sadrian error = bus_dmamem_alloc(rx_ring->desc_dmat, (void **)&rx_ring->desc, 502293010Sadrian BUS_DMA_NOWAIT | BUS_DMA_ZERO | BUS_DMA_COHERENT, 503293010Sadrian &rx_ring->desc_map); 504293010Sadrian if (error != 0) { 505293010Sadrian device_printf(sc->sc_dev, "could not allocate rx desc\n"); 506293010Sadrian goto fail; 507293010Sadrian } 508293010Sadrian error = bus_dmamap_load(rx_ring->desc_dmat, rx_ring->desc_map, 509293010Sadrian rx_ring->desc, size, rtwn_dma_map_addr, &rx_ring->paddr, 0); 510293010Sadrian if (error != 0) { 511293010Sadrian device_printf(sc->sc_dev, "could not load rx desc DMA map\n"); 512293010Sadrian goto fail; 513293010Sadrian } 514293010Sadrian bus_dmamap_sync(rx_ring->desc_dmat, rx_ring->desc_map, 515293010Sadrian BUS_DMASYNC_PREWRITE); 516293010Sadrian 517293010Sadrian /* Create RX buffer DMA tag. */ 518293010Sadrian error = bus_dma_tag_create(bus_get_dma_tag(sc->sc_dev), 1, 0, 519293010Sadrian BUS_SPACE_MAXADDR_32BIT, BUS_SPACE_MAXADDR, NULL, NULL, MCLBYTES, 520293010Sadrian 1, MCLBYTES, 0, NULL, NULL, &rx_ring->data_dmat); 521293010Sadrian if (error != 0) { 522293010Sadrian device_printf(sc->sc_dev, "could not create rx buf DMA tag\n"); 523293010Sadrian goto fail; 524293010Sadrian } 525293010Sadrian 526293010Sadrian /* Allocate Rx buffers. */ 527293010Sadrian for (i = 0; i < RTWN_RX_LIST_COUNT; i++) { 528293010Sadrian rx_data = &rx_ring->rx_data[i]; 529293010Sadrian error = bus_dmamap_create(rx_ring->data_dmat, 0, &rx_data->map); 530293010Sadrian if (error != 0) { 531293010Sadrian device_printf(sc->sc_dev, 532293010Sadrian "could not create rx buf DMA map\n"); 533293010Sadrian goto fail; 534293010Sadrian } 535293010Sadrian 536293010Sadrian rx_data->m = m_getcl(M_NOWAIT, MT_DATA, M_PKTHDR); 537293010Sadrian if (rx_data->m == NULL) { 538293010Sadrian device_printf(sc->sc_dev, 539293010Sadrian "could not allocate rx mbuf\n"); 540293010Sadrian error = ENOMEM; 541293010Sadrian goto fail; 542293010Sadrian } 543293010Sadrian 544293010Sadrian error = bus_dmamap_load(rx_ring->data_dmat, rx_data->map, 545293010Sadrian mtod(rx_data->m, void *), MCLBYTES, rtwn_dma_map_addr, 546293010Sadrian &rx_data->paddr, BUS_DMA_NOWAIT); 547293010Sadrian if (error != 0) { 548293010Sadrian device_printf(sc->sc_dev, 549293010Sadrian "could not load rx buf DMA map"); 550293010Sadrian goto fail; 551293010Sadrian } 552293010Sadrian 553293010Sadrian rtwn_setup_rx_desc(sc, &rx_ring->desc[i], rx_data->paddr, 554293010Sadrian MCLBYTES, i); 555293010Sadrian } 556293010Sadrian return (0); 557293010Sadrian 558293010Sadrianfail: 559293010Sadrian rtwn_free_rx_list(sc); 560293010Sadrian return (error); 561293010Sadrian} 562293010Sadrian 563293010Sadrianstatic void 564293010Sadrianrtwn_reset_rx_list(struct rtwn_softc *sc) 565293010Sadrian{ 566293010Sadrian struct rtwn_rx_ring *rx_ring = &sc->rx_ring; 567293010Sadrian struct rtwn_rx_data *rx_data; 568293010Sadrian int i; 569293010Sadrian 570293010Sadrian for (i = 0; i < RTWN_RX_LIST_COUNT; i++) { 571293010Sadrian rx_data = &rx_ring->rx_data[i]; 572293010Sadrian rtwn_setup_rx_desc(sc, &rx_ring->desc[i], rx_data->paddr, 573293010Sadrian MCLBYTES, i); 574293010Sadrian } 575293010Sadrian} 576293010Sadrian 577293010Sadrianstatic void 578293010Sadrianrtwn_free_rx_list(struct rtwn_softc *sc) 579293010Sadrian{ 580293010Sadrian struct rtwn_rx_ring *rx_ring = &sc->rx_ring; 581293010Sadrian struct rtwn_rx_data *rx_data; 582293010Sadrian int i; 583293010Sadrian 584293010Sadrian if (rx_ring->desc_dmat != NULL) { 585293010Sadrian if (rx_ring->desc != NULL) { 586302035Savos bus_dmamap_sync(rx_ring->desc_dmat, 587302035Savos rx_ring->desc_map, 588302035Savos BUS_DMASYNC_POSTREAD | BUS_DMASYNC_POSTWRITE); 589293010Sadrian bus_dmamap_unload(rx_ring->desc_dmat, 590293010Sadrian rx_ring->desc_map); 591293010Sadrian bus_dmamem_free(rx_ring->desc_dmat, rx_ring->desc, 592293010Sadrian rx_ring->desc_map); 593293010Sadrian rx_ring->desc = NULL; 594293010Sadrian } 595293010Sadrian bus_dma_tag_destroy(rx_ring->desc_dmat); 596293010Sadrian rx_ring->desc_dmat = NULL; 597293010Sadrian } 598293010Sadrian 599293010Sadrian for (i = 0; i < RTWN_RX_LIST_COUNT; i++) { 600293010Sadrian rx_data = &rx_ring->rx_data[i]; 601293010Sadrian 602293010Sadrian if (rx_data->m != NULL) { 603302035Savos bus_dmamap_sync(rx_ring->data_dmat, 604302035Savos rx_data->map, BUS_DMASYNC_POSTREAD); 605293010Sadrian bus_dmamap_unload(rx_ring->data_dmat, rx_data->map); 606293010Sadrian m_freem(rx_data->m); 607293010Sadrian rx_data->m = NULL; 608293010Sadrian } 609293010Sadrian bus_dmamap_destroy(rx_ring->data_dmat, rx_data->map); 610293010Sadrian rx_data->map = NULL; 611293010Sadrian } 612293010Sadrian if (rx_ring->data_dmat != NULL) { 613293010Sadrian bus_dma_tag_destroy(rx_ring->data_dmat); 614293010Sadrian rx_ring->data_dmat = NULL; 615293010Sadrian } 616293010Sadrian} 617293010Sadrian 618293010Sadrianstatic int 619293010Sadrianrtwn_alloc_tx_list(struct rtwn_softc *sc, int qid) 620293010Sadrian{ 621293010Sadrian struct rtwn_tx_ring *tx_ring = &sc->tx_ring[qid]; 622293010Sadrian struct rtwn_tx_data *tx_data; 623293010Sadrian bus_size_t size; 624293010Sadrian int i, error; 625293010Sadrian 626293010Sadrian size = sizeof(struct r92c_tx_desc) * RTWN_TX_LIST_COUNT; 627293010Sadrian error = bus_dma_tag_create(bus_get_dma_tag(sc->sc_dev), PAGE_SIZE, 0, 628293010Sadrian BUS_SPACE_MAXADDR_32BIT, BUS_SPACE_MAXADDR, NULL, NULL, 629293010Sadrian size, 1, size, 0, NULL, NULL, &tx_ring->desc_dmat); 630293010Sadrian if (error != 0) { 631293010Sadrian device_printf(sc->sc_dev, "could not create tx ring DMA tag\n"); 632293010Sadrian goto fail; 633293010Sadrian } 634293010Sadrian 635293010Sadrian error = bus_dmamem_alloc(tx_ring->desc_dmat, (void **)&tx_ring->desc, 636293010Sadrian BUS_DMA_NOWAIT | BUS_DMA_ZERO, &tx_ring->desc_map); 637293010Sadrian if (error != 0) { 638293010Sadrian device_printf(sc->sc_dev, "can't map tx ring DMA memory\n"); 639293010Sadrian goto fail; 640293010Sadrian } 641293010Sadrian error = bus_dmamap_load(tx_ring->desc_dmat, tx_ring->desc_map, 642293010Sadrian tx_ring->desc, size, rtwn_dma_map_addr, &tx_ring->paddr, 643293010Sadrian BUS_DMA_NOWAIT); 644293010Sadrian if (error != 0) { 645293010Sadrian device_printf(sc->sc_dev, "could not load desc DMA map\n"); 646293010Sadrian goto fail; 647293010Sadrian } 648302035Savos bus_dmamap_sync(tx_ring->desc_dmat, tx_ring->desc_map, 649302035Savos BUS_DMASYNC_PREWRITE); 650293010Sadrian 651293010Sadrian error = bus_dma_tag_create(bus_get_dma_tag(sc->sc_dev), 1, 0, 652293010Sadrian BUS_SPACE_MAXADDR_32BIT, BUS_SPACE_MAXADDR, NULL, NULL, MCLBYTES, 653293010Sadrian 1, MCLBYTES, 0, NULL, NULL, &tx_ring->data_dmat); 654293010Sadrian if (error != 0) { 655293010Sadrian device_printf(sc->sc_dev, "could not create tx buf DMA tag\n"); 656293010Sadrian goto fail; 657293010Sadrian } 658293010Sadrian 659293010Sadrian for (i = 0; i < RTWN_TX_LIST_COUNT; i++) { 660293010Sadrian struct r92c_tx_desc *desc = &tx_ring->desc[i]; 661293010Sadrian 662293010Sadrian /* setup tx desc */ 663293010Sadrian desc->nextdescaddr = htole32(tx_ring->paddr + 664293010Sadrian + sizeof(struct r92c_tx_desc) 665293010Sadrian * ((i + 1) % RTWN_TX_LIST_COUNT)); 666293010Sadrian tx_data = &tx_ring->tx_data[i]; 667293010Sadrian error = bus_dmamap_create(tx_ring->data_dmat, 0, &tx_data->map); 668293010Sadrian if (error != 0) { 669293010Sadrian device_printf(sc->sc_dev, 670293010Sadrian "could not create tx buf DMA map\n"); 671293010Sadrian goto fail; 672293010Sadrian } 673293010Sadrian tx_data->m = NULL; 674293010Sadrian tx_data->ni = NULL; 675293010Sadrian } 676293010Sadrian return (0); 677293010Sadrian 678293010Sadrianfail: 679293010Sadrian rtwn_free_tx_list(sc, qid); 680293010Sadrian return (error); 681293010Sadrian} 682293010Sadrian 683293010Sadrianstatic void 684293010Sadrianrtwn_reset_tx_list(struct rtwn_softc *sc, int qid) 685293010Sadrian{ 686293010Sadrian struct rtwn_tx_ring *tx_ring = &sc->tx_ring[qid]; 687293010Sadrian int i; 688293010Sadrian 689293010Sadrian for (i = 0; i < RTWN_TX_LIST_COUNT; i++) { 690293010Sadrian struct r92c_tx_desc *desc = &tx_ring->desc[i]; 691293010Sadrian struct rtwn_tx_data *tx_data = &tx_ring->tx_data[i]; 692293010Sadrian 693293010Sadrian memset(desc, 0, sizeof(*desc) - 694293010Sadrian (sizeof(desc->reserved) + sizeof(desc->nextdescaddr64) + 695293010Sadrian sizeof(desc->nextdescaddr))); 696293010Sadrian 697293010Sadrian if (tx_data->m != NULL) { 698302035Savos bus_dmamap_sync(tx_ring->data_dmat, tx_data->map, 699302035Savos BUS_DMASYNC_POSTWRITE); 700293010Sadrian bus_dmamap_unload(tx_ring->data_dmat, tx_data->map); 701293010Sadrian m_freem(tx_data->m); 702293010Sadrian tx_data->m = NULL; 703293010Sadrian } 704293010Sadrian if (tx_data->ni != NULL) { 705293010Sadrian ieee80211_free_node(tx_data->ni); 706293010Sadrian tx_data->ni = NULL; 707293010Sadrian } 708293010Sadrian } 709293010Sadrian 710293010Sadrian bus_dmamap_sync(tx_ring->desc_dmat, tx_ring->desc_map, 711293010Sadrian BUS_DMASYNC_POSTWRITE); 712293010Sadrian 713293010Sadrian sc->qfullmsk &= ~(1 << qid); 714293010Sadrian tx_ring->queued = 0; 715293010Sadrian tx_ring->cur = 0; 716293010Sadrian} 717293010Sadrian 718293010Sadrianstatic void 719293010Sadrianrtwn_free_tx_list(struct rtwn_softc *sc, int qid) 720293010Sadrian{ 721293010Sadrian struct rtwn_tx_ring *tx_ring = &sc->tx_ring[qid]; 722293010Sadrian struct rtwn_tx_data *tx_data; 723293010Sadrian int i; 724293010Sadrian 725293010Sadrian if (tx_ring->desc_dmat != NULL) { 726293010Sadrian if (tx_ring->desc != NULL) { 727302035Savos bus_dmamap_sync(tx_ring->desc_dmat, 728302035Savos tx_ring->desc_map, BUS_DMASYNC_POSTWRITE); 729293010Sadrian bus_dmamap_unload(tx_ring->desc_dmat, 730293010Sadrian tx_ring->desc_map); 731293010Sadrian bus_dmamem_free(tx_ring->desc_dmat, tx_ring->desc, 732293010Sadrian tx_ring->desc_map); 733293010Sadrian } 734293010Sadrian bus_dma_tag_destroy(tx_ring->desc_dmat); 735293010Sadrian } 736293010Sadrian 737293010Sadrian for (i = 0; i < RTWN_TX_LIST_COUNT; i++) { 738293010Sadrian tx_data = &tx_ring->tx_data[i]; 739293010Sadrian 740293010Sadrian if (tx_data->m != NULL) { 741302035Savos bus_dmamap_sync(tx_ring->data_dmat, tx_data->map, 742302035Savos BUS_DMASYNC_POSTWRITE); 743293010Sadrian bus_dmamap_unload(tx_ring->data_dmat, tx_data->map); 744293010Sadrian m_freem(tx_data->m); 745293010Sadrian tx_data->m = NULL; 746293010Sadrian } 747293010Sadrian } 748293010Sadrian if (tx_ring->data_dmat != NULL) { 749293010Sadrian bus_dma_tag_destroy(tx_ring->data_dmat); 750293010Sadrian tx_ring->data_dmat = NULL; 751293010Sadrian } 752293010Sadrian 753293010Sadrian sc->qfullmsk &= ~(1 << qid); 754293010Sadrian tx_ring->queued = 0; 755293010Sadrian tx_ring->cur = 0; 756293010Sadrian} 757293010Sadrian 758293010Sadrian 759293010Sadrianstatic struct ieee80211vap * 760293010Sadrianrtwn_vap_create(struct ieee80211com *ic, const char name[IFNAMSIZ], int unit, 761293010Sadrian enum ieee80211_opmode opmode, int flags, 762293010Sadrian const uint8_t bssid[IEEE80211_ADDR_LEN], 763293010Sadrian const uint8_t mac[IEEE80211_ADDR_LEN]) 764293010Sadrian{ 765293010Sadrian struct rtwn_vap *rvp; 766293010Sadrian struct ieee80211vap *vap; 767293010Sadrian 768293010Sadrian if (!TAILQ_EMPTY(&ic->ic_vaps)) 769293010Sadrian return (NULL); 770293010Sadrian 771293010Sadrian rvp = malloc(sizeof(struct rtwn_vap), M_80211_VAP, M_WAITOK | M_ZERO); 772293010Sadrian vap = &rvp->vap; 773293010Sadrian if (ieee80211_vap_setup(ic, vap, name, unit, opmode, 774293010Sadrian flags | IEEE80211_CLONE_NOBEACONS, bssid) != 0) { 775293010Sadrian /* out of memory */ 776293010Sadrian free(rvp, M_80211_VAP); 777293010Sadrian return (NULL); 778293010Sadrian } 779293010Sadrian 780293010Sadrian /* Override state transition machine. */ 781293010Sadrian rvp->newstate = vap->iv_newstate; 782293010Sadrian vap->iv_newstate = rtwn_newstate; 783293010Sadrian 784293010Sadrian /* Complete setup. */ 785293010Sadrian ieee80211_vap_attach(vap, ieee80211_media_change, 786293010Sadrian ieee80211_media_status, mac); 787293010Sadrian ic->ic_opmode = opmode; 788293010Sadrian return (vap); 789293010Sadrian} 790293010Sadrian 791293010Sadrianstatic void 792293010Sadrianrtwn_vap_delete(struct ieee80211vap *vap) 793293010Sadrian{ 794293010Sadrian struct rtwn_vap *rvp = RTWN_VAP(vap); 795293010Sadrian 796293010Sadrian ieee80211_vap_detach(vap); 797293010Sadrian free(rvp, M_80211_VAP); 798293010Sadrian} 799293010Sadrian 800293010Sadrianstatic void 801293010Sadrianrtwn_write_1(struct rtwn_softc *sc, uint16_t addr, uint8_t val) 802293010Sadrian{ 803293010Sadrian 804293010Sadrian bus_space_write_1(sc->sc_st, sc->sc_sh, addr, val); 805293010Sadrian} 806293010Sadrian 807293010Sadrianstatic void 808293010Sadrianrtwn_write_2(struct rtwn_softc *sc, uint16_t addr, uint16_t val) 809293010Sadrian{ 810293010Sadrian 811293010Sadrian val = htole16(val); 812293010Sadrian bus_space_write_2(sc->sc_st, sc->sc_sh, addr, val); 813293010Sadrian} 814293010Sadrian 815293010Sadrianstatic void 816293010Sadrianrtwn_write_4(struct rtwn_softc *sc, uint16_t addr, uint32_t val) 817293010Sadrian{ 818293010Sadrian 819293010Sadrian val = htole32(val); 820293010Sadrian bus_space_write_4(sc->sc_st, sc->sc_sh, addr, val); 821293010Sadrian} 822293010Sadrian 823293010Sadrianstatic uint8_t 824293010Sadrianrtwn_read_1(struct rtwn_softc *sc, uint16_t addr) 825293010Sadrian{ 826293010Sadrian 827293010Sadrian return (bus_space_read_1(sc->sc_st, sc->sc_sh, addr)); 828293010Sadrian} 829293010Sadrian 830293010Sadrianstatic uint16_t 831293010Sadrianrtwn_read_2(struct rtwn_softc *sc, uint16_t addr) 832293010Sadrian{ 833293010Sadrian 834293010Sadrian return (bus_space_read_2(sc->sc_st, sc->sc_sh, addr)); 835293010Sadrian} 836293010Sadrian 837293010Sadrianstatic uint32_t 838293010Sadrianrtwn_read_4(struct rtwn_softc *sc, uint16_t addr) 839293010Sadrian{ 840293010Sadrian 841293010Sadrian return (bus_space_read_4(sc->sc_st, sc->sc_sh, addr)); 842293010Sadrian} 843293010Sadrian 844293010Sadrianstatic int 845293010Sadrianrtwn_fw_cmd(struct rtwn_softc *sc, uint8_t id, const void *buf, int len) 846293010Sadrian{ 847293010Sadrian struct r92c_fw_cmd cmd; 848293010Sadrian int ntries; 849293010Sadrian 850293010Sadrian /* Wait for current FW box to be empty. */ 851293010Sadrian for (ntries = 0; ntries < 100; ntries++) { 852293010Sadrian if (!(rtwn_read_1(sc, R92C_HMETFR) & (1 << sc->fwcur))) 853293010Sadrian break; 854293010Sadrian DELAY(1); 855293010Sadrian } 856293010Sadrian if (ntries == 100) { 857293010Sadrian device_printf(sc->sc_dev, 858293010Sadrian "could not send firmware command %d\n", id); 859293010Sadrian return (ETIMEDOUT); 860293010Sadrian } 861293010Sadrian memset(&cmd, 0, sizeof(cmd)); 862293010Sadrian cmd.id = id; 863293010Sadrian if (len > 3) 864293010Sadrian cmd.id |= R92C_CMD_FLAG_EXT; 865293010Sadrian KASSERT(len <= sizeof(cmd.msg), ("rtwn_fw_cmd\n")); 866293010Sadrian memcpy(cmd.msg, buf, len); 867293010Sadrian 868293010Sadrian /* Write the first word last since that will trigger the FW. */ 869293010Sadrian rtwn_write_2(sc, R92C_HMEBOX_EXT(sc->fwcur), *((uint8_t *)&cmd + 4)); 870293010Sadrian rtwn_write_4(sc, R92C_HMEBOX(sc->fwcur), *((uint8_t *)&cmd + 0)); 871293010Sadrian 872293010Sadrian sc->fwcur = (sc->fwcur + 1) % R92C_H2C_NBOX; 873293010Sadrian 874293010Sadrian /* Give firmware some time for processing. */ 875293010Sadrian DELAY(2000); 876293010Sadrian 877293010Sadrian return (0); 878293010Sadrian} 879293010Sadrian 880293010Sadrianstatic void 881293010Sadrianrtwn_rf_write(struct rtwn_softc *sc, int chain, uint8_t addr, uint32_t val) 882293010Sadrian{ 883293010Sadrian rtwn_bb_write(sc, R92C_LSSI_PARAM(chain), 884293010Sadrian SM(R92C_LSSI_PARAM_ADDR, addr) | 885293010Sadrian SM(R92C_LSSI_PARAM_DATA, val)); 886293010Sadrian} 887293010Sadrian 888293010Sadrianstatic uint32_t 889293010Sadrianrtwn_rf_read(struct rtwn_softc *sc, int chain, uint8_t addr) 890293010Sadrian{ 891293010Sadrian uint32_t reg[R92C_MAX_CHAINS], val; 892293010Sadrian 893293010Sadrian reg[0] = rtwn_bb_read(sc, R92C_HSSI_PARAM2(0)); 894293010Sadrian if (chain != 0) 895293010Sadrian reg[chain] = rtwn_bb_read(sc, R92C_HSSI_PARAM2(chain)); 896293010Sadrian 897293010Sadrian rtwn_bb_write(sc, R92C_HSSI_PARAM2(0), 898293010Sadrian reg[0] & ~R92C_HSSI_PARAM2_READ_EDGE); 899293010Sadrian DELAY(1000); 900293010Sadrian 901293010Sadrian rtwn_bb_write(sc, R92C_HSSI_PARAM2(chain), 902293010Sadrian RW(reg[chain], R92C_HSSI_PARAM2_READ_ADDR, addr) | 903293010Sadrian R92C_HSSI_PARAM2_READ_EDGE); 904293010Sadrian DELAY(1000); 905293010Sadrian 906293010Sadrian rtwn_bb_write(sc, R92C_HSSI_PARAM2(0), 907293010Sadrian reg[0] | R92C_HSSI_PARAM2_READ_EDGE); 908293010Sadrian DELAY(1000); 909293010Sadrian 910293010Sadrian if (rtwn_bb_read(sc, R92C_HSSI_PARAM1(chain)) & R92C_HSSI_PARAM1_PI) 911293010Sadrian val = rtwn_bb_read(sc, R92C_HSPI_READBACK(chain)); 912293010Sadrian else 913293010Sadrian val = rtwn_bb_read(sc, R92C_LSSI_READBACK(chain)); 914293010Sadrian return (MS(val, R92C_LSSI_READBACK_DATA)); 915293010Sadrian} 916293010Sadrian 917293010Sadrianstatic int 918293010Sadrianrtwn_llt_write(struct rtwn_softc *sc, uint32_t addr, uint32_t data) 919293010Sadrian{ 920293010Sadrian int ntries; 921293010Sadrian 922293010Sadrian rtwn_write_4(sc, R92C_LLT_INIT, 923293010Sadrian SM(R92C_LLT_INIT_OP, R92C_LLT_INIT_OP_WRITE) | 924293010Sadrian SM(R92C_LLT_INIT_ADDR, addr) | 925293010Sadrian SM(R92C_LLT_INIT_DATA, data)); 926293010Sadrian /* Wait for write operation to complete. */ 927293010Sadrian for (ntries = 0; ntries < 20; ntries++) { 928293010Sadrian if (MS(rtwn_read_4(sc, R92C_LLT_INIT), R92C_LLT_INIT_OP) == 929293010Sadrian R92C_LLT_INIT_OP_NO_ACTIVE) 930293010Sadrian return (0); 931293010Sadrian DELAY(5); 932293010Sadrian } 933293010Sadrian return (ETIMEDOUT); 934293010Sadrian} 935293010Sadrian 936293010Sadrianstatic uint8_t 937293010Sadrianrtwn_efuse_read_1(struct rtwn_softc *sc, uint16_t addr) 938293010Sadrian{ 939293010Sadrian uint32_t reg; 940293010Sadrian int ntries; 941293010Sadrian 942293010Sadrian reg = rtwn_read_4(sc, R92C_EFUSE_CTRL); 943293010Sadrian reg = RW(reg, R92C_EFUSE_CTRL_ADDR, addr); 944293010Sadrian reg &= ~R92C_EFUSE_CTRL_VALID; 945293010Sadrian rtwn_write_4(sc, R92C_EFUSE_CTRL, reg); 946293010Sadrian /* Wait for read operation to complete. */ 947293010Sadrian for (ntries = 0; ntries < 100; ntries++) { 948293010Sadrian reg = rtwn_read_4(sc, R92C_EFUSE_CTRL); 949293010Sadrian if (reg & R92C_EFUSE_CTRL_VALID) 950293010Sadrian return (MS(reg, R92C_EFUSE_CTRL_DATA)); 951293010Sadrian DELAY(5); 952293010Sadrian } 953293010Sadrian device_printf(sc->sc_dev, 954293010Sadrian "could not read efuse byte at address 0x%x\n", addr); 955293010Sadrian return (0xff); 956293010Sadrian} 957293010Sadrian 958293010Sadrianstatic void 959293010Sadrianrtwn_efuse_read(struct rtwn_softc *sc) 960293010Sadrian{ 961293010Sadrian uint8_t *rom = (uint8_t *)&sc->rom; 962293010Sadrian uint16_t addr = 0; 963293010Sadrian uint32_t reg; 964293010Sadrian uint8_t off, msk; 965293010Sadrian int i; 966293010Sadrian 967293010Sadrian reg = rtwn_read_2(sc, R92C_SYS_ISO_CTRL); 968293010Sadrian if (!(reg & R92C_SYS_ISO_CTRL_PWC_EV12V)) { 969293010Sadrian rtwn_write_2(sc, R92C_SYS_ISO_CTRL, 970293010Sadrian reg | R92C_SYS_ISO_CTRL_PWC_EV12V); 971293010Sadrian } 972293010Sadrian reg = rtwn_read_2(sc, R92C_SYS_FUNC_EN); 973293010Sadrian if (!(reg & R92C_SYS_FUNC_EN_ELDR)) { 974293010Sadrian rtwn_write_2(sc, R92C_SYS_FUNC_EN, 975293010Sadrian reg | R92C_SYS_FUNC_EN_ELDR); 976293010Sadrian } 977293010Sadrian reg = rtwn_read_2(sc, R92C_SYS_CLKR); 978293010Sadrian if ((reg & (R92C_SYS_CLKR_LOADER_EN | R92C_SYS_CLKR_ANA8M)) != 979293010Sadrian (R92C_SYS_CLKR_LOADER_EN | R92C_SYS_CLKR_ANA8M)) { 980293010Sadrian rtwn_write_2(sc, R92C_SYS_CLKR, 981293010Sadrian reg | R92C_SYS_CLKR_LOADER_EN | R92C_SYS_CLKR_ANA8M); 982293010Sadrian } 983293010Sadrian memset(&sc->rom, 0xff, sizeof(sc->rom)); 984293010Sadrian while (addr < 512) { 985293010Sadrian reg = rtwn_efuse_read_1(sc, addr); 986293010Sadrian if (reg == 0xff) 987293010Sadrian break; 988293010Sadrian addr++; 989293010Sadrian off = reg >> 4; 990293010Sadrian msk = reg & 0xf; 991293010Sadrian for (i = 0; i < 4; i++) { 992293010Sadrian if (msk & (1 << i)) 993293010Sadrian continue; 994293010Sadrian rom[off * 8 + i * 2 + 0] = 995293010Sadrian rtwn_efuse_read_1(sc, addr); 996293010Sadrian addr++; 997293010Sadrian rom[off * 8 + i * 2 + 1] = 998293010Sadrian rtwn_efuse_read_1(sc, addr); 999293010Sadrian addr++; 1000293010Sadrian } 1001293010Sadrian } 1002293010Sadrian#ifdef RTWN_DEBUG 1003293010Sadrian if (sc->sc_debug >= 2) { 1004293010Sadrian /* Dump ROM content. */ 1005293010Sadrian printf("\n"); 1006293010Sadrian for (i = 0; i < sizeof(sc->rom); i++) 1007293010Sadrian printf("%02x:", rom[i]); 1008293010Sadrian printf("\n"); 1009293010Sadrian } 1010293010Sadrian#endif 1011293010Sadrian} 1012293010Sadrian 1013293010Sadrianstatic int 1014293010Sadrianrtwn_read_chipid(struct rtwn_softc *sc) 1015293010Sadrian{ 1016293010Sadrian uint32_t reg; 1017293010Sadrian 1018293010Sadrian reg = rtwn_read_4(sc, R92C_SYS_CFG); 1019293010Sadrian if (reg & R92C_SYS_CFG_TRP_VAUX_EN) 1020293010Sadrian /* Unsupported test chip. */ 1021293010Sadrian return (EIO); 1022293010Sadrian 1023293010Sadrian if (reg & R92C_SYS_CFG_TYPE_92C) { 1024293010Sadrian sc->chip |= RTWN_CHIP_92C; 1025293010Sadrian /* Check if it is a castrated 8192C. */ 1026293010Sadrian if (MS(rtwn_read_4(sc, R92C_HPON_FSM), 1027293010Sadrian R92C_HPON_FSM_CHIP_BONDING_ID) == 1028293010Sadrian R92C_HPON_FSM_CHIP_BONDING_ID_92C_1T2R) 1029293010Sadrian sc->chip |= RTWN_CHIP_92C_1T2R; 1030293010Sadrian } 1031293010Sadrian if (reg & R92C_SYS_CFG_VENDOR_UMC) { 1032293010Sadrian sc->chip |= RTWN_CHIP_UMC; 1033293010Sadrian if (MS(reg, R92C_SYS_CFG_CHIP_VER_RTL) == 0) 1034293010Sadrian sc->chip |= RTWN_CHIP_UMC_A_CUT; 1035293010Sadrian } 1036293010Sadrian return (0); 1037293010Sadrian} 1038293010Sadrian 1039293010Sadrianstatic void 1040293010Sadrianrtwn_read_rom(struct rtwn_softc *sc) 1041293010Sadrian{ 1042293010Sadrian struct r92c_rom *rom = &sc->rom; 1043293010Sadrian 1044293010Sadrian /* Read full ROM image. */ 1045293010Sadrian rtwn_efuse_read(sc); 1046293010Sadrian 1047293010Sadrian if (rom->id != 0x8129) 1048293010Sadrian device_printf(sc->sc_dev, "invalid EEPROM ID 0x%x\n", rom->id); 1049293010Sadrian 1050293010Sadrian /* XXX Weird but this is what the vendor driver does. */ 1051293010Sadrian sc->pa_setting = rtwn_efuse_read_1(sc, 0x1fa); 1052293010Sadrian DPRINTF(("PA setting=0x%x\n", sc->pa_setting)); 1053293010Sadrian 1054293010Sadrian sc->board_type = MS(rom->rf_opt1, R92C_ROM_RF1_BOARD_TYPE); 1055293010Sadrian 1056293010Sadrian sc->regulatory = MS(rom->rf_opt1, R92C_ROM_RF1_REGULATORY); 1057293010Sadrian DPRINTF(("regulatory type=%d\n", sc->regulatory)); 1058293010Sadrian 1059293010Sadrian IEEE80211_ADDR_COPY(sc->sc_ic.ic_macaddr, rom->macaddr); 1060293010Sadrian} 1061293010Sadrian 1062300744Savosstatic __inline uint8_t 1063300744Savosrate2ridx(uint8_t rate) 1064300744Savos{ 1065300744Savos switch (rate) { 1066300744Savos case 12: return 4; 1067300744Savos case 18: return 5; 1068300744Savos case 24: return 6; 1069300744Savos case 36: return 7; 1070300744Savos case 48: return 8; 1071300744Savos case 72: return 9; 1072300744Savos case 96: return 10; 1073300744Savos case 108: return 11; 1074300744Savos case 2: return 0; 1075300744Savos case 4: return 1; 1076300744Savos case 11: return 2; 1077300744Savos case 22: return 3; 1078300744Savos default: return RTWN_RIDX_UNKNOWN; 1079300744Savos } 1080300744Savos} 1081300744Savos 1082293010Sadrian/* 1083293010Sadrian * Initialize rate adaptation in firmware. 1084293010Sadrian */ 1085293010Sadrianstatic int 1086293010Sadrianrtwn_ra_init(struct rtwn_softc *sc) 1087293010Sadrian{ 1088293010Sadrian struct ieee80211com *ic = &sc->sc_ic; 1089293010Sadrian struct ieee80211vap *vap = TAILQ_FIRST(&ic->ic_vaps); 1090293010Sadrian struct ieee80211_node *ni = ieee80211_ref_node(vap->iv_bss); 1091293010Sadrian struct ieee80211_rateset *rs = &ni->ni_rates; 1092293010Sadrian struct r92c_fw_cmd_macid_cfg cmd; 1093293010Sadrian uint32_t rates, basicrates; 1094300744Savos uint8_t maxrate, maxbasicrate, mode, ridx; 1095300744Savos int error, i; 1096293010Sadrian 1097293010Sadrian /* Get normal and basic rates mask. */ 1098293010Sadrian rates = basicrates = 0; 1099293010Sadrian maxrate = maxbasicrate = 0; 1100293010Sadrian for (i = 0; i < rs->rs_nrates; i++) { 1101293010Sadrian /* Convert 802.11 rate to HW rate index. */ 1102300744Savos ridx = rate2ridx(IEEE80211_RV(rs->rs_rates[i])); 1103300744Savos if (ridx == RTWN_RIDX_UNKNOWN) /* Unknown rate, skip. */ 1104293010Sadrian continue; 1105300744Savos rates |= 1 << ridx; 1106300744Savos if (ridx > maxrate) 1107300744Savos maxrate = ridx; 1108293010Sadrian if (rs->rs_rates[i] & IEEE80211_RATE_BASIC) { 1109300744Savos basicrates |= 1 << ridx; 1110300744Savos if (ridx > maxbasicrate) 1111300744Savos maxbasicrate = ridx; 1112293010Sadrian } 1113293010Sadrian } 1114293010Sadrian if (ic->ic_curmode == IEEE80211_MODE_11B) 1115293010Sadrian mode = R92C_RAID_11B; 1116293010Sadrian else 1117293010Sadrian mode = R92C_RAID_11BG; 1118293010Sadrian DPRINTF(("mode=0x%x rates=0x%08x, basicrates=0x%08x\n", 1119293010Sadrian mode, rates, basicrates)); 1120293010Sadrian 1121293010Sadrian /* Set rates mask for group addressed frames. */ 1122293010Sadrian cmd.macid = RTWN_MACID_BC | RTWN_MACID_VALID; 1123293010Sadrian cmd.mask = htole32(mode << 28 | basicrates); 1124293010Sadrian error = rtwn_fw_cmd(sc, R92C_CMD_MACID_CONFIG, &cmd, sizeof(cmd)); 1125293010Sadrian if (error != 0) { 1126293010Sadrian device_printf(sc->sc_dev, 1127293010Sadrian "could not add broadcast station\n"); 1128293010Sadrian return (error); 1129293010Sadrian } 1130293010Sadrian /* Set initial MRR rate. */ 1131293010Sadrian DPRINTF(("maxbasicrate=%d\n", maxbasicrate)); 1132293010Sadrian rtwn_write_1(sc, R92C_INIDATA_RATE_SEL(RTWN_MACID_BC), 1133293010Sadrian maxbasicrate); 1134293010Sadrian 1135293010Sadrian /* Set rates mask for unicast frames. */ 1136293010Sadrian cmd.macid = RTWN_MACID_BSS | RTWN_MACID_VALID; 1137293010Sadrian cmd.mask = htole32(mode << 28 | rates); 1138293010Sadrian error = rtwn_fw_cmd(sc, R92C_CMD_MACID_CONFIG, &cmd, sizeof(cmd)); 1139293010Sadrian if (error != 0) { 1140293010Sadrian device_printf(sc->sc_dev, "could not add BSS station\n"); 1141293010Sadrian return (error); 1142293010Sadrian } 1143293010Sadrian /* Set initial MRR rate. */ 1144293010Sadrian DPRINTF(("maxrate=%d\n", maxrate)); 1145293010Sadrian rtwn_write_1(sc, R92C_INIDATA_RATE_SEL(RTWN_MACID_BSS), 1146293010Sadrian maxrate); 1147293010Sadrian 1148293010Sadrian /* Configure Automatic Rate Fallback Register. */ 1149293010Sadrian if (ic->ic_curmode == IEEE80211_MODE_11B) { 1150293010Sadrian if (rates & 0x0c) 1151293010Sadrian rtwn_write_4(sc, R92C_ARFR(0), htole32(rates & 0x0d)); 1152293010Sadrian else 1153293010Sadrian rtwn_write_4(sc, R92C_ARFR(0), htole32(rates & 0x0f)); 1154293010Sadrian } else 1155293010Sadrian rtwn_write_4(sc, R92C_ARFR(0), htole32(rates & 0x0ff5)); 1156293010Sadrian 1157293010Sadrian /* Indicate highest supported rate. */ 1158293010Sadrian ni->ni_txrate = rs->rs_rates[rs->rs_nrates - 1]; 1159293010Sadrian return (0); 1160293010Sadrian} 1161293010Sadrian 1162293010Sadrianstatic void 1163293010Sadrianrtwn_tsf_sync_enable(struct rtwn_softc *sc) 1164293010Sadrian{ 1165293010Sadrian struct ieee80211com *ic = &sc->sc_ic; 1166293010Sadrian struct ieee80211vap *vap = TAILQ_FIRST(&ic->ic_vaps); 1167293010Sadrian struct ieee80211_node *ni = vap->iv_bss; 1168293010Sadrian uint64_t tsf; 1169293010Sadrian 1170293010Sadrian /* Enable TSF synchronization. */ 1171293010Sadrian rtwn_write_1(sc, R92C_BCN_CTRL, 1172293010Sadrian rtwn_read_1(sc, R92C_BCN_CTRL) & ~R92C_BCN_CTRL_DIS_TSF_UDT0); 1173293010Sadrian 1174293010Sadrian rtwn_write_1(sc, R92C_BCN_CTRL, 1175293010Sadrian rtwn_read_1(sc, R92C_BCN_CTRL) & ~R92C_BCN_CTRL_EN_BCN); 1176293010Sadrian 1177293010Sadrian /* Set initial TSF. */ 1178293010Sadrian memcpy(&tsf, ni->ni_tstamp.data, 8); 1179293010Sadrian tsf = le64toh(tsf); 1180293010Sadrian tsf = tsf - (tsf % (vap->iv_bss->ni_intval * IEEE80211_DUR_TU)); 1181293010Sadrian tsf -= IEEE80211_DUR_TU; 1182293010Sadrian rtwn_write_4(sc, R92C_TSFTR + 0, tsf); 1183293010Sadrian rtwn_write_4(sc, R92C_TSFTR + 4, tsf >> 32); 1184293010Sadrian 1185293010Sadrian rtwn_write_1(sc, R92C_BCN_CTRL, 1186293010Sadrian rtwn_read_1(sc, R92C_BCN_CTRL) | R92C_BCN_CTRL_EN_BCN); 1187293010Sadrian} 1188293010Sadrian 1189293010Sadrianstatic void 1190293010Sadrianrtwn_set_led(struct rtwn_softc *sc, int led, int on) 1191293010Sadrian{ 1192293010Sadrian uint8_t reg; 1193293010Sadrian 1194293010Sadrian if (led == RTWN_LED_LINK) { 1195293010Sadrian reg = rtwn_read_1(sc, R92C_LEDCFG2) & 0xf0; 1196293010Sadrian if (!on) 1197293010Sadrian reg |= R92C_LEDCFG2_DIS; 1198293010Sadrian else 1199293010Sadrian reg |= R92C_LEDCFG2_EN; 1200293010Sadrian rtwn_write_1(sc, R92C_LEDCFG2, reg); 1201293010Sadrian sc->ledlink = on; /* Save LED state. */ 1202293010Sadrian } 1203293010Sadrian} 1204293010Sadrian 1205293010Sadrianstatic void 1206293010Sadrianrtwn_calib_to(void *arg) 1207293010Sadrian{ 1208293010Sadrian struct rtwn_softc *sc = arg; 1209293010Sadrian struct r92c_fw_cmd_rssi cmd; 1210293010Sadrian 1211293010Sadrian if (sc->avg_pwdb != -1) { 1212293010Sadrian /* Indicate Rx signal strength to FW for rate adaptation. */ 1213293010Sadrian memset(&cmd, 0, sizeof(cmd)); 1214293010Sadrian cmd.macid = 0; /* BSS. */ 1215293010Sadrian cmd.pwdb = sc->avg_pwdb; 1216293010Sadrian DPRINTFN(3, ("sending RSSI command avg=%d\n", sc->avg_pwdb)); 1217293010Sadrian rtwn_fw_cmd(sc, R92C_CMD_RSSI_SETTING, &cmd, sizeof(cmd)); 1218293010Sadrian } 1219293010Sadrian 1220293010Sadrian /* Do temperature compensation. */ 1221293010Sadrian rtwn_temp_calib(sc); 1222293010Sadrian 1223293010Sadrian callout_reset(&sc->calib_to, hz * 2, rtwn_calib_to, sc); 1224293010Sadrian} 1225293010Sadrian 1226293010Sadrianstatic int 1227293010Sadrianrtwn_newstate(struct ieee80211vap *vap, enum ieee80211_state nstate, int arg) 1228293010Sadrian{ 1229293010Sadrian struct rtwn_vap *rvp = RTWN_VAP(vap); 1230293010Sadrian struct ieee80211com *ic = vap->iv_ic; 1231293010Sadrian struct ieee80211_node *ni = vap->iv_bss; 1232293010Sadrian struct rtwn_softc *sc = ic->ic_softc; 1233293010Sadrian uint32_t reg; 1234293010Sadrian 1235293010Sadrian IEEE80211_UNLOCK(ic); 1236293010Sadrian RTWN_LOCK(sc); 1237293010Sadrian 1238293010Sadrian if (vap->iv_state == IEEE80211_S_RUN) { 1239293010Sadrian /* Stop calibration. */ 1240293010Sadrian callout_stop(&sc->calib_to); 1241293010Sadrian 1242293010Sadrian /* Turn link LED off. */ 1243293010Sadrian rtwn_set_led(sc, RTWN_LED_LINK, 0); 1244293010Sadrian 1245293010Sadrian /* Set media status to 'No Link'. */ 1246293010Sadrian reg = rtwn_read_4(sc, R92C_CR); 1247293010Sadrian reg = RW(reg, R92C_CR_NETTYPE, R92C_CR_NETTYPE_NOLINK); 1248293010Sadrian rtwn_write_4(sc, R92C_CR, reg); 1249293010Sadrian 1250293010Sadrian /* Stop Rx of data frames. */ 1251293010Sadrian rtwn_write_2(sc, R92C_RXFLTMAP2, 0); 1252293010Sadrian 1253293010Sadrian /* Rest TSF. */ 1254293010Sadrian rtwn_write_1(sc, R92C_DUAL_TSF_RST, 0x03); 1255293010Sadrian 1256293010Sadrian /* Disable TSF synchronization. */ 1257293010Sadrian rtwn_write_1(sc, R92C_BCN_CTRL, 1258293010Sadrian rtwn_read_1(sc, R92C_BCN_CTRL) | 1259293010Sadrian R92C_BCN_CTRL_DIS_TSF_UDT0); 1260293010Sadrian 1261293010Sadrian /* Reset EDCA parameters. */ 1262293010Sadrian rtwn_write_4(sc, R92C_EDCA_VO_PARAM, 0x002f3217); 1263293010Sadrian rtwn_write_4(sc, R92C_EDCA_VI_PARAM, 0x005e4317); 1264293010Sadrian rtwn_write_4(sc, R92C_EDCA_BE_PARAM, 0x00105320); 1265293010Sadrian rtwn_write_4(sc, R92C_EDCA_BK_PARAM, 0x0000a444); 1266293010Sadrian } 1267293010Sadrian switch (nstate) { 1268293010Sadrian case IEEE80211_S_INIT: 1269293010Sadrian /* Turn link LED off. */ 1270293010Sadrian rtwn_set_led(sc, RTWN_LED_LINK, 0); 1271293010Sadrian break; 1272293010Sadrian case IEEE80211_S_SCAN: 1273293010Sadrian /* Make link LED blink during scan. */ 1274293010Sadrian rtwn_set_led(sc, RTWN_LED_LINK, !sc->ledlink); 1275293010Sadrian 1276293010Sadrian /* Pause AC Tx queues. */ 1277293010Sadrian rtwn_write_1(sc, R92C_TXPAUSE, 1278293010Sadrian rtwn_read_1(sc, R92C_TXPAUSE) | 0x0f); 1279293010Sadrian break; 1280293010Sadrian case IEEE80211_S_AUTH: 1281293010Sadrian rtwn_set_chan(sc, ic->ic_curchan, NULL); 1282293010Sadrian break; 1283293010Sadrian case IEEE80211_S_RUN: 1284293010Sadrian if (ic->ic_opmode == IEEE80211_M_MONITOR) { 1285293010Sadrian /* Enable Rx of data frames. */ 1286293010Sadrian rtwn_write_2(sc, R92C_RXFLTMAP2, 0xffff); 1287293010Sadrian 1288293010Sadrian /* Turn link LED on. */ 1289293010Sadrian rtwn_set_led(sc, RTWN_LED_LINK, 1); 1290293010Sadrian break; 1291293010Sadrian } 1292293010Sadrian 1293293010Sadrian /* Set media status to 'Associated'. */ 1294293010Sadrian reg = rtwn_read_4(sc, R92C_CR); 1295293010Sadrian reg = RW(reg, R92C_CR_NETTYPE, R92C_CR_NETTYPE_INFRA); 1296293010Sadrian rtwn_write_4(sc, R92C_CR, reg); 1297293010Sadrian 1298293010Sadrian /* Set BSSID. */ 1299298359Savos rtwn_write_4(sc, R92C_BSSID + 0, le32dec(&ni->ni_bssid[0])); 1300298359Savos rtwn_write_4(sc, R92C_BSSID + 4, le16dec(&ni->ni_bssid[4])); 1301293010Sadrian 1302293010Sadrian if (ic->ic_curmode == IEEE80211_MODE_11B) 1303293010Sadrian rtwn_write_1(sc, R92C_INIRTS_RATE_SEL, 0); 1304293010Sadrian else /* 802.11b/g */ 1305293010Sadrian rtwn_write_1(sc, R92C_INIRTS_RATE_SEL, 3); 1306293010Sadrian 1307293010Sadrian /* Enable Rx of data frames. */ 1308293010Sadrian rtwn_write_2(sc, R92C_RXFLTMAP2, 0xffff); 1309293010Sadrian 1310293010Sadrian /* Flush all AC queues. */ 1311293010Sadrian rtwn_write_1(sc, R92C_TXPAUSE, 0); 1312293010Sadrian 1313293010Sadrian /* Set beacon interval. */ 1314293010Sadrian rtwn_write_2(sc, R92C_BCN_INTERVAL, ni->ni_intval); 1315293010Sadrian 1316293010Sadrian /* Allow Rx from our BSSID only. */ 1317293010Sadrian rtwn_write_4(sc, R92C_RCR, 1318293010Sadrian rtwn_read_4(sc, R92C_RCR) | 1319293010Sadrian R92C_RCR_CBSSID_DATA | R92C_RCR_CBSSID_BCN); 1320293010Sadrian 1321293010Sadrian /* Enable TSF synchronization. */ 1322293010Sadrian rtwn_tsf_sync_enable(sc); 1323293010Sadrian 1324293010Sadrian rtwn_write_1(sc, R92C_SIFS_CCK + 1, 10); 1325293010Sadrian rtwn_write_1(sc, R92C_SIFS_OFDM + 1, 10); 1326293010Sadrian rtwn_write_1(sc, R92C_SPEC_SIFS + 1, 10); 1327293010Sadrian rtwn_write_1(sc, R92C_MAC_SPEC_SIFS + 1, 10); 1328293010Sadrian rtwn_write_1(sc, R92C_R2T_SIFS + 1, 10); 1329293010Sadrian rtwn_write_1(sc, R92C_T2T_SIFS + 1, 10); 1330293010Sadrian 1331293010Sadrian /* Intialize rate adaptation. */ 1332293010Sadrian rtwn_ra_init(sc); 1333293010Sadrian /* Turn link LED on. */ 1334293010Sadrian rtwn_set_led(sc, RTWN_LED_LINK, 1); 1335293010Sadrian 1336293010Sadrian sc->avg_pwdb = -1; /* Reset average RSSI. */ 1337293010Sadrian /* Reset temperature calibration state machine. */ 1338293010Sadrian sc->thcal_state = 0; 1339293010Sadrian sc->thcal_lctemp = 0; 1340293010Sadrian /* Start periodic calibration. */ 1341293010Sadrian callout_reset(&sc->calib_to, hz * 2, rtwn_calib_to, sc); 1342293010Sadrian break; 1343293010Sadrian default: 1344293010Sadrian break; 1345293010Sadrian } 1346293010Sadrian RTWN_UNLOCK(sc); 1347293010Sadrian IEEE80211_LOCK(ic); 1348293010Sadrian return (rvp->newstate(vap, nstate, arg)); 1349293010Sadrian} 1350293010Sadrian 1351293010Sadrianstatic int 1352293010Sadrianrtwn_updateedca(struct ieee80211com *ic) 1353293010Sadrian{ 1354293010Sadrian struct rtwn_softc *sc = ic->ic_softc; 1355293010Sadrian const uint16_t aci2reg[WME_NUM_AC] = { 1356293010Sadrian R92C_EDCA_BE_PARAM, 1357293010Sadrian R92C_EDCA_BK_PARAM, 1358293010Sadrian R92C_EDCA_VI_PARAM, 1359293010Sadrian R92C_EDCA_VO_PARAM 1360293010Sadrian }; 1361293010Sadrian int aci, aifs, slottime; 1362293010Sadrian 1363293010Sadrian IEEE80211_LOCK(ic); 1364293010Sadrian slottime = (ic->ic_flags & IEEE80211_F_SHSLOT) ? 9 : 20; 1365293010Sadrian for (aci = 0; aci < WME_NUM_AC; aci++) { 1366293010Sadrian const struct wmeParams *ac = 1367293010Sadrian &ic->ic_wme.wme_chanParams.cap_wmeParams[aci]; 1368293010Sadrian /* AIFS[AC] = AIFSN[AC] * aSlotTime + aSIFSTime. */ 1369293010Sadrian aifs = ac->wmep_aifsn * slottime + 10; 1370293010Sadrian rtwn_write_4(sc, aci2reg[aci], 1371293010Sadrian SM(R92C_EDCA_PARAM_TXOP, ac->wmep_txopLimit) | 1372293010Sadrian SM(R92C_EDCA_PARAM_ECWMIN, ac->wmep_logcwmin) | 1373293010Sadrian SM(R92C_EDCA_PARAM_ECWMAX, ac->wmep_logcwmax) | 1374293010Sadrian SM(R92C_EDCA_PARAM_AIFS, aifs)); 1375293010Sadrian } 1376293010Sadrian IEEE80211_UNLOCK(ic); 1377293010Sadrian return (0); 1378293010Sadrian} 1379293010Sadrian 1380293010Sadrianstatic void 1381293010Sadrianrtwn_update_avgrssi(struct rtwn_softc *sc, int rate, int8_t rssi) 1382293010Sadrian{ 1383293010Sadrian int pwdb; 1384293010Sadrian 1385293010Sadrian /* Convert antenna signal to percentage. */ 1386293010Sadrian if (rssi <= -100 || rssi >= 20) 1387293010Sadrian pwdb = 0; 1388293010Sadrian else if (rssi >= 0) 1389293010Sadrian pwdb = 100; 1390293010Sadrian else 1391293010Sadrian pwdb = 100 + rssi; 1392300744Savos if (RTWN_RATE_IS_CCK(rate)) { 1393293010Sadrian /* CCK gain is smaller than OFDM/MCS gain. */ 1394293010Sadrian pwdb += 6; 1395293010Sadrian if (pwdb > 100) 1396293010Sadrian pwdb = 100; 1397293010Sadrian if (pwdb <= 14) 1398293010Sadrian pwdb -= 4; 1399293010Sadrian else if (pwdb <= 26) 1400293010Sadrian pwdb -= 8; 1401293010Sadrian else if (pwdb <= 34) 1402293010Sadrian pwdb -= 6; 1403293010Sadrian else if (pwdb <= 42) 1404293010Sadrian pwdb -= 2; 1405293010Sadrian } 1406293010Sadrian if (sc->avg_pwdb == -1) /* Init. */ 1407293010Sadrian sc->avg_pwdb = pwdb; 1408293010Sadrian else if (sc->avg_pwdb < pwdb) 1409293010Sadrian sc->avg_pwdb = ((sc->avg_pwdb * 19 + pwdb) / 20) + 1; 1410293010Sadrian else 1411293010Sadrian sc->avg_pwdb = ((sc->avg_pwdb * 19 + pwdb) / 20); 1412293010Sadrian DPRINTFN(4, ("PWDB=%d EMA=%d\n", pwdb, sc->avg_pwdb)); 1413293010Sadrian} 1414293010Sadrian 1415293010Sadrianstatic int8_t 1416293010Sadrianrtwn_get_rssi(struct rtwn_softc *sc, int rate, void *physt) 1417293010Sadrian{ 1418293010Sadrian static const int8_t cckoff[] = { 16, -12, -26, -46 }; 1419293010Sadrian struct r92c_rx_phystat *phy; 1420293010Sadrian struct r92c_rx_cck *cck; 1421293010Sadrian uint8_t rpt; 1422293010Sadrian int8_t rssi; 1423293010Sadrian 1424300744Savos if (RTWN_RATE_IS_CCK(rate)) { 1425293010Sadrian cck = (struct r92c_rx_cck *)physt; 1426293010Sadrian if (sc->sc_flags & RTWN_FLAG_CCK_HIPWR) { 1427293010Sadrian rpt = (cck->agc_rpt >> 5) & 0x3; 1428293010Sadrian rssi = (cck->agc_rpt & 0x1f) << 1; 1429293010Sadrian } else { 1430293010Sadrian rpt = (cck->agc_rpt >> 6) & 0x3; 1431293010Sadrian rssi = cck->agc_rpt & 0x3e; 1432293010Sadrian } 1433293010Sadrian rssi = cckoff[rpt] - rssi; 1434293010Sadrian } else { /* OFDM/HT. */ 1435293010Sadrian phy = (struct r92c_rx_phystat *)physt; 1436293010Sadrian rssi = ((le32toh(phy->phydw1) >> 1) & 0x7f) - 110; 1437293010Sadrian } 1438293010Sadrian return (rssi); 1439293010Sadrian} 1440293010Sadrian 1441293010Sadrianstatic void 1442293010Sadrianrtwn_rx_frame(struct rtwn_softc *sc, struct r92c_rx_desc *rx_desc, 1443293010Sadrian struct rtwn_rx_data *rx_data, int desc_idx) 1444293010Sadrian{ 1445293010Sadrian struct ieee80211com *ic = &sc->sc_ic; 1446293714Savos struct ieee80211_frame_min *wh; 1447293010Sadrian struct ieee80211_node *ni; 1448293010Sadrian struct r92c_rx_phystat *phy = NULL; 1449293010Sadrian uint32_t rxdw0, rxdw3; 1450293010Sadrian struct mbuf *m, *m1; 1451293010Sadrian bus_dma_segment_t segs[1]; 1452293010Sadrian bus_addr_t physaddr; 1453293010Sadrian uint8_t rate; 1454293010Sadrian int8_t rssi = 0, nf; 1455293010Sadrian int infosz, nsegs, pktlen, shift, error; 1456293010Sadrian 1457293010Sadrian rxdw0 = le32toh(rx_desc->rxdw0); 1458293010Sadrian rxdw3 = le32toh(rx_desc->rxdw3); 1459293010Sadrian 1460293010Sadrian if (__predict_false(rxdw0 & (R92C_RXDW0_CRCERR | R92C_RXDW0_ICVERR))) { 1461293010Sadrian /* 1462293010Sadrian * This should not happen since we setup our Rx filter 1463293010Sadrian * to not receive these frames. 1464293010Sadrian */ 1465293010Sadrian counter_u64_add(ic->ic_ierrors, 1); 1466293010Sadrian return; 1467293010Sadrian } 1468293010Sadrian 1469293010Sadrian pktlen = MS(rxdw0, R92C_RXDW0_PKTLEN); 1470293714Savos if (__predict_false(pktlen < sizeof(struct ieee80211_frame_ack) || 1471293714Savos pktlen > MCLBYTES)) { 1472293010Sadrian counter_u64_add(ic->ic_ierrors, 1); 1473293010Sadrian return; 1474293010Sadrian } 1475293010Sadrian 1476293010Sadrian rate = MS(rxdw3, R92C_RXDW3_RATE); 1477293010Sadrian infosz = MS(rxdw0, R92C_RXDW0_INFOSZ) * 8; 1478293010Sadrian if (infosz > sizeof(struct r92c_rx_phystat)) 1479293010Sadrian infosz = sizeof(struct r92c_rx_phystat); 1480293010Sadrian shift = MS(rxdw0, R92C_RXDW0_SHIFT); 1481293010Sadrian 1482293010Sadrian /* Get RSSI from PHY status descriptor if present. */ 1483293010Sadrian if (infosz != 0 && (rxdw0 & R92C_RXDW0_PHYST)) { 1484293010Sadrian phy = mtod(rx_data->m, struct r92c_rx_phystat *); 1485293010Sadrian rssi = rtwn_get_rssi(sc, rate, phy); 1486293010Sadrian /* Update our average RSSI. */ 1487293010Sadrian rtwn_update_avgrssi(sc, rate, rssi); 1488293010Sadrian } 1489293010Sadrian 1490293010Sadrian DPRINTFN(5, ("Rx frame len=%d rate=%d infosz=%d shift=%d rssi=%d\n", 1491293010Sadrian pktlen, rate, infosz, shift, rssi)); 1492293010Sadrian 1493293010Sadrian m1 = m_getcl(M_NOWAIT, MT_DATA, M_PKTHDR); 1494293010Sadrian if (m1 == NULL) { 1495293010Sadrian counter_u64_add(ic->ic_ierrors, 1); 1496293010Sadrian return; 1497293010Sadrian } 1498293010Sadrian bus_dmamap_unload(sc->rx_ring.data_dmat, rx_data->map); 1499293010Sadrian 1500293010Sadrian error = bus_dmamap_load(sc->rx_ring.data_dmat, rx_data->map, 1501293010Sadrian mtod(m1, void *), MCLBYTES, rtwn_dma_map_addr, 1502293010Sadrian &physaddr, 0); 1503293010Sadrian if (error != 0) { 1504293010Sadrian m_freem(m1); 1505293010Sadrian 1506293010Sadrian if (bus_dmamap_load_mbuf_sg(sc->rx_ring.data_dmat, 1507293010Sadrian rx_data->map, rx_data->m, segs, &nsegs, 0)) 1508293010Sadrian panic("%s: could not load old RX mbuf", 1509293010Sadrian device_get_name(sc->sc_dev)); 1510293010Sadrian 1511293010Sadrian /* Physical address may have changed. */ 1512293010Sadrian rtwn_setup_rx_desc(sc, rx_desc, physaddr, MCLBYTES, desc_idx); 1513293010Sadrian counter_u64_add(ic->ic_ierrors, 1); 1514293010Sadrian return; 1515293010Sadrian } 1516293010Sadrian 1517293010Sadrian /* Finalize mbuf. */ 1518293010Sadrian m = rx_data->m; 1519293010Sadrian rx_data->m = m1; 1520293010Sadrian m->m_pkthdr.len = m->m_len = pktlen + infosz + shift; 1521293010Sadrian 1522293010Sadrian /* Update RX descriptor. */ 1523293010Sadrian rtwn_setup_rx_desc(sc, rx_desc, physaddr, MCLBYTES, desc_idx); 1524293010Sadrian 1525293010Sadrian /* Get ieee80211 frame header. */ 1526293010Sadrian if (rxdw0 & R92C_RXDW0_PHYST) 1527293010Sadrian m_adj(m, infosz + shift); 1528293010Sadrian else 1529293010Sadrian m_adj(m, shift); 1530293010Sadrian 1531293010Sadrian nf = -95; 1532293010Sadrian if (ieee80211_radiotap_active(ic)) { 1533293010Sadrian struct rtwn_rx_radiotap_header *tap = &sc->sc_rxtap; 1534293010Sadrian 1535293010Sadrian tap->wr_flags = 0; 1536293010Sadrian if (!(rxdw3 & R92C_RXDW3_HT)) { 1537300744Savos tap->wr_rate = ridx2rate[rate]; 1538293010Sadrian } else if (rate >= 12) { /* MCS0~15. */ 1539293010Sadrian /* Bit 7 set means HT MCS instead of rate. */ 1540293010Sadrian tap->wr_rate = 0x80 | (rate - 12); 1541293010Sadrian } 1542293010Sadrian tap->wr_dbm_antsignal = rssi; 1543293010Sadrian } 1544293010Sadrian 1545293010Sadrian RTWN_UNLOCK(sc); 1546293714Savos wh = mtod(m, struct ieee80211_frame_min *); 1547293714Savos if (m->m_len >= sizeof(*wh)) 1548293714Savos ni = ieee80211_find_rxnode(ic, wh); 1549293714Savos else 1550293714Savos ni = NULL; 1551293010Sadrian 1552293010Sadrian /* Send the frame to the 802.11 layer. */ 1553293010Sadrian if (ni != NULL) { 1554293010Sadrian (void)ieee80211_input(ni, m, rssi - nf, nf); 1555293010Sadrian /* Node is no longer needed. */ 1556293010Sadrian ieee80211_free_node(ni); 1557293010Sadrian } else 1558293010Sadrian (void)ieee80211_input_all(ic, m, rssi - nf, nf); 1559293010Sadrian 1560293010Sadrian RTWN_LOCK(sc); 1561293010Sadrian} 1562293010Sadrian 1563293010Sadrianstatic int 1564293010Sadrianrtwn_tx(struct rtwn_softc *sc, struct mbuf *m, struct ieee80211_node *ni) 1565293010Sadrian{ 1566293010Sadrian struct ieee80211com *ic = &sc->sc_ic; 1567293010Sadrian struct ieee80211vap *vap = ni->ni_vap; 1568293010Sadrian struct ieee80211_frame *wh; 1569293010Sadrian struct ieee80211_key *k = NULL; 1570293010Sadrian struct rtwn_tx_ring *tx_ring; 1571293010Sadrian struct rtwn_tx_data *data; 1572293010Sadrian struct r92c_tx_desc *txd; 1573293010Sadrian bus_dma_segment_t segs[1]; 1574293010Sadrian uint16_t qos; 1575293010Sadrian uint8_t raid, type, tid, qid; 1576293010Sadrian int nsegs, error; 1577293010Sadrian 1578293010Sadrian wh = mtod(m, struct ieee80211_frame *); 1579293010Sadrian type = wh->i_fc[0] & IEEE80211_FC0_TYPE_MASK; 1580293010Sadrian 1581293010Sadrian /* Encrypt the frame if need be. */ 1582293010Sadrian if (wh->i_fc[1] & IEEE80211_FC1_PROTECTED) { 1583293010Sadrian k = ieee80211_crypto_encap(ni, m); 1584293010Sadrian if (k == NULL) { 1585293010Sadrian m_freem(m); 1586293010Sadrian return (ENOBUFS); 1587293010Sadrian } 1588293010Sadrian /* 802.11 header may have moved. */ 1589293010Sadrian wh = mtod(m, struct ieee80211_frame *); 1590293010Sadrian } 1591293010Sadrian 1592293010Sadrian if (IEEE80211_QOS_HAS_SEQ(wh)) { 1593293010Sadrian qos = ((const struct ieee80211_qosframe *)wh)->i_qos[0]; 1594293010Sadrian tid = qos & IEEE80211_QOS_TID; 1595293010Sadrian } else { 1596293010Sadrian qos = 0; 1597293010Sadrian tid = 0; 1598293010Sadrian } 1599293010Sadrian 1600293010Sadrian switch (type) { 1601293010Sadrian case IEEE80211_FC0_TYPE_CTL: 1602293010Sadrian case IEEE80211_FC0_TYPE_MGT: 1603293010Sadrian qid = RTWN_VO_QUEUE; 1604293010Sadrian break; 1605293010Sadrian default: 1606293010Sadrian qid = M_WME_GETAC(m); 1607293010Sadrian break; 1608293010Sadrian } 1609293010Sadrian 1610293010Sadrian /* Grab a Tx buffer from the ring. */ 1611293010Sadrian tx_ring = &sc->tx_ring[qid]; 1612293010Sadrian data = &tx_ring->tx_data[tx_ring->cur]; 1613293010Sadrian if (data->m != NULL) { 1614293010Sadrian m_freem(m); 1615293010Sadrian return (ENOBUFS); 1616293010Sadrian } 1617293010Sadrian 1618293010Sadrian /* Fill Tx descriptor. */ 1619293010Sadrian txd = &tx_ring->desc[tx_ring->cur]; 1620293010Sadrian if (htole32(txd->txdw0) & R92C_RXDW0_OWN) { 1621293010Sadrian m_freem(m); 1622293010Sadrian return (ENOBUFS); 1623293010Sadrian } 1624293010Sadrian txd->txdw0 = htole32( 1625293010Sadrian SM(R92C_TXDW0_PKTLEN, m->m_pkthdr.len) | 1626293010Sadrian SM(R92C_TXDW0_OFFSET, sizeof(*txd)) | 1627293010Sadrian R92C_TXDW0_FSG | R92C_TXDW0_LSG); 1628293010Sadrian if (IEEE80211_IS_MULTICAST(wh->i_addr1)) 1629293010Sadrian txd->txdw0 |= htole32(R92C_TXDW0_BMCAST); 1630293010Sadrian 1631293010Sadrian txd->txdw1 = 0; 1632293010Sadrian txd->txdw4 = 0; 1633293010Sadrian txd->txdw5 = 0; 1634293010Sadrian 1635293010Sadrian /* XXX TODO: rate control; implement low-rate for EAPOL */ 1636293010Sadrian if (!IEEE80211_IS_MULTICAST(wh->i_addr1) && 1637293010Sadrian type == IEEE80211_FC0_TYPE_DATA) { 1638293010Sadrian if (ic->ic_curmode == IEEE80211_MODE_11B) 1639293010Sadrian raid = R92C_RAID_11B; 1640293010Sadrian else 1641293010Sadrian raid = R92C_RAID_11BG; 1642293010Sadrian txd->txdw1 |= htole32( 1643293010Sadrian SM(R92C_TXDW1_MACID, RTWN_MACID_BSS) | 1644293010Sadrian SM(R92C_TXDW1_QSEL, R92C_TXDW1_QSEL_BE) | 1645293010Sadrian SM(R92C_TXDW1_RAID, raid) | 1646293010Sadrian R92C_TXDW1_AGGBK); 1647293010Sadrian 1648293010Sadrian if (ic->ic_flags & IEEE80211_F_USEPROT) { 1649293010Sadrian if (ic->ic_protmode == IEEE80211_PROT_CTSONLY) { 1650293010Sadrian txd->txdw4 |= htole32(R92C_TXDW4_CTS2SELF | 1651293010Sadrian R92C_TXDW4_HWRTSEN); 1652293010Sadrian } else if (ic->ic_protmode == IEEE80211_PROT_RTSCTS) { 1653293010Sadrian txd->txdw4 |= htole32(R92C_TXDW4_RTSEN | 1654293010Sadrian R92C_TXDW4_HWRTSEN); 1655293010Sadrian } 1656293010Sadrian } 1657293010Sadrian 1658293010Sadrian /* XXX TODO: implement rate control */ 1659293010Sadrian 1660293010Sadrian /* Send RTS at OFDM24. */ 1661300744Savos txd->txdw4 |= htole32(SM(R92C_TXDW4_RTSRATE, 1662300744Savos RTWN_RIDX_OFDM24)); 1663293010Sadrian txd->txdw5 |= htole32(SM(R92C_TXDW5_RTSRATE_FBLIMIT, 0xf)); 1664293010Sadrian /* Send data at OFDM54. */ 1665300744Savos txd->txdw5 |= htole32(SM(R92C_TXDW5_DATARATE, 1666300744Savos RTWN_RIDX_OFDM54)); 1667293010Sadrian txd->txdw5 |= htole32(SM(R92C_TXDW5_DATARATE_FBLIMIT, 0x1f)); 1668293010Sadrian 1669293010Sadrian } else { 1670293010Sadrian txd->txdw1 |= htole32( 1671293010Sadrian SM(R92C_TXDW1_MACID, 0) | 1672293010Sadrian SM(R92C_TXDW1_QSEL, R92C_TXDW1_QSEL_MGNT) | 1673293010Sadrian SM(R92C_TXDW1_RAID, R92C_RAID_11B)); 1674293010Sadrian 1675293010Sadrian /* Force CCK1. */ 1676293010Sadrian txd->txdw4 |= htole32(R92C_TXDW4_DRVRATE); 1677300744Savos txd->txdw5 |= htole32(SM(R92C_TXDW5_DATARATE, RTWN_RIDX_CCK1)); 1678293010Sadrian } 1679293010Sadrian /* Set sequence number (already little endian). */ 1680293616Savos txd->txdseq = htole16(M_SEQNO_GET(m) % IEEE80211_SEQ_RANGE); 1681293010Sadrian 1682293010Sadrian if (!qos) { 1683293010Sadrian /* Use HW sequence numbering for non-QoS frames. */ 1684293010Sadrian txd->txdw4 |= htole32(R92C_TXDW4_HWSEQ); 1685293010Sadrian txd->txdseq |= htole16(0x8000); 1686293010Sadrian } else 1687293010Sadrian txd->txdw4 |= htole32(R92C_TXDW4_QOS); 1688293010Sadrian 1689293010Sadrian error = bus_dmamap_load_mbuf_sg(tx_ring->data_dmat, data->map, m, segs, 1690293010Sadrian &nsegs, BUS_DMA_NOWAIT); 1691293010Sadrian if (error != 0 && error != EFBIG) { 1692293010Sadrian device_printf(sc->sc_dev, "can't map mbuf (error %d)\n", error); 1693293010Sadrian m_freem(m); 1694293010Sadrian return (error); 1695293010Sadrian } 1696293010Sadrian if (error != 0) { 1697293010Sadrian struct mbuf *mnew; 1698293010Sadrian 1699293010Sadrian mnew = m_defrag(m, M_NOWAIT); 1700293010Sadrian if (mnew == NULL) { 1701293010Sadrian device_printf(sc->sc_dev, 1702293010Sadrian "can't defragment mbuf\n"); 1703293010Sadrian m_freem(m); 1704293010Sadrian return (ENOBUFS); 1705293010Sadrian } 1706293010Sadrian m = mnew; 1707293010Sadrian 1708293010Sadrian error = bus_dmamap_load_mbuf_sg(tx_ring->data_dmat, data->map, 1709293010Sadrian m, segs, &nsegs, BUS_DMA_NOWAIT); 1710293010Sadrian if (error != 0) { 1711293010Sadrian device_printf(sc->sc_dev, 1712293010Sadrian "can't map mbuf (error %d)\n", error); 1713293010Sadrian m_freem(m); 1714293010Sadrian return (error); 1715293010Sadrian } 1716293010Sadrian } 1717293010Sadrian 1718293010Sadrian txd->txbufaddr = htole32(segs[0].ds_addr); 1719293010Sadrian txd->txbufsize = htole16(m->m_pkthdr.len); 1720293010Sadrian bus_space_barrier(sc->sc_st, sc->sc_sh, 0, sc->sc_mapsize, 1721293010Sadrian BUS_SPACE_BARRIER_WRITE); 1722293010Sadrian txd->txdw0 |= htole32(R92C_TXDW0_OWN); 1723293010Sadrian 1724293010Sadrian bus_dmamap_sync(tx_ring->desc_dmat, tx_ring->desc_map, 1725293010Sadrian BUS_DMASYNC_POSTWRITE); 1726293010Sadrian bus_dmamap_sync(tx_ring->data_dmat, data->map, BUS_DMASYNC_POSTWRITE); 1727293010Sadrian 1728293010Sadrian data->m = m; 1729293010Sadrian data->ni = ni; 1730293010Sadrian 1731293010Sadrian if (ieee80211_radiotap_active_vap(vap)) { 1732293010Sadrian struct rtwn_tx_radiotap_header *tap = &sc->sc_txtap; 1733293010Sadrian 1734293010Sadrian tap->wt_flags = 0; 1735293010Sadrian 1736293010Sadrian ieee80211_radiotap_tx(vap, m); 1737293010Sadrian } 1738293010Sadrian 1739293010Sadrian tx_ring->cur = (tx_ring->cur + 1) % RTWN_TX_LIST_COUNT; 1740293010Sadrian tx_ring->queued++; 1741293010Sadrian 1742293010Sadrian if (tx_ring->queued >= (RTWN_TX_LIST_COUNT - 1)) 1743293010Sadrian sc->qfullmsk |= (1 << qid); 1744293010Sadrian 1745293010Sadrian /* Kick TX. */ 1746293010Sadrian rtwn_write_2(sc, R92C_PCIE_CTRL_REG, (1 << qid)); 1747293010Sadrian return (0); 1748293010Sadrian} 1749293010Sadrian 1750293010Sadrianstatic void 1751293010Sadrianrtwn_tx_done(struct rtwn_softc *sc, int qid) 1752293010Sadrian{ 1753293010Sadrian struct rtwn_tx_ring *tx_ring = &sc->tx_ring[qid]; 1754293010Sadrian struct rtwn_tx_data *tx_data; 1755293010Sadrian struct r92c_tx_desc *tx_desc; 1756293010Sadrian int i; 1757293010Sadrian 1758293010Sadrian bus_dmamap_sync(tx_ring->desc_dmat, tx_ring->desc_map, 1759293010Sadrian BUS_DMASYNC_POSTREAD); 1760293010Sadrian 1761293010Sadrian for (i = 0; i < RTWN_TX_LIST_COUNT; i++) { 1762293010Sadrian tx_data = &tx_ring->tx_data[i]; 1763293010Sadrian if (tx_data->m == NULL) 1764293010Sadrian continue; 1765293010Sadrian 1766293010Sadrian tx_desc = &tx_ring->desc[i]; 1767293010Sadrian if (le32toh(tx_desc->txdw0) & R92C_TXDW0_OWN) 1768293010Sadrian continue; 1769293010Sadrian 1770302035Savos /* Unmap and free mbuf. */ 1771302035Savos bus_dmamap_sync(tx_ring->data_dmat, tx_data->map, 1772302035Savos BUS_DMASYNC_POSTWRITE); 1773302035Savos bus_dmamap_unload(tx_ring->data_dmat, tx_data->map); 1774293010Sadrian 1775293010Sadrian /* 1776293010Sadrian * XXX TODO: figure out whether the transmit succeeded or not. 1777293010Sadrian * .. and then notify rate control. 1778293010Sadrian */ 1779293010Sadrian ieee80211_tx_complete(tx_data->ni, tx_data->m, 0); 1780293010Sadrian tx_data->ni = NULL; 1781293010Sadrian tx_data->m = NULL; 1782293010Sadrian 1783302035Savos if (--tx_ring->queued) 1784302035Savos sc->sc_tx_timer = 5; 1785302035Savos else 1786302035Savos sc->sc_tx_timer = 0; 1787293010Sadrian } 1788293010Sadrian 1789293010Sadrian if (tx_ring->queued < (RTWN_TX_LIST_COUNT - 1)) 1790293010Sadrian sc->qfullmsk &= ~(1 << qid); 1791293010Sadrian rtwn_start(sc); 1792293010Sadrian} 1793293010Sadrian 1794293010Sadrianstatic int 1795293010Sadrianrtwn_raw_xmit(struct ieee80211_node *ni, struct mbuf *m, 1796293010Sadrian const struct ieee80211_bpf_params *params) 1797293010Sadrian{ 1798293010Sadrian struct ieee80211com *ic = ni->ni_ic; 1799293010Sadrian struct rtwn_softc *sc = ic->ic_softc; 1800293010Sadrian 1801293010Sadrian RTWN_LOCK(sc); 1802293010Sadrian 1803293010Sadrian /* Prevent management frames from being sent if we're not ready. */ 1804293010Sadrian if (!(sc->sc_flags & RTWN_RUNNING)) { 1805293010Sadrian RTWN_UNLOCK(sc); 1806293010Sadrian m_freem(m); 1807293010Sadrian return (ENETDOWN); 1808293010Sadrian } 1809293010Sadrian 1810293010Sadrian if (rtwn_tx(sc, m, ni) != 0) { 1811293010Sadrian RTWN_UNLOCK(sc); 1812293010Sadrian return (EIO); 1813293010Sadrian } 1814293010Sadrian sc->sc_tx_timer = 5; 1815293010Sadrian RTWN_UNLOCK(sc); 1816293010Sadrian return (0); 1817293010Sadrian} 1818293010Sadrian 1819293010Sadrianstatic int 1820293010Sadrianrtwn_transmit(struct ieee80211com *ic, struct mbuf *m) 1821293010Sadrian{ 1822293010Sadrian struct rtwn_softc *sc = ic->ic_softc; 1823293010Sadrian int error; 1824293010Sadrian 1825293010Sadrian RTWN_LOCK(sc); 1826293010Sadrian if ((sc->sc_flags & RTWN_RUNNING) == 0) { 1827293010Sadrian RTWN_UNLOCK(sc); 1828293010Sadrian return (ENXIO); 1829293010Sadrian } 1830293010Sadrian error = mbufq_enqueue(&sc->sc_snd, m); 1831293010Sadrian if (error) { 1832293010Sadrian RTWN_UNLOCK(sc); 1833293010Sadrian return (error); 1834293010Sadrian } 1835293010Sadrian rtwn_start(sc); 1836293010Sadrian RTWN_UNLOCK(sc); 1837293010Sadrian return (0); 1838293010Sadrian} 1839293010Sadrian 1840293010Sadrianstatic void 1841293010Sadrianrtwn_parent(struct ieee80211com *ic) 1842293010Sadrian{ 1843293010Sadrian struct rtwn_softc *sc = ic->ic_softc; 1844294842Savos struct ieee80211vap *vap = TAILQ_FIRST(&ic->ic_vaps); 1845293010Sadrian 1846294842Savos if (ic->ic_nrunning > 0) { 1847294842Savos if (rtwn_init(sc) == 0) 1848294842Savos ieee80211_start_all(ic); 1849294842Savos else 1850294842Savos ieee80211_stop(vap); 1851294842Savos } else 1852294842Savos rtwn_stop(sc); 1853293010Sadrian} 1854293010Sadrian 1855293010Sadrianstatic void 1856293010Sadrianrtwn_start(struct rtwn_softc *sc) 1857293010Sadrian{ 1858293010Sadrian struct ieee80211_node *ni; 1859293010Sadrian struct mbuf *m; 1860293010Sadrian 1861293010Sadrian RTWN_LOCK_ASSERT(sc); 1862293010Sadrian 1863293010Sadrian if ((sc->sc_flags & RTWN_RUNNING) == 0) 1864293010Sadrian return; 1865293010Sadrian 1866293010Sadrian while (sc->qfullmsk == 0 && (m = mbufq_dequeue(&sc->sc_snd)) != NULL) { 1867293010Sadrian ni = (struct ieee80211_node *)m->m_pkthdr.rcvif; 1868293010Sadrian if (rtwn_tx(sc, m, ni) != 0) { 1869293010Sadrian if_inc_counter(ni->ni_vap->iv_ifp, 1870293010Sadrian IFCOUNTER_OERRORS, 1); 1871293010Sadrian ieee80211_free_node(ni); 1872293010Sadrian continue; 1873293010Sadrian } 1874293010Sadrian sc->sc_tx_timer = 5; 1875293010Sadrian } 1876293010Sadrian} 1877293010Sadrian 1878293010Sadrianstatic void 1879293010Sadrianrtwn_watchdog(void *arg) 1880293010Sadrian{ 1881293010Sadrian struct rtwn_softc *sc = arg; 1882293010Sadrian struct ieee80211com *ic = &sc->sc_ic; 1883293010Sadrian 1884293010Sadrian RTWN_LOCK_ASSERT(sc); 1885293010Sadrian 1886293010Sadrian KASSERT(sc->sc_flags & RTWN_RUNNING, ("not running")); 1887293010Sadrian 1888293010Sadrian if (sc->sc_tx_timer != 0 && --sc->sc_tx_timer == 0) { 1889293010Sadrian ic_printf(ic, "device timeout\n"); 1890294841Savos ieee80211_restart_all(ic); 1891293010Sadrian return; 1892293010Sadrian } 1893293010Sadrian callout_reset(&sc->watchdog_to, hz, rtwn_watchdog, sc); 1894293010Sadrian} 1895293010Sadrian 1896293010Sadrianstatic int 1897293010Sadrianrtwn_power_on(struct rtwn_softc *sc) 1898293010Sadrian{ 1899293010Sadrian uint32_t reg; 1900293010Sadrian int ntries; 1901293010Sadrian 1902293010Sadrian /* Wait for autoload done bit. */ 1903293010Sadrian for (ntries = 0; ntries < 1000; ntries++) { 1904293010Sadrian if (rtwn_read_1(sc, R92C_APS_FSMCO) & R92C_APS_FSMCO_PFM_ALDN) 1905293010Sadrian break; 1906293010Sadrian DELAY(5); 1907293010Sadrian } 1908293010Sadrian if (ntries == 1000) { 1909293010Sadrian device_printf(sc->sc_dev, 1910293010Sadrian "timeout waiting for chip autoload\n"); 1911293010Sadrian return (ETIMEDOUT); 1912293010Sadrian } 1913293010Sadrian 1914293010Sadrian /* Unlock ISO/CLK/Power control register. */ 1915293010Sadrian rtwn_write_1(sc, R92C_RSV_CTRL, 0); 1916293010Sadrian 1917293010Sadrian /* TODO: check if we need this for 8188CE */ 1918293010Sadrian if (sc->board_type != R92C_BOARD_TYPE_DONGLE) { 1919293010Sadrian /* bt coex */ 1920293010Sadrian reg = rtwn_read_4(sc, R92C_APS_FSMCO); 1921293010Sadrian reg |= (R92C_APS_FSMCO_SOP_ABG | 1922293010Sadrian R92C_APS_FSMCO_SOP_AMB | 1923293010Sadrian R92C_APS_FSMCO_XOP_BTCK); 1924293010Sadrian rtwn_write_4(sc, R92C_APS_FSMCO, reg); 1925293010Sadrian } 1926293010Sadrian 1927293010Sadrian /* Move SPS into PWM mode. */ 1928293010Sadrian rtwn_write_1(sc, R92C_SPS0_CTRL, 0x2b); 1929293010Sadrian 1930293010Sadrian /* Set low byte to 0x0f, leave others unchanged. */ 1931293010Sadrian rtwn_write_4(sc, R92C_AFE_XTAL_CTRL, 1932293010Sadrian (rtwn_read_4(sc, R92C_AFE_XTAL_CTRL) & 0xffffff00) | 0x0f); 1933293010Sadrian 1934293010Sadrian /* TODO: check if we need this for 8188CE */ 1935293010Sadrian if (sc->board_type != R92C_BOARD_TYPE_DONGLE) { 1936293010Sadrian /* bt coex */ 1937293010Sadrian reg = rtwn_read_4(sc, R92C_AFE_XTAL_CTRL); 1938293010Sadrian reg &= (~0x00024800); /* XXX magic from linux */ 1939293010Sadrian rtwn_write_4(sc, R92C_AFE_XTAL_CTRL, reg); 1940293010Sadrian } 1941293010Sadrian 1942293010Sadrian rtwn_write_2(sc, R92C_SYS_ISO_CTRL, 1943293010Sadrian (rtwn_read_2(sc, R92C_SYS_ISO_CTRL) & 0xff) | 1944293010Sadrian R92C_SYS_ISO_CTRL_PWC_EV12V | R92C_SYS_ISO_CTRL_DIOR); 1945293010Sadrian DELAY(200); 1946293010Sadrian 1947293010Sadrian /* TODO: linux does additional btcoex stuff here */ 1948293010Sadrian 1949293010Sadrian /* Auto enable WLAN. */ 1950293010Sadrian rtwn_write_2(sc, R92C_APS_FSMCO, 1951293010Sadrian rtwn_read_2(sc, R92C_APS_FSMCO) | R92C_APS_FSMCO_APFM_ONMAC); 1952293010Sadrian for (ntries = 0; ntries < 1000; ntries++) { 1953293010Sadrian if (!(rtwn_read_2(sc, R92C_APS_FSMCO) & 1954293010Sadrian R92C_APS_FSMCO_APFM_ONMAC)) 1955293010Sadrian break; 1956293010Sadrian DELAY(5); 1957293010Sadrian } 1958293010Sadrian if (ntries == 1000) { 1959293010Sadrian device_printf(sc->sc_dev, "timeout waiting for MAC auto ON\n"); 1960293010Sadrian return (ETIMEDOUT); 1961293010Sadrian } 1962293010Sadrian 1963293010Sadrian /* Enable radio, GPIO and LED functions. */ 1964293010Sadrian rtwn_write_2(sc, R92C_APS_FSMCO, 1965293010Sadrian R92C_APS_FSMCO_AFSM_PCIE | 1966293010Sadrian R92C_APS_FSMCO_PDN_EN | 1967293010Sadrian R92C_APS_FSMCO_PFM_ALDN); 1968293010Sadrian /* Release RF digital isolation. */ 1969293010Sadrian rtwn_write_2(sc, R92C_SYS_ISO_CTRL, 1970293010Sadrian rtwn_read_2(sc, R92C_SYS_ISO_CTRL) & ~R92C_SYS_ISO_CTRL_DIOR); 1971293010Sadrian 1972293010Sadrian if (sc->chip & RTWN_CHIP_92C) 1973293010Sadrian rtwn_write_1(sc, R92C_PCIE_CTRL_REG + 3, 0x77); 1974293010Sadrian else 1975293010Sadrian rtwn_write_1(sc, R92C_PCIE_CTRL_REG + 3, 0x22); 1976293010Sadrian 1977293010Sadrian rtwn_write_4(sc, R92C_INT_MIG, 0); 1978293010Sadrian 1979293010Sadrian if (sc->board_type != R92C_BOARD_TYPE_DONGLE) { 1980293010Sadrian /* bt coex */ 1981293010Sadrian reg = rtwn_read_4(sc, R92C_AFE_XTAL_CTRL + 2); 1982293010Sadrian reg &= 0xfd; /* XXX magic from linux */ 1983293010Sadrian rtwn_write_4(sc, R92C_AFE_XTAL_CTRL + 2, reg); 1984293010Sadrian } 1985293010Sadrian 1986293010Sadrian rtwn_write_1(sc, R92C_GPIO_MUXCFG, 1987293010Sadrian rtwn_read_1(sc, R92C_GPIO_MUXCFG) & ~R92C_GPIO_MUXCFG_RFKILL); 1988293010Sadrian 1989293010Sadrian reg = rtwn_read_1(sc, R92C_GPIO_IO_SEL); 1990293010Sadrian if (!(reg & R92C_GPIO_IO_SEL_RFKILL)) { 1991293010Sadrian device_printf(sc->sc_dev, 1992293010Sadrian "radio is disabled by hardware switch\n"); 1993293010Sadrian return (EPERM); 1994293010Sadrian } 1995293010Sadrian 1996293010Sadrian /* Initialize MAC. */ 1997293010Sadrian reg = rtwn_read_1(sc, R92C_APSD_CTRL); 1998293010Sadrian rtwn_write_1(sc, R92C_APSD_CTRL, 1999293010Sadrian rtwn_read_1(sc, R92C_APSD_CTRL) & ~R92C_APSD_CTRL_OFF); 2000293010Sadrian for (ntries = 0; ntries < 200; ntries++) { 2001293010Sadrian if (!(rtwn_read_1(sc, R92C_APSD_CTRL) & 2002293010Sadrian R92C_APSD_CTRL_OFF_STATUS)) 2003293010Sadrian break; 2004293010Sadrian DELAY(500); 2005293010Sadrian } 2006293010Sadrian if (ntries == 200) { 2007293010Sadrian device_printf(sc->sc_dev, 2008293010Sadrian "timeout waiting for MAC initialization\n"); 2009293010Sadrian return (ETIMEDOUT); 2010293010Sadrian } 2011293010Sadrian 2012293010Sadrian /* Enable MAC DMA/WMAC/SCHEDULE/SEC blocks. */ 2013293010Sadrian reg = rtwn_read_2(sc, R92C_CR); 2014293010Sadrian reg |= R92C_CR_HCI_TXDMA_EN | R92C_CR_HCI_RXDMA_EN | 2015293010Sadrian R92C_CR_TXDMA_EN | R92C_CR_RXDMA_EN | R92C_CR_PROTOCOL_EN | 2016293010Sadrian R92C_CR_SCHEDULE_EN | R92C_CR_MACTXEN | R92C_CR_MACRXEN | 2017293010Sadrian R92C_CR_ENSEC; 2018293010Sadrian rtwn_write_2(sc, R92C_CR, reg); 2019293010Sadrian 2020293010Sadrian rtwn_write_1(sc, 0xfe10, 0x19); 2021293010Sadrian 2022293010Sadrian return (0); 2023293010Sadrian} 2024293010Sadrian 2025293010Sadrianstatic int 2026293010Sadrianrtwn_llt_init(struct rtwn_softc *sc) 2027293010Sadrian{ 2028293010Sadrian int i, error; 2029293010Sadrian 2030293010Sadrian /* Reserve pages [0; R92C_TX_PAGE_COUNT]. */ 2031293010Sadrian for (i = 0; i < R92C_TX_PAGE_COUNT; i++) { 2032293010Sadrian if ((error = rtwn_llt_write(sc, i, i + 1)) != 0) 2033293010Sadrian return (error); 2034293010Sadrian } 2035293010Sadrian /* NB: 0xff indicates end-of-list. */ 2036293010Sadrian if ((error = rtwn_llt_write(sc, i, 0xff)) != 0) 2037293010Sadrian return (error); 2038293010Sadrian /* 2039293010Sadrian * Use pages [R92C_TX_PAGE_COUNT + 1; R92C_TXPKTBUF_COUNT - 1] 2040293010Sadrian * as ring buffer. 2041293010Sadrian */ 2042293010Sadrian for (++i; i < R92C_TXPKTBUF_COUNT - 1; i++) { 2043293010Sadrian if ((error = rtwn_llt_write(sc, i, i + 1)) != 0) 2044293010Sadrian return (error); 2045293010Sadrian } 2046293010Sadrian /* Make the last page point to the beginning of the ring buffer. */ 2047293010Sadrian error = rtwn_llt_write(sc, i, R92C_TX_PAGE_COUNT + 1); 2048293010Sadrian return (error); 2049293010Sadrian} 2050293010Sadrian 2051293010Sadrianstatic void 2052293010Sadrianrtwn_fw_reset(struct rtwn_softc *sc) 2053293010Sadrian{ 2054293010Sadrian uint16_t reg; 2055293010Sadrian int ntries; 2056293010Sadrian 2057293010Sadrian /* Tell 8051 to reset itself. */ 2058293010Sadrian rtwn_write_1(sc, R92C_HMETFR + 3, 0x20); 2059293010Sadrian 2060293010Sadrian /* Wait until 8051 resets by itself. */ 2061293010Sadrian for (ntries = 0; ntries < 100; ntries++) { 2062293010Sadrian reg = rtwn_read_2(sc, R92C_SYS_FUNC_EN); 2063293010Sadrian if (!(reg & R92C_SYS_FUNC_EN_CPUEN)) 2064293010Sadrian goto sleep; 2065293010Sadrian DELAY(50); 2066293010Sadrian } 2067293010Sadrian /* Force 8051 reset. */ 2068293010Sadrian rtwn_write_2(sc, R92C_SYS_FUNC_EN, reg & ~R92C_SYS_FUNC_EN_CPUEN); 2069293010Sadriansleep: 2070293010Sadrian /* 2071293010Sadrian * We must sleep for one second to let the firmware settle. 2072293010Sadrian * Accessing registers too early will hang the whole system. 2073293010Sadrian */ 2074293010Sadrian if (msleep(®, &sc->sc_mtx, 0, "rtwnrst", hz)) { 2075293010Sadrian device_printf(sc->sc_dev, "timeout waiting for firmware " 2076293010Sadrian "initialization to complete\n"); 2077293010Sadrian } 2078293010Sadrian} 2079293010Sadrian 2080293010Sadrianstatic void 2081293010Sadrianrtwn_fw_loadpage(struct rtwn_softc *sc, int page, const uint8_t *buf, int len) 2082293010Sadrian{ 2083293010Sadrian uint32_t reg; 2084293010Sadrian int off, mlen, i; 2085293010Sadrian 2086293010Sadrian reg = rtwn_read_4(sc, R92C_MCUFWDL); 2087293010Sadrian reg = RW(reg, R92C_MCUFWDL_PAGE, page); 2088293010Sadrian rtwn_write_4(sc, R92C_MCUFWDL, reg); 2089293010Sadrian 2090293010Sadrian DELAY(5); 2091293010Sadrian 2092293010Sadrian off = R92C_FW_START_ADDR; 2093293010Sadrian while (len > 0) { 2094293010Sadrian if (len > 196) 2095293010Sadrian mlen = 196; 2096293010Sadrian else if (len > 4) 2097293010Sadrian mlen = 4; 2098293010Sadrian else 2099293010Sadrian mlen = 1; 2100293010Sadrian for (i = 0; i < mlen; i++) 2101293010Sadrian rtwn_write_1(sc, off++, buf[i]); 2102293010Sadrian buf += mlen; 2103293010Sadrian len -= mlen; 2104293010Sadrian } 2105293010Sadrian} 2106293010Sadrian 2107293010Sadrianstatic int 2108293010Sadrianrtwn_load_firmware(struct rtwn_softc *sc) 2109293010Sadrian{ 2110293010Sadrian const struct firmware *fw; 2111293010Sadrian const struct r92c_fw_hdr *hdr; 2112293010Sadrian const char *name; 2113293010Sadrian const u_char *ptr; 2114293010Sadrian size_t len; 2115293010Sadrian uint32_t reg; 2116293010Sadrian int mlen, ntries, page, error = 0; 2117293010Sadrian 2118293010Sadrian /* Read firmware image from the filesystem. */ 2119293010Sadrian if ((sc->chip & (RTWN_CHIP_UMC_A_CUT | RTWN_CHIP_92C)) == 2120293010Sadrian RTWN_CHIP_UMC_A_CUT) 2121293010Sadrian name = "rtwn-rtl8192cfwU"; 2122293010Sadrian else 2123293010Sadrian name = "rtwn-rtl8192cfwU_B"; 2124293010Sadrian RTWN_UNLOCK(sc); 2125293010Sadrian fw = firmware_get(name); 2126293010Sadrian RTWN_LOCK(sc); 2127293010Sadrian if (fw == NULL) { 2128293010Sadrian device_printf(sc->sc_dev, 2129293010Sadrian "could not read firmware %s\n", name); 2130293010Sadrian return (ENOENT); 2131293010Sadrian } 2132293010Sadrian len = fw->datasize; 2133293010Sadrian if (len < sizeof(*hdr)) { 2134293010Sadrian device_printf(sc->sc_dev, "firmware too short\n"); 2135293010Sadrian error = EINVAL; 2136293010Sadrian goto fail; 2137293010Sadrian } 2138293010Sadrian ptr = fw->data; 2139293010Sadrian hdr = (const struct r92c_fw_hdr *)ptr; 2140293010Sadrian /* Check if there is a valid FW header and skip it. */ 2141293010Sadrian if ((le16toh(hdr->signature) >> 4) == 0x88c || 2142293010Sadrian (le16toh(hdr->signature) >> 4) == 0x92c) { 2143293010Sadrian DPRINTF(("FW V%d.%d %02d-%02d %02d:%02d\n", 2144293010Sadrian le16toh(hdr->version), le16toh(hdr->subversion), 2145293010Sadrian hdr->month, hdr->date, hdr->hour, hdr->minute)); 2146293010Sadrian ptr += sizeof(*hdr); 2147293010Sadrian len -= sizeof(*hdr); 2148293010Sadrian } 2149293010Sadrian 2150293010Sadrian if (rtwn_read_1(sc, R92C_MCUFWDL) & R92C_MCUFWDL_RAM_DL_SEL) 2151293010Sadrian rtwn_fw_reset(sc); 2152293010Sadrian 2153293010Sadrian /* Enable FW download. */ 2154293010Sadrian rtwn_write_2(sc, R92C_SYS_FUNC_EN, 2155293010Sadrian rtwn_read_2(sc, R92C_SYS_FUNC_EN) | 2156293010Sadrian R92C_SYS_FUNC_EN_CPUEN); 2157293010Sadrian rtwn_write_1(sc, R92C_MCUFWDL, 2158293010Sadrian rtwn_read_1(sc, R92C_MCUFWDL) | R92C_MCUFWDL_EN); 2159293010Sadrian rtwn_write_1(sc, R92C_MCUFWDL + 2, 2160293010Sadrian rtwn_read_1(sc, R92C_MCUFWDL + 2) & ~0x08); 2161293010Sadrian 2162293010Sadrian /* Reset the FWDL checksum. */ 2163293010Sadrian rtwn_write_1(sc, R92C_MCUFWDL, 2164293010Sadrian rtwn_read_1(sc, R92C_MCUFWDL) | R92C_MCUFWDL_CHKSUM_RPT); 2165293010Sadrian 2166293010Sadrian for (page = 0; len > 0; page++) { 2167293010Sadrian mlen = MIN(len, R92C_FW_PAGE_SIZE); 2168293010Sadrian rtwn_fw_loadpage(sc, page, ptr, mlen); 2169293010Sadrian ptr += mlen; 2170293010Sadrian len -= mlen; 2171293010Sadrian } 2172293010Sadrian 2173293010Sadrian /* Disable FW download. */ 2174293010Sadrian rtwn_write_1(sc, R92C_MCUFWDL, 2175293010Sadrian rtwn_read_1(sc, R92C_MCUFWDL) & ~R92C_MCUFWDL_EN); 2176293010Sadrian rtwn_write_1(sc, R92C_MCUFWDL + 1, 0); 2177293010Sadrian 2178293010Sadrian /* Wait for checksum report. */ 2179293010Sadrian for (ntries = 0; ntries < 1000; ntries++) { 2180293010Sadrian if (rtwn_read_4(sc, R92C_MCUFWDL) & R92C_MCUFWDL_CHKSUM_RPT) 2181293010Sadrian break; 2182293010Sadrian DELAY(5); 2183293010Sadrian } 2184293010Sadrian if (ntries == 1000) { 2185293010Sadrian device_printf(sc->sc_dev, 2186293010Sadrian "timeout waiting for checksum report\n"); 2187293010Sadrian error = ETIMEDOUT; 2188293010Sadrian goto fail; 2189293010Sadrian } 2190293010Sadrian 2191293010Sadrian reg = rtwn_read_4(sc, R92C_MCUFWDL); 2192293010Sadrian reg = (reg & ~R92C_MCUFWDL_WINTINI_RDY) | R92C_MCUFWDL_RDY; 2193293010Sadrian rtwn_write_4(sc, R92C_MCUFWDL, reg); 2194293010Sadrian /* Wait for firmware readiness. */ 2195293010Sadrian for (ntries = 0; ntries < 2000; ntries++) { 2196293010Sadrian if (rtwn_read_4(sc, R92C_MCUFWDL) & R92C_MCUFWDL_WINTINI_RDY) 2197293010Sadrian break; 2198293010Sadrian DELAY(50); 2199293010Sadrian } 2200293010Sadrian if (ntries == 1000) { 2201293010Sadrian device_printf(sc->sc_dev, 2202293010Sadrian "timeout waiting for firmware readiness\n"); 2203293010Sadrian error = ETIMEDOUT; 2204293010Sadrian goto fail; 2205293010Sadrian } 2206293010Sadrianfail: 2207293010Sadrian firmware_put(fw, FIRMWARE_UNLOAD); 2208293010Sadrian return (error); 2209293010Sadrian} 2210293010Sadrian 2211293010Sadrianstatic int 2212293010Sadrianrtwn_dma_init(struct rtwn_softc *sc) 2213293010Sadrian{ 2214293010Sadrian uint32_t reg; 2215293010Sadrian int error; 2216293010Sadrian 2217293010Sadrian /* Initialize LLT table. */ 2218293010Sadrian error = rtwn_llt_init(sc); 2219293010Sadrian if (error != 0) 2220293010Sadrian return error; 2221293010Sadrian 2222293010Sadrian /* Set number of pages for normal priority queue. */ 2223293010Sadrian rtwn_write_2(sc, R92C_RQPN_NPQ, 0); 2224293010Sadrian rtwn_write_4(sc, R92C_RQPN, 2225293010Sadrian /* Set number of pages for public queue. */ 2226293010Sadrian SM(R92C_RQPN_PUBQ, R92C_PUBQ_NPAGES) | 2227293010Sadrian /* Set number of pages for high priority queue. */ 2228293010Sadrian SM(R92C_RQPN_HPQ, R92C_HPQ_NPAGES) | 2229293010Sadrian /* Set number of pages for low priority queue. */ 2230293010Sadrian SM(R92C_RQPN_LPQ, R92C_LPQ_NPAGES) | 2231293010Sadrian /* Load values. */ 2232293010Sadrian R92C_RQPN_LD); 2233293010Sadrian 2234293010Sadrian rtwn_write_1(sc, R92C_TXPKTBUF_BCNQ_BDNY, R92C_TX_PAGE_BOUNDARY); 2235293010Sadrian rtwn_write_1(sc, R92C_TXPKTBUF_MGQ_BDNY, R92C_TX_PAGE_BOUNDARY); 2236293010Sadrian rtwn_write_1(sc, R92C_TXPKTBUF_WMAC_LBK_BF_HD, R92C_TX_PAGE_BOUNDARY); 2237293010Sadrian rtwn_write_1(sc, R92C_TRXFF_BNDY, R92C_TX_PAGE_BOUNDARY); 2238293010Sadrian rtwn_write_1(sc, R92C_TDECTRL + 1, R92C_TX_PAGE_BOUNDARY); 2239293010Sadrian 2240293010Sadrian reg = rtwn_read_2(sc, R92C_TRXDMA_CTRL); 2241293010Sadrian reg &= ~R92C_TRXDMA_CTRL_QMAP_M; 2242293010Sadrian reg |= 0xF771; 2243293010Sadrian rtwn_write_2(sc, R92C_TRXDMA_CTRL, reg); 2244293010Sadrian 2245293010Sadrian rtwn_write_4(sc, R92C_TCR, R92C_TCR_CFENDFORM | (1 << 12) | (1 << 13)); 2246293010Sadrian 2247293010Sadrian /* Configure Tx DMA. */ 2248293010Sadrian rtwn_write_4(sc, R92C_BKQ_DESA, sc->tx_ring[RTWN_BK_QUEUE].paddr); 2249293010Sadrian rtwn_write_4(sc, R92C_BEQ_DESA, sc->tx_ring[RTWN_BE_QUEUE].paddr); 2250293010Sadrian rtwn_write_4(sc, R92C_VIQ_DESA, sc->tx_ring[RTWN_VI_QUEUE].paddr); 2251293010Sadrian rtwn_write_4(sc, R92C_VOQ_DESA, sc->tx_ring[RTWN_VO_QUEUE].paddr); 2252293010Sadrian rtwn_write_4(sc, R92C_BCNQ_DESA, sc->tx_ring[RTWN_BEACON_QUEUE].paddr); 2253293010Sadrian rtwn_write_4(sc, R92C_MGQ_DESA, sc->tx_ring[RTWN_MGNT_QUEUE].paddr); 2254293010Sadrian rtwn_write_4(sc, R92C_HQ_DESA, sc->tx_ring[RTWN_HIGH_QUEUE].paddr); 2255293010Sadrian 2256293010Sadrian /* Configure Rx DMA. */ 2257293010Sadrian rtwn_write_4(sc, R92C_RX_DESA, sc->rx_ring.paddr); 2258293010Sadrian 2259293010Sadrian /* Set Tx/Rx transfer page boundary. */ 2260293010Sadrian rtwn_write_2(sc, R92C_TRXFF_BNDY + 2, 0x27ff); 2261293010Sadrian 2262293010Sadrian /* Set Tx/Rx transfer page size. */ 2263293010Sadrian rtwn_write_1(sc, R92C_PBP, 2264293010Sadrian SM(R92C_PBP_PSRX, R92C_PBP_128) | 2265293010Sadrian SM(R92C_PBP_PSTX, R92C_PBP_128)); 2266293010Sadrian return (0); 2267293010Sadrian} 2268293010Sadrian 2269293010Sadrianstatic void 2270293010Sadrianrtwn_mac_init(struct rtwn_softc *sc) 2271293010Sadrian{ 2272293010Sadrian int i; 2273293010Sadrian 2274293010Sadrian /* Write MAC initialization values. */ 2275293010Sadrian for (i = 0; i < nitems(rtl8192ce_mac); i++) 2276293010Sadrian rtwn_write_1(sc, rtl8192ce_mac[i].reg, rtl8192ce_mac[i].val); 2277293010Sadrian} 2278293010Sadrian 2279293010Sadrianstatic void 2280293010Sadrianrtwn_bb_init(struct rtwn_softc *sc) 2281293010Sadrian{ 2282293010Sadrian const struct rtwn_bb_prog *prog; 2283293010Sadrian uint32_t reg; 2284293010Sadrian int i; 2285293010Sadrian 2286293010Sadrian /* Enable BB and RF. */ 2287293010Sadrian rtwn_write_2(sc, R92C_SYS_FUNC_EN, 2288293010Sadrian rtwn_read_2(sc, R92C_SYS_FUNC_EN) | 2289293010Sadrian R92C_SYS_FUNC_EN_BBRSTB | R92C_SYS_FUNC_EN_BB_GLB_RST | 2290293010Sadrian R92C_SYS_FUNC_EN_DIO_RF); 2291293010Sadrian 2292293010Sadrian rtwn_write_2(sc, R92C_AFE_PLL_CTRL, 0xdb83); 2293293010Sadrian 2294293010Sadrian rtwn_write_1(sc, R92C_RF_CTRL, 2295293010Sadrian R92C_RF_CTRL_EN | R92C_RF_CTRL_RSTB | R92C_RF_CTRL_SDMRSTB); 2296293010Sadrian 2297293010Sadrian rtwn_write_1(sc, R92C_SYS_FUNC_EN, 2298293010Sadrian R92C_SYS_FUNC_EN_DIO_PCIE | R92C_SYS_FUNC_EN_PCIEA | 2299293010Sadrian R92C_SYS_FUNC_EN_PPLL | R92C_SYS_FUNC_EN_BB_GLB_RST | 2300293010Sadrian R92C_SYS_FUNC_EN_BBRSTB); 2301293010Sadrian 2302293010Sadrian rtwn_write_1(sc, R92C_AFE_XTAL_CTRL + 1, 0x80); 2303293010Sadrian 2304293010Sadrian rtwn_write_4(sc, R92C_LEDCFG0, 2305293010Sadrian rtwn_read_4(sc, R92C_LEDCFG0) | 0x00800000); 2306293010Sadrian 2307293010Sadrian /* Select BB programming. */ 2308293010Sadrian prog = (sc->chip & RTWN_CHIP_92C) ? 2309293010Sadrian &rtl8192ce_bb_prog_2t : &rtl8192ce_bb_prog_1t; 2310293010Sadrian 2311293010Sadrian /* Write BB initialization values. */ 2312293010Sadrian for (i = 0; i < prog->count; i++) { 2313293010Sadrian rtwn_bb_write(sc, prog->regs[i], prog->vals[i]); 2314293010Sadrian DELAY(1); 2315293010Sadrian } 2316293010Sadrian 2317293010Sadrian if (sc->chip & RTWN_CHIP_92C_1T2R) { 2318293010Sadrian /* 8192C 1T only configuration. */ 2319293010Sadrian reg = rtwn_bb_read(sc, R92C_FPGA0_TXINFO); 2320293010Sadrian reg = (reg & ~0x00000003) | 0x2; 2321293010Sadrian rtwn_bb_write(sc, R92C_FPGA0_TXINFO, reg); 2322293010Sadrian 2323293010Sadrian reg = rtwn_bb_read(sc, R92C_FPGA1_TXINFO); 2324293010Sadrian reg = (reg & ~0x00300033) | 0x00200022; 2325293010Sadrian rtwn_bb_write(sc, R92C_FPGA1_TXINFO, reg); 2326293010Sadrian 2327293010Sadrian reg = rtwn_bb_read(sc, R92C_CCK0_AFESETTING); 2328293010Sadrian reg = (reg & ~0xff000000) | 0x45 << 24; 2329293010Sadrian rtwn_bb_write(sc, R92C_CCK0_AFESETTING, reg); 2330293010Sadrian 2331293010Sadrian reg = rtwn_bb_read(sc, R92C_OFDM0_TRXPATHENA); 2332293010Sadrian reg = (reg & ~0x000000ff) | 0x23; 2333293010Sadrian rtwn_bb_write(sc, R92C_OFDM0_TRXPATHENA, reg); 2334293010Sadrian 2335293010Sadrian reg = rtwn_bb_read(sc, R92C_OFDM0_AGCPARAM1); 2336293010Sadrian reg = (reg & ~0x00000030) | 1 << 4; 2337293010Sadrian rtwn_bb_write(sc, R92C_OFDM0_AGCPARAM1, reg); 2338293010Sadrian 2339293010Sadrian reg = rtwn_bb_read(sc, 0xe74); 2340293010Sadrian reg = (reg & ~0x0c000000) | 2 << 26; 2341293010Sadrian rtwn_bb_write(sc, 0xe74, reg); 2342293010Sadrian reg = rtwn_bb_read(sc, 0xe78); 2343293010Sadrian reg = (reg & ~0x0c000000) | 2 << 26; 2344293010Sadrian rtwn_bb_write(sc, 0xe78, reg); 2345293010Sadrian reg = rtwn_bb_read(sc, 0xe7c); 2346293010Sadrian reg = (reg & ~0x0c000000) | 2 << 26; 2347293010Sadrian rtwn_bb_write(sc, 0xe7c, reg); 2348293010Sadrian reg = rtwn_bb_read(sc, 0xe80); 2349293010Sadrian reg = (reg & ~0x0c000000) | 2 << 26; 2350293010Sadrian rtwn_bb_write(sc, 0xe80, reg); 2351293010Sadrian reg = rtwn_bb_read(sc, 0xe88); 2352293010Sadrian reg = (reg & ~0x0c000000) | 2 << 26; 2353293010Sadrian rtwn_bb_write(sc, 0xe88, reg); 2354293010Sadrian } 2355293010Sadrian 2356293010Sadrian /* Write AGC values. */ 2357293010Sadrian for (i = 0; i < prog->agccount; i++) { 2358293010Sadrian rtwn_bb_write(sc, R92C_OFDM0_AGCRSSITABLE, 2359293010Sadrian prog->agcvals[i]); 2360293010Sadrian DELAY(1); 2361293010Sadrian } 2362293010Sadrian 2363293010Sadrian if (rtwn_bb_read(sc, R92C_HSSI_PARAM2(0)) & 2364293010Sadrian R92C_HSSI_PARAM2_CCK_HIPWR) 2365293010Sadrian sc->sc_flags |= RTWN_FLAG_CCK_HIPWR; 2366293010Sadrian} 2367293010Sadrian 2368293010Sadrianstatic void 2369293010Sadrianrtwn_rf_init(struct rtwn_softc *sc) 2370293010Sadrian{ 2371293010Sadrian const struct rtwn_rf_prog *prog; 2372293010Sadrian uint32_t reg, type; 2373293010Sadrian int i, j, idx, off; 2374293010Sadrian 2375293010Sadrian /* Select RF programming based on board type. */ 2376293010Sadrian if (!(sc->chip & RTWN_CHIP_92C)) { 2377293010Sadrian if (sc->board_type == R92C_BOARD_TYPE_MINICARD) 2378293010Sadrian prog = rtl8188ce_rf_prog; 2379293010Sadrian else if (sc->board_type == R92C_BOARD_TYPE_HIGHPA) 2380293010Sadrian prog = rtl8188ru_rf_prog; 2381293010Sadrian else 2382293010Sadrian prog = rtl8188cu_rf_prog; 2383293010Sadrian } else 2384293010Sadrian prog = rtl8192ce_rf_prog; 2385293010Sadrian 2386293010Sadrian for (i = 0; i < sc->nrxchains; i++) { 2387293010Sadrian /* Save RF_ENV control type. */ 2388293010Sadrian idx = i / 2; 2389293010Sadrian off = (i % 2) * 16; 2390293010Sadrian reg = rtwn_bb_read(sc, R92C_FPGA0_RFIFACESW(idx)); 2391293010Sadrian type = (reg >> off) & 0x10; 2392293010Sadrian 2393293010Sadrian /* Set RF_ENV enable. */ 2394293010Sadrian reg = rtwn_bb_read(sc, R92C_FPGA0_RFIFACEOE(i)); 2395293010Sadrian reg |= 0x100000; 2396293010Sadrian rtwn_bb_write(sc, R92C_FPGA0_RFIFACEOE(i), reg); 2397293010Sadrian DELAY(1); 2398293010Sadrian /* Set RF_ENV output high. */ 2399293010Sadrian reg = rtwn_bb_read(sc, R92C_FPGA0_RFIFACEOE(i)); 2400293010Sadrian reg |= 0x10; 2401293010Sadrian rtwn_bb_write(sc, R92C_FPGA0_RFIFACEOE(i), reg); 2402293010Sadrian DELAY(1); 2403293010Sadrian /* Set address and data lengths of RF registers. */ 2404293010Sadrian reg = rtwn_bb_read(sc, R92C_HSSI_PARAM2(i)); 2405293010Sadrian reg &= ~R92C_HSSI_PARAM2_ADDR_LENGTH; 2406293010Sadrian rtwn_bb_write(sc, R92C_HSSI_PARAM2(i), reg); 2407293010Sadrian DELAY(1); 2408293010Sadrian reg = rtwn_bb_read(sc, R92C_HSSI_PARAM2(i)); 2409293010Sadrian reg &= ~R92C_HSSI_PARAM2_DATA_LENGTH; 2410293010Sadrian rtwn_bb_write(sc, R92C_HSSI_PARAM2(i), reg); 2411293010Sadrian DELAY(1); 2412293010Sadrian 2413293010Sadrian /* Write RF initialization values for this chain. */ 2414293010Sadrian for (j = 0; j < prog[i].count; j++) { 2415293010Sadrian if (prog[i].regs[j] >= 0xf9 && 2416293010Sadrian prog[i].regs[j] <= 0xfe) { 2417293010Sadrian /* 2418293010Sadrian * These are fake RF registers offsets that 2419293010Sadrian * indicate a delay is required. 2420293010Sadrian */ 2421293010Sadrian DELAY(50); 2422293010Sadrian continue; 2423293010Sadrian } 2424293010Sadrian rtwn_rf_write(sc, i, prog[i].regs[j], 2425293010Sadrian prog[i].vals[j]); 2426293010Sadrian DELAY(1); 2427293010Sadrian } 2428293010Sadrian 2429293010Sadrian /* Restore RF_ENV control type. */ 2430293010Sadrian reg = rtwn_bb_read(sc, R92C_FPGA0_RFIFACESW(idx)); 2431293010Sadrian reg &= ~(0x10 << off) | (type << off); 2432293010Sadrian rtwn_bb_write(sc, R92C_FPGA0_RFIFACESW(idx), reg); 2433293010Sadrian 2434293010Sadrian /* Cache RF register CHNLBW. */ 2435293010Sadrian sc->rf_chnlbw[i] = rtwn_rf_read(sc, i, R92C_RF_CHNLBW); 2436293010Sadrian } 2437293010Sadrian 2438293010Sadrian if ((sc->chip & (RTWN_CHIP_UMC_A_CUT | RTWN_CHIP_92C)) == 2439293010Sadrian RTWN_CHIP_UMC_A_CUT) { 2440293010Sadrian rtwn_rf_write(sc, 0, R92C_RF_RX_G1, 0x30255); 2441293010Sadrian rtwn_rf_write(sc, 0, R92C_RF_RX_G2, 0x50a00); 2442293010Sadrian } 2443293010Sadrian} 2444293010Sadrian 2445293010Sadrianstatic void 2446293010Sadrianrtwn_cam_init(struct rtwn_softc *sc) 2447293010Sadrian{ 2448293010Sadrian /* Invalidate all CAM entries. */ 2449293010Sadrian rtwn_write_4(sc, R92C_CAMCMD, 2450293010Sadrian R92C_CAMCMD_POLLING | R92C_CAMCMD_CLR); 2451293010Sadrian} 2452293010Sadrian 2453293010Sadrianstatic void 2454293010Sadrianrtwn_pa_bias_init(struct rtwn_softc *sc) 2455293010Sadrian{ 2456293010Sadrian uint8_t reg; 2457293010Sadrian int i; 2458293010Sadrian 2459293010Sadrian for (i = 0; i < sc->nrxchains; i++) { 2460293010Sadrian if (sc->pa_setting & (1 << i)) 2461293010Sadrian continue; 2462293010Sadrian rtwn_rf_write(sc, i, R92C_RF_IPA, 0x0f406); 2463293010Sadrian rtwn_rf_write(sc, i, R92C_RF_IPA, 0x4f406); 2464293010Sadrian rtwn_rf_write(sc, i, R92C_RF_IPA, 0x8f406); 2465293010Sadrian rtwn_rf_write(sc, i, R92C_RF_IPA, 0xcf406); 2466293010Sadrian } 2467293010Sadrian if (!(sc->pa_setting & 0x10)) { 2468293010Sadrian reg = rtwn_read_1(sc, 0x16); 2469293010Sadrian reg = (reg & ~0xf0) | 0x90; 2470293010Sadrian rtwn_write_1(sc, 0x16, reg); 2471293010Sadrian } 2472293010Sadrian} 2473293010Sadrian 2474293010Sadrianstatic void 2475293010Sadrianrtwn_rxfilter_init(struct rtwn_softc *sc) 2476293010Sadrian{ 2477293010Sadrian /* Initialize Rx filter. */ 2478293010Sadrian /* TODO: use better filter for monitor mode. */ 2479293010Sadrian rtwn_write_4(sc, R92C_RCR, 2480293010Sadrian R92C_RCR_AAP | R92C_RCR_APM | R92C_RCR_AM | R92C_RCR_AB | 2481293010Sadrian R92C_RCR_APP_ICV | R92C_RCR_AMF | R92C_RCR_HTC_LOC_CTRL | 2482293010Sadrian R92C_RCR_APP_MIC | R92C_RCR_APP_PHYSTS); 2483293010Sadrian /* Accept all multicast frames. */ 2484293010Sadrian rtwn_write_4(sc, R92C_MAR + 0, 0xffffffff); 2485293010Sadrian rtwn_write_4(sc, R92C_MAR + 4, 0xffffffff); 2486293010Sadrian /* Accept all management frames. */ 2487293010Sadrian rtwn_write_2(sc, R92C_RXFLTMAP0, 0xffff); 2488293010Sadrian /* Reject all control frames. */ 2489293010Sadrian rtwn_write_2(sc, R92C_RXFLTMAP1, 0x0000); 2490293010Sadrian /* Accept all data frames. */ 2491293010Sadrian rtwn_write_2(sc, R92C_RXFLTMAP2, 0xffff); 2492293010Sadrian} 2493293010Sadrian 2494293010Sadrianstatic void 2495293010Sadrianrtwn_edca_init(struct rtwn_softc *sc) 2496293010Sadrian{ 2497293010Sadrian 2498293010Sadrian rtwn_write_2(sc, R92C_SPEC_SIFS, 0x1010); 2499293010Sadrian rtwn_write_2(sc, R92C_MAC_SPEC_SIFS, 0x1010); 2500293010Sadrian rtwn_write_2(sc, R92C_SIFS_CCK, 0x1010); 2501293010Sadrian rtwn_write_2(sc, R92C_SIFS_OFDM, 0x0e0e); 2502293010Sadrian rtwn_write_4(sc, R92C_EDCA_BE_PARAM, 0x005ea42b); 2503293010Sadrian rtwn_write_4(sc, R92C_EDCA_BK_PARAM, 0x0000a44f); 2504293010Sadrian rtwn_write_4(sc, R92C_EDCA_VI_PARAM, 0x005e4322); 2505293010Sadrian rtwn_write_4(sc, R92C_EDCA_VO_PARAM, 0x002f3222); 2506293010Sadrian} 2507293010Sadrian 2508293010Sadrianstatic void 2509293010Sadrianrtwn_write_txpower(struct rtwn_softc *sc, int chain, 2510293010Sadrian uint16_t power[RTWN_RIDX_COUNT]) 2511293010Sadrian{ 2512293010Sadrian uint32_t reg; 2513293010Sadrian 2514293010Sadrian /* Write per-CCK rate Tx power. */ 2515293010Sadrian if (chain == 0) { 2516293010Sadrian reg = rtwn_bb_read(sc, R92C_TXAGC_A_CCK1_MCS32); 2517293010Sadrian reg = RW(reg, R92C_TXAGC_A_CCK1, power[0]); 2518293010Sadrian rtwn_bb_write(sc, R92C_TXAGC_A_CCK1_MCS32, reg); 2519293010Sadrian reg = rtwn_bb_read(sc, R92C_TXAGC_B_CCK11_A_CCK2_11); 2520293010Sadrian reg = RW(reg, R92C_TXAGC_A_CCK2, power[1]); 2521293010Sadrian reg = RW(reg, R92C_TXAGC_A_CCK55, power[2]); 2522293010Sadrian reg = RW(reg, R92C_TXAGC_A_CCK11, power[3]); 2523293010Sadrian rtwn_bb_write(sc, R92C_TXAGC_B_CCK11_A_CCK2_11, reg); 2524293010Sadrian } else { 2525293010Sadrian reg = rtwn_bb_read(sc, R92C_TXAGC_B_CCK1_55_MCS32); 2526293010Sadrian reg = RW(reg, R92C_TXAGC_B_CCK1, power[0]); 2527293010Sadrian reg = RW(reg, R92C_TXAGC_B_CCK2, power[1]); 2528293010Sadrian reg = RW(reg, R92C_TXAGC_B_CCK55, power[2]); 2529293010Sadrian rtwn_bb_write(sc, R92C_TXAGC_B_CCK1_55_MCS32, reg); 2530293010Sadrian reg = rtwn_bb_read(sc, R92C_TXAGC_B_CCK11_A_CCK2_11); 2531293010Sadrian reg = RW(reg, R92C_TXAGC_B_CCK11, power[3]); 2532293010Sadrian rtwn_bb_write(sc, R92C_TXAGC_B_CCK11_A_CCK2_11, reg); 2533293010Sadrian } 2534293010Sadrian /* Write per-OFDM rate Tx power. */ 2535293010Sadrian rtwn_bb_write(sc, R92C_TXAGC_RATE18_06(chain), 2536293010Sadrian SM(R92C_TXAGC_RATE06, power[ 4]) | 2537293010Sadrian SM(R92C_TXAGC_RATE09, power[ 5]) | 2538293010Sadrian SM(R92C_TXAGC_RATE12, power[ 6]) | 2539293010Sadrian SM(R92C_TXAGC_RATE18, power[ 7])); 2540293010Sadrian rtwn_bb_write(sc, R92C_TXAGC_RATE54_24(chain), 2541293010Sadrian SM(R92C_TXAGC_RATE24, power[ 8]) | 2542293010Sadrian SM(R92C_TXAGC_RATE36, power[ 9]) | 2543293010Sadrian SM(R92C_TXAGC_RATE48, power[10]) | 2544293010Sadrian SM(R92C_TXAGC_RATE54, power[11])); 2545293010Sadrian /* Write per-MCS Tx power. */ 2546293010Sadrian rtwn_bb_write(sc, R92C_TXAGC_MCS03_MCS00(chain), 2547293010Sadrian SM(R92C_TXAGC_MCS00, power[12]) | 2548293010Sadrian SM(R92C_TXAGC_MCS01, power[13]) | 2549293010Sadrian SM(R92C_TXAGC_MCS02, power[14]) | 2550293010Sadrian SM(R92C_TXAGC_MCS03, power[15])); 2551293010Sadrian rtwn_bb_write(sc, R92C_TXAGC_MCS07_MCS04(chain), 2552293010Sadrian SM(R92C_TXAGC_MCS04, power[16]) | 2553293010Sadrian SM(R92C_TXAGC_MCS05, power[17]) | 2554293010Sadrian SM(R92C_TXAGC_MCS06, power[18]) | 2555293010Sadrian SM(R92C_TXAGC_MCS07, power[19])); 2556293010Sadrian rtwn_bb_write(sc, R92C_TXAGC_MCS11_MCS08(chain), 2557293010Sadrian SM(R92C_TXAGC_MCS08, power[20]) | 2558293010Sadrian SM(R92C_TXAGC_MCS09, power[21]) | 2559293010Sadrian SM(R92C_TXAGC_MCS10, power[22]) | 2560293010Sadrian SM(R92C_TXAGC_MCS11, power[23])); 2561293010Sadrian rtwn_bb_write(sc, R92C_TXAGC_MCS15_MCS12(chain), 2562293010Sadrian SM(R92C_TXAGC_MCS12, power[24]) | 2563293010Sadrian SM(R92C_TXAGC_MCS13, power[25]) | 2564293010Sadrian SM(R92C_TXAGC_MCS14, power[26]) | 2565293010Sadrian SM(R92C_TXAGC_MCS15, power[27])); 2566293010Sadrian} 2567293010Sadrian 2568293010Sadrianstatic void 2569293010Sadrianrtwn_get_txpower(struct rtwn_softc *sc, int chain, 2570293010Sadrian struct ieee80211_channel *c, struct ieee80211_channel *extc, 2571293010Sadrian uint16_t power[RTWN_RIDX_COUNT]) 2572293010Sadrian{ 2573293010Sadrian struct ieee80211com *ic = &sc->sc_ic; 2574293010Sadrian struct r92c_rom *rom = &sc->rom; 2575293010Sadrian uint16_t cckpow, ofdmpow, htpow, diff, max; 2576293010Sadrian const struct rtwn_txpwr *base; 2577293010Sadrian int ridx, chan, group; 2578293010Sadrian 2579293010Sadrian /* Determine channel group. */ 2580293010Sadrian chan = ieee80211_chan2ieee(ic, c); /* XXX center freq! */ 2581293010Sadrian if (chan <= 3) 2582293010Sadrian group = 0; 2583293010Sadrian else if (chan <= 9) 2584293010Sadrian group = 1; 2585293010Sadrian else 2586293010Sadrian group = 2; 2587293010Sadrian 2588293010Sadrian /* Get original Tx power based on board type and RF chain. */ 2589293010Sadrian if (!(sc->chip & RTWN_CHIP_92C)) { 2590293010Sadrian if (sc->board_type == R92C_BOARD_TYPE_HIGHPA) 2591293010Sadrian base = &rtl8188ru_txagc[chain]; 2592293010Sadrian else 2593293010Sadrian base = &rtl8192cu_txagc[chain]; 2594293010Sadrian } else 2595293010Sadrian base = &rtl8192cu_txagc[chain]; 2596293010Sadrian 2597293010Sadrian memset(power, 0, RTWN_RIDX_COUNT * sizeof(power[0])); 2598293010Sadrian if (sc->regulatory == 0) { 2599300744Savos for (ridx = RTWN_RIDX_CCK1; ridx <= RTWN_RIDX_CCK11; ridx++) 2600293010Sadrian power[ridx] = base->pwr[0][ridx]; 2601293010Sadrian } 2602300744Savos for (ridx = RTWN_RIDX_OFDM6; ridx < RTWN_RIDX_COUNT; ridx++) { 2603293010Sadrian if (sc->regulatory == 3) { 2604293010Sadrian power[ridx] = base->pwr[0][ridx]; 2605293010Sadrian /* Apply vendor limits. */ 2606293010Sadrian if (extc != NULL) 2607293010Sadrian max = rom->ht40_max_pwr[group]; 2608293010Sadrian else 2609293010Sadrian max = rom->ht20_max_pwr[group]; 2610293010Sadrian max = (max >> (chain * 4)) & 0xf; 2611293010Sadrian if (power[ridx] > max) 2612293010Sadrian power[ridx] = max; 2613293010Sadrian } else if (sc->regulatory == 1) { 2614293010Sadrian if (extc == NULL) 2615293010Sadrian power[ridx] = base->pwr[group][ridx]; 2616293010Sadrian } else if (sc->regulatory != 2) 2617293010Sadrian power[ridx] = base->pwr[0][ridx]; 2618293010Sadrian } 2619293010Sadrian 2620293010Sadrian /* Compute per-CCK rate Tx power. */ 2621293010Sadrian cckpow = rom->cck_tx_pwr[chain][group]; 2622300744Savos for (ridx = RTWN_RIDX_CCK1; ridx <= RTWN_RIDX_CCK11; ridx++) { 2623293010Sadrian power[ridx] += cckpow; 2624293010Sadrian if (power[ridx] > R92C_MAX_TX_PWR) 2625293010Sadrian power[ridx] = R92C_MAX_TX_PWR; 2626293010Sadrian } 2627293010Sadrian 2628293010Sadrian htpow = rom->ht40_1s_tx_pwr[chain][group]; 2629293010Sadrian if (sc->ntxchains > 1) { 2630293010Sadrian /* Apply reduction for 2 spatial streams. */ 2631293010Sadrian diff = rom->ht40_2s_tx_pwr_diff[group]; 2632293010Sadrian diff = (diff >> (chain * 4)) & 0xf; 2633293010Sadrian htpow = (htpow > diff) ? htpow - diff : 0; 2634293010Sadrian } 2635293010Sadrian 2636293010Sadrian /* Compute per-OFDM rate Tx power. */ 2637293010Sadrian diff = rom->ofdm_tx_pwr_diff[group]; 2638293010Sadrian diff = (diff >> (chain * 4)) & 0xf; 2639293010Sadrian ofdmpow = htpow + diff; /* HT->OFDM correction. */ 2640300744Savos for (ridx = RTWN_RIDX_OFDM6; ridx <= RTWN_RIDX_OFDM54; ridx++) { 2641293010Sadrian power[ridx] += ofdmpow; 2642293010Sadrian if (power[ridx] > R92C_MAX_TX_PWR) 2643293010Sadrian power[ridx] = R92C_MAX_TX_PWR; 2644293010Sadrian } 2645293010Sadrian 2646293010Sadrian /* Compute per-MCS Tx power. */ 2647293010Sadrian if (extc == NULL) { 2648293010Sadrian diff = rom->ht20_tx_pwr_diff[group]; 2649293010Sadrian diff = (diff >> (chain * 4)) & 0xf; 2650293010Sadrian htpow += diff; /* HT40->HT20 correction. */ 2651293010Sadrian } 2652300744Savos for (ridx = RTWN_RIDX_MCS0; ridx <= RTWN_RIDX_MCS15; ridx++) { 2653293010Sadrian power[ridx] += htpow; 2654293010Sadrian if (power[ridx] > R92C_MAX_TX_PWR) 2655293010Sadrian power[ridx] = R92C_MAX_TX_PWR; 2656293010Sadrian } 2657293010Sadrian#ifdef RTWN_DEBUG 2658293010Sadrian if (sc->sc_debug >= 4) { 2659293010Sadrian /* Dump per-rate Tx power values. */ 2660293010Sadrian printf("Tx power for chain %d:\n", chain); 2661300744Savos for (ridx = RTWN_RIDX_CCK1; ridx < RTWN_RIDX_COUNT; ridx++) 2662293010Sadrian printf("Rate %d = %u\n", ridx, power[ridx]); 2663293010Sadrian } 2664293010Sadrian#endif 2665293010Sadrian} 2666293010Sadrian 2667293010Sadrianstatic void 2668293010Sadrianrtwn_set_txpower(struct rtwn_softc *sc, struct ieee80211_channel *c, 2669293010Sadrian struct ieee80211_channel *extc) 2670293010Sadrian{ 2671293010Sadrian uint16_t power[RTWN_RIDX_COUNT]; 2672293010Sadrian int i; 2673293010Sadrian 2674293010Sadrian for (i = 0; i < sc->ntxchains; i++) { 2675293010Sadrian /* Compute per-rate Tx power values. */ 2676293010Sadrian rtwn_get_txpower(sc, i, c, extc, power); 2677293010Sadrian /* Write per-rate Tx power values to hardware. */ 2678293010Sadrian rtwn_write_txpower(sc, i, power); 2679293010Sadrian } 2680293010Sadrian} 2681293010Sadrian 2682293010Sadrianstatic void 2683295865Savosrtwn_set_rx_bssid_all(struct rtwn_softc *sc, int enable) 2684295865Savos{ 2685295865Savos uint32_t reg; 2686295865Savos 2687295865Savos reg = rtwn_read_4(sc, R92C_RCR); 2688295865Savos if (enable) 2689295865Savos reg &= ~R92C_RCR_CBSSID_BCN; 2690295865Savos else 2691295865Savos reg |= R92C_RCR_CBSSID_BCN; 2692295865Savos rtwn_write_4(sc, R92C_RCR, reg); 2693295865Savos} 2694295865Savos 2695295865Savosstatic void 2696295865Savosrtwn_set_gain(struct rtwn_softc *sc, uint8_t gain) 2697295865Savos{ 2698295865Savos uint32_t reg; 2699295865Savos 2700295865Savos reg = rtwn_bb_read(sc, R92C_OFDM0_AGCCORE1(0)); 2701295865Savos reg = RW(reg, R92C_OFDM0_AGCCORE1_GAIN, gain); 2702295865Savos rtwn_bb_write(sc, R92C_OFDM0_AGCCORE1(0), reg); 2703295865Savos 2704295865Savos reg = rtwn_bb_read(sc, R92C_OFDM0_AGCCORE1(1)); 2705295865Savos reg = RW(reg, R92C_OFDM0_AGCCORE1_GAIN, gain); 2706295865Savos rtwn_bb_write(sc, R92C_OFDM0_AGCCORE1(1), reg); 2707295865Savos} 2708295865Savos 2709295865Savosstatic void 2710293010Sadrianrtwn_scan_start(struct ieee80211com *ic) 2711293010Sadrian{ 2712295865Savos struct rtwn_softc *sc = ic->ic_softc; 2713293010Sadrian 2714295865Savos RTWN_LOCK(sc); 2715295865Savos /* Receive beacons / probe responses from any BSSID. */ 2716295865Savos rtwn_set_rx_bssid_all(sc, 1); 2717295865Savos /* Set gain for scanning. */ 2718295865Savos rtwn_set_gain(sc, 0x20); 2719295865Savos RTWN_UNLOCK(sc); 2720293010Sadrian} 2721293010Sadrian 2722293010Sadrianstatic void 2723293010Sadrianrtwn_scan_end(struct ieee80211com *ic) 2724293010Sadrian{ 2725295865Savos struct rtwn_softc *sc = ic->ic_softc; 2726293010Sadrian 2727295865Savos RTWN_LOCK(sc); 2728295865Savos /* Restore limitations. */ 2729295865Savos rtwn_set_rx_bssid_all(sc, 0); 2730295865Savos /* Set gain under link. */ 2731295865Savos rtwn_set_gain(sc, 0x32); 2732295865Savos RTWN_UNLOCK(sc); 2733293010Sadrian} 2734293010Sadrian 2735293010Sadrianstatic void 2736300754Savosrtwn_getradiocaps(struct ieee80211com *ic, 2737300754Savos int maxchans, int *nchans, struct ieee80211_channel chans[]) 2738300754Savos{ 2739300754Savos uint8_t bands[IEEE80211_MODE_BYTES]; 2740300754Savos 2741300754Savos memset(bands, 0, sizeof(bands)); 2742300754Savos setbit(bands, IEEE80211_MODE_11B); 2743300754Savos setbit(bands, IEEE80211_MODE_11G); 2744343976Savos ieee80211_add_channels_default_2ghz(chans, maxchans, nchans, bands, 0); 2745300754Savos} 2746300754Savos 2747300754Savosstatic void 2748293010Sadrianrtwn_set_channel(struct ieee80211com *ic) 2749293010Sadrian{ 2750293010Sadrian struct rtwn_softc *sc = ic->ic_softc; 2751293010Sadrian struct ieee80211vap *vap = TAILQ_FIRST(&ic->ic_vaps); 2752293010Sadrian 2753293010Sadrian RTWN_LOCK(sc); 2754293010Sadrian if (vap->iv_state == IEEE80211_S_SCAN) { 2755293010Sadrian /* Make link LED blink during scan. */ 2756293010Sadrian rtwn_set_led(sc, RTWN_LED_LINK, !sc->ledlink); 2757293010Sadrian } 2758293010Sadrian rtwn_set_chan(sc, ic->ic_curchan, NULL); 2759293010Sadrian RTWN_UNLOCK(sc); 2760293010Sadrian} 2761293010Sadrian 2762293010Sadrianstatic void 2763293010Sadrianrtwn_update_mcast(struct ieee80211com *ic) 2764293010Sadrian{ 2765293010Sadrian 2766293010Sadrian /* XXX do nothing? */ 2767293010Sadrian} 2768293010Sadrian 2769293010Sadrianstatic void 2770293010Sadrianrtwn_set_chan(struct rtwn_softc *sc, struct ieee80211_channel *c, 2771293010Sadrian struct ieee80211_channel *extc) 2772293010Sadrian{ 2773293010Sadrian struct ieee80211com *ic = &sc->sc_ic; 2774293010Sadrian u_int chan; 2775293010Sadrian int i; 2776293010Sadrian 2777293010Sadrian chan = ieee80211_chan2ieee(ic, c); /* XXX center freq! */ 2778293010Sadrian if (chan == 0 || chan == IEEE80211_CHAN_ANY) { 2779293010Sadrian device_printf(sc->sc_dev, 2780293010Sadrian "%s: invalid channel %x\n", __func__, chan); 2781293010Sadrian return; 2782293010Sadrian } 2783293010Sadrian 2784293010Sadrian /* Set Tx power for this new channel. */ 2785293010Sadrian rtwn_set_txpower(sc, c, extc); 2786293010Sadrian 2787293010Sadrian for (i = 0; i < sc->nrxchains; i++) { 2788293010Sadrian rtwn_rf_write(sc, i, R92C_RF_CHNLBW, 2789293010Sadrian RW(sc->rf_chnlbw[i], R92C_RF_CHNLBW_CHNL, chan)); 2790293010Sadrian } 2791293010Sadrian#ifndef IEEE80211_NO_HT 2792293010Sadrian if (extc != NULL) { 2793293010Sadrian uint32_t reg; 2794293010Sadrian 2795293010Sadrian /* Is secondary channel below or above primary? */ 2796293010Sadrian int prichlo = c->ic_freq < extc->ic_freq; 2797293010Sadrian 2798293010Sadrian rtwn_write_1(sc, R92C_BWOPMODE, 2799293010Sadrian rtwn_read_1(sc, R92C_BWOPMODE) & ~R92C_BWOPMODE_20MHZ); 2800293010Sadrian 2801293010Sadrian reg = rtwn_read_1(sc, R92C_RRSR + 2); 2802293010Sadrian reg = (reg & ~0x6f) | (prichlo ? 1 : 2) << 5; 2803293010Sadrian rtwn_write_1(sc, R92C_RRSR + 2, reg); 2804293010Sadrian 2805293010Sadrian rtwn_bb_write(sc, R92C_FPGA0_RFMOD, 2806293010Sadrian rtwn_bb_read(sc, R92C_FPGA0_RFMOD) | R92C_RFMOD_40MHZ); 2807293010Sadrian rtwn_bb_write(sc, R92C_FPGA1_RFMOD, 2808293010Sadrian rtwn_bb_read(sc, R92C_FPGA1_RFMOD) | R92C_RFMOD_40MHZ); 2809293010Sadrian 2810293010Sadrian /* Set CCK side band. */ 2811293010Sadrian reg = rtwn_bb_read(sc, R92C_CCK0_SYSTEM); 2812293010Sadrian reg = (reg & ~0x00000010) | (prichlo ? 0 : 1) << 4; 2813293010Sadrian rtwn_bb_write(sc, R92C_CCK0_SYSTEM, reg); 2814293010Sadrian 2815293010Sadrian reg = rtwn_bb_read(sc, R92C_OFDM1_LSTF); 2816293010Sadrian reg = (reg & ~0x00000c00) | (prichlo ? 1 : 2) << 10; 2817293010Sadrian rtwn_bb_write(sc, R92C_OFDM1_LSTF, reg); 2818293010Sadrian 2819293010Sadrian rtwn_bb_write(sc, R92C_FPGA0_ANAPARAM2, 2820293010Sadrian rtwn_bb_read(sc, R92C_FPGA0_ANAPARAM2) & 2821293010Sadrian ~R92C_FPGA0_ANAPARAM2_CBW20); 2822293010Sadrian 2823293010Sadrian reg = rtwn_bb_read(sc, 0x818); 2824293010Sadrian reg = (reg & ~0x0c000000) | (prichlo ? 2 : 1) << 26; 2825293010Sadrian rtwn_bb_write(sc, 0x818, reg); 2826293010Sadrian 2827293010Sadrian /* Select 40MHz bandwidth. */ 2828293010Sadrian rtwn_rf_write(sc, 0, R92C_RF_CHNLBW, 2829293010Sadrian (sc->rf_chnlbw[0] & ~0xfff) | chan); 2830293010Sadrian } else 2831293010Sadrian#endif 2832293010Sadrian { 2833293010Sadrian rtwn_write_1(sc, R92C_BWOPMODE, 2834293010Sadrian rtwn_read_1(sc, R92C_BWOPMODE) | R92C_BWOPMODE_20MHZ); 2835293010Sadrian 2836293010Sadrian rtwn_bb_write(sc, R92C_FPGA0_RFMOD, 2837293010Sadrian rtwn_bb_read(sc, R92C_FPGA0_RFMOD) & ~R92C_RFMOD_40MHZ); 2838293010Sadrian rtwn_bb_write(sc, R92C_FPGA1_RFMOD, 2839293010Sadrian rtwn_bb_read(sc, R92C_FPGA1_RFMOD) & ~R92C_RFMOD_40MHZ); 2840293010Sadrian 2841293010Sadrian rtwn_bb_write(sc, R92C_FPGA0_ANAPARAM2, 2842293010Sadrian rtwn_bb_read(sc, R92C_FPGA0_ANAPARAM2) | 2843293010Sadrian R92C_FPGA0_ANAPARAM2_CBW20); 2844293010Sadrian 2845293010Sadrian /* Select 20MHz bandwidth. */ 2846293010Sadrian rtwn_rf_write(sc, 0, R92C_RF_CHNLBW, 2847293010Sadrian (sc->rf_chnlbw[0] & ~0xfff) | R92C_RF_CHNLBW_BW20 | chan); 2848293010Sadrian } 2849293010Sadrian} 2850293010Sadrian 2851293010Sadrianstatic int 2852293010Sadrianrtwn_iq_calib_chain(struct rtwn_softc *sc, int chain, uint16_t tx[2], 2853293010Sadrian uint16_t rx[2]) 2854293010Sadrian{ 2855293010Sadrian uint32_t status; 2856293010Sadrian int offset = chain * 0x20; 2857293010Sadrian 2858293010Sadrian if (chain == 0) { /* IQ calibration for chain 0. */ 2859293010Sadrian /* IQ calibration settings for chain 0. */ 2860293010Sadrian rtwn_bb_write(sc, 0xe30, 0x10008c1f); 2861293010Sadrian rtwn_bb_write(sc, 0xe34, 0x10008c1f); 2862293010Sadrian rtwn_bb_write(sc, 0xe38, 0x82140102); 2863293010Sadrian 2864293010Sadrian if (sc->ntxchains > 1) { 2865293010Sadrian rtwn_bb_write(sc, 0xe3c, 0x28160202); /* 2T */ 2866293010Sadrian /* IQ calibration settings for chain 1. */ 2867293010Sadrian rtwn_bb_write(sc, 0xe50, 0x10008c22); 2868293010Sadrian rtwn_bb_write(sc, 0xe54, 0x10008c22); 2869293010Sadrian rtwn_bb_write(sc, 0xe58, 0x82140102); 2870293010Sadrian rtwn_bb_write(sc, 0xe5c, 0x28160202); 2871293010Sadrian } else 2872293010Sadrian rtwn_bb_write(sc, 0xe3c, 0x28160502); /* 1T */ 2873293010Sadrian 2874293010Sadrian /* LO calibration settings. */ 2875293010Sadrian rtwn_bb_write(sc, 0xe4c, 0x001028d1); 2876293010Sadrian /* We're doing LO and IQ calibration in one shot. */ 2877293010Sadrian rtwn_bb_write(sc, 0xe48, 0xf9000000); 2878293010Sadrian rtwn_bb_write(sc, 0xe48, 0xf8000000); 2879293010Sadrian 2880293010Sadrian } else { /* IQ calibration for chain 1. */ 2881293010Sadrian /* We're doing LO and IQ calibration in one shot. */ 2882293010Sadrian rtwn_bb_write(sc, 0xe60, 0x00000002); 2883293010Sadrian rtwn_bb_write(sc, 0xe60, 0x00000000); 2884293010Sadrian } 2885293010Sadrian 2886293010Sadrian /* Give LO and IQ calibrations the time to complete. */ 2887293010Sadrian DELAY(1000); 2888293010Sadrian 2889293010Sadrian /* Read IQ calibration status. */ 2890293010Sadrian status = rtwn_bb_read(sc, 0xeac); 2891293010Sadrian 2892293010Sadrian if (status & (1 << (28 + chain * 3))) 2893293010Sadrian return (0); /* Tx failed. */ 2894293010Sadrian /* Read Tx IQ calibration results. */ 2895293010Sadrian tx[0] = (rtwn_bb_read(sc, 0xe94 + offset) >> 16) & 0x3ff; 2896293010Sadrian tx[1] = (rtwn_bb_read(sc, 0xe9c + offset) >> 16) & 0x3ff; 2897293010Sadrian if (tx[0] == 0x142 || tx[1] == 0x042) 2898293010Sadrian return (0); /* Tx failed. */ 2899293010Sadrian 2900293010Sadrian if (status & (1 << (27 + chain * 3))) 2901293010Sadrian return (1); /* Rx failed. */ 2902293010Sadrian /* Read Rx IQ calibration results. */ 2903293010Sadrian rx[0] = (rtwn_bb_read(sc, 0xea4 + offset) >> 16) & 0x3ff; 2904293010Sadrian rx[1] = (rtwn_bb_read(sc, 0xeac + offset) >> 16) & 0x3ff; 2905293010Sadrian if (rx[0] == 0x132 || rx[1] == 0x036) 2906293010Sadrian return (1); /* Rx failed. */ 2907293010Sadrian 2908293010Sadrian return (3); /* Both Tx and Rx succeeded. */ 2909293010Sadrian} 2910293010Sadrian 2911293010Sadrianstatic void 2912293010Sadrianrtwn_iq_calib_run(struct rtwn_softc *sc, int n, uint16_t tx[2][2], 2913293010Sadrian uint16_t rx[2][2]) 2914293010Sadrian{ 2915293010Sadrian /* Registers to save and restore during IQ calibration. */ 2916293010Sadrian struct iq_cal_regs { 2917293010Sadrian uint32_t adda[16]; 2918293010Sadrian uint8_t txpause; 2919293010Sadrian uint8_t bcn_ctrl; 2920293010Sadrian uint8_t ustime_tsf; 2921293010Sadrian uint32_t gpio_muxcfg; 2922293010Sadrian uint32_t ofdm0_trxpathena; 2923293010Sadrian uint32_t ofdm0_trmuxpar; 2924293010Sadrian uint32_t fpga0_rfifacesw1; 2925293010Sadrian } iq_cal_regs; 2926293010Sadrian static const uint16_t reg_adda[16] = { 2927293010Sadrian 0x85c, 0xe6c, 0xe70, 0xe74, 2928293010Sadrian 0xe78, 0xe7c, 0xe80, 0xe84, 2929293010Sadrian 0xe88, 0xe8c, 0xed0, 0xed4, 2930293010Sadrian 0xed8, 0xedc, 0xee0, 0xeec 2931293010Sadrian }; 2932293010Sadrian int i, chain; 2933293010Sadrian uint32_t hssi_param1; 2934293010Sadrian 2935293010Sadrian if (n == 0) { 2936293010Sadrian for (i = 0; i < nitems(reg_adda); i++) 2937293010Sadrian iq_cal_regs.adda[i] = rtwn_bb_read(sc, reg_adda[i]); 2938293010Sadrian 2939293010Sadrian iq_cal_regs.txpause = rtwn_read_1(sc, R92C_TXPAUSE); 2940293010Sadrian iq_cal_regs.bcn_ctrl = rtwn_read_1(sc, R92C_BCN_CTRL); 2941293010Sadrian iq_cal_regs.ustime_tsf = rtwn_read_1(sc, R92C_USTIME_TSF); 2942293010Sadrian iq_cal_regs.gpio_muxcfg = rtwn_read_4(sc, R92C_GPIO_MUXCFG); 2943293010Sadrian } 2944293010Sadrian 2945293010Sadrian if (sc->ntxchains == 1) { 2946293010Sadrian rtwn_bb_write(sc, reg_adda[0], 0x0b1b25a0); 2947293010Sadrian for (i = 1; i < nitems(reg_adda); i++) 2948293010Sadrian rtwn_bb_write(sc, reg_adda[i], 0x0bdb25a0); 2949293010Sadrian } else { 2950293010Sadrian for (i = 0; i < nitems(reg_adda); i++) 2951293010Sadrian rtwn_bb_write(sc, reg_adda[i], 0x04db25a4); 2952293010Sadrian } 2953293010Sadrian 2954293010Sadrian hssi_param1 = rtwn_bb_read(sc, R92C_HSSI_PARAM1(0)); 2955293010Sadrian if (!(hssi_param1 & R92C_HSSI_PARAM1_PI)) { 2956293010Sadrian rtwn_bb_write(sc, R92C_HSSI_PARAM1(0), 2957293010Sadrian hssi_param1 | R92C_HSSI_PARAM1_PI); 2958293010Sadrian rtwn_bb_write(sc, R92C_HSSI_PARAM1(1), 2959293010Sadrian hssi_param1 | R92C_HSSI_PARAM1_PI); 2960293010Sadrian } 2961293010Sadrian 2962293010Sadrian if (n == 0) { 2963293010Sadrian iq_cal_regs.ofdm0_trxpathena = 2964293010Sadrian rtwn_bb_read(sc, R92C_OFDM0_TRXPATHENA); 2965293010Sadrian iq_cal_regs.ofdm0_trmuxpar = 2966293010Sadrian rtwn_bb_read(sc, R92C_OFDM0_TRMUXPAR); 2967293010Sadrian iq_cal_regs.fpga0_rfifacesw1 = 2968293010Sadrian rtwn_bb_read(sc, R92C_FPGA0_RFIFACESW(1)); 2969293010Sadrian } 2970293010Sadrian 2971293010Sadrian rtwn_bb_write(sc, R92C_OFDM0_TRXPATHENA, 0x03a05600); 2972293010Sadrian rtwn_bb_write(sc, R92C_OFDM0_TRMUXPAR, 0x000800e4); 2973293010Sadrian rtwn_bb_write(sc, R92C_FPGA0_RFIFACESW(1), 0x22204000); 2974293010Sadrian if (sc->ntxchains > 1) { 2975293010Sadrian rtwn_bb_write(sc, R92C_LSSI_PARAM(0), 0x00010000); 2976293010Sadrian rtwn_bb_write(sc, R92C_LSSI_PARAM(1), 0x00010000); 2977293010Sadrian } 2978293010Sadrian 2979293010Sadrian rtwn_write_1(sc, R92C_TXPAUSE, 0x3f); 2980293010Sadrian rtwn_write_1(sc, R92C_BCN_CTRL, iq_cal_regs.bcn_ctrl & ~(0x08)); 2981293010Sadrian rtwn_write_1(sc, R92C_USTIME_TSF, iq_cal_regs.ustime_tsf & ~(0x08)); 2982293010Sadrian rtwn_write_1(sc, R92C_GPIO_MUXCFG, 2983293010Sadrian iq_cal_regs.gpio_muxcfg & ~(0x20)); 2984293010Sadrian 2985293010Sadrian rtwn_bb_write(sc, 0x0b68, 0x00080000); 2986293010Sadrian if (sc->ntxchains > 1) 2987293010Sadrian rtwn_bb_write(sc, 0x0b6c, 0x00080000); 2988293010Sadrian 2989293010Sadrian rtwn_bb_write(sc, 0x0e28, 0x80800000); 2990293010Sadrian rtwn_bb_write(sc, 0x0e40, 0x01007c00); 2991293010Sadrian rtwn_bb_write(sc, 0x0e44, 0x01004800); 2992293010Sadrian 2993293010Sadrian rtwn_bb_write(sc, 0x0b68, 0x00080000); 2994293010Sadrian 2995293010Sadrian for (chain = 0; chain < sc->ntxchains; chain++) { 2996293010Sadrian if (chain > 0) { 2997293010Sadrian /* Put chain 0 on standby. */ 2998293010Sadrian rtwn_bb_write(sc, 0x0e28, 0x00); 2999293010Sadrian rtwn_bb_write(sc, R92C_LSSI_PARAM(0), 0x00010000); 3000293010Sadrian rtwn_bb_write(sc, 0x0e28, 0x80800000); 3001293010Sadrian 3002293010Sadrian /* Enable chain 1. */ 3003293010Sadrian for (i = 0; i < nitems(reg_adda); i++) 3004293010Sadrian rtwn_bb_write(sc, reg_adda[i], 0x0b1b25a4); 3005293010Sadrian } 3006293010Sadrian 3007293010Sadrian /* Run IQ calibration twice. */ 3008293010Sadrian for (i = 0; i < 2; i++) { 3009293010Sadrian int ret; 3010293010Sadrian 3011293010Sadrian ret = rtwn_iq_calib_chain(sc, chain, 3012293010Sadrian tx[chain], rx[chain]); 3013293010Sadrian if (ret == 0) { 3014293010Sadrian DPRINTF(("%s: chain %d: Tx failed.\n", 3015293010Sadrian __func__, chain)); 3016293010Sadrian tx[chain][0] = 0xff; 3017293010Sadrian tx[chain][1] = 0xff; 3018293010Sadrian rx[chain][0] = 0xff; 3019293010Sadrian rx[chain][1] = 0xff; 3020293010Sadrian } else if (ret == 1) { 3021293010Sadrian DPRINTF(("%s: chain %d: Rx failed.\n", 3022293010Sadrian __func__, chain)); 3023293010Sadrian rx[chain][0] = 0xff; 3024293010Sadrian rx[chain][1] = 0xff; 3025293010Sadrian } else if (ret == 3) { 3026293010Sadrian DPRINTF(("%s: chain %d: Both Tx and Rx " 3027293010Sadrian "succeeded.\n", __func__, chain)); 3028293010Sadrian } 3029293010Sadrian } 3030293010Sadrian 3031293010Sadrian DPRINTF(("%s: results for run %d chain %d: tx[0]=0x%x, " 3032293010Sadrian "tx[1]=0x%x rx[0]=0x%x rx[1]=0x%x\n", __func__, n, chain, 3033293010Sadrian tx[chain][0], tx[chain][1], rx[chain][0], rx[chain][1])); 3034293010Sadrian } 3035293010Sadrian 3036293010Sadrian rtwn_bb_write(sc, R92C_OFDM0_TRXPATHENA, 3037293010Sadrian iq_cal_regs.ofdm0_trxpathena); 3038293010Sadrian rtwn_bb_write(sc, R92C_FPGA0_RFIFACESW(1), 3039293010Sadrian iq_cal_regs.fpga0_rfifacesw1); 3040293010Sadrian rtwn_bb_write(sc, R92C_OFDM0_TRMUXPAR, iq_cal_regs.ofdm0_trmuxpar); 3041293010Sadrian 3042293010Sadrian rtwn_bb_write(sc, 0x0e28, 0x00); 3043293010Sadrian rtwn_bb_write(sc, R92C_LSSI_PARAM(0), 0x00032ed3); 3044293010Sadrian if (sc->ntxchains > 1) 3045293010Sadrian rtwn_bb_write(sc, R92C_LSSI_PARAM(1), 0x00032ed3); 3046293010Sadrian 3047293010Sadrian if (n != 0) { 3048293010Sadrian if (!(hssi_param1 & R92C_HSSI_PARAM1_PI)) { 3049293010Sadrian rtwn_bb_write(sc, R92C_HSSI_PARAM1(0), hssi_param1); 3050293010Sadrian rtwn_bb_write(sc, R92C_HSSI_PARAM1(1), hssi_param1); 3051293010Sadrian } 3052293010Sadrian 3053293010Sadrian for (i = 0; i < nitems(reg_adda); i++) 3054293010Sadrian rtwn_bb_write(sc, reg_adda[i], iq_cal_regs.adda[i]); 3055293010Sadrian 3056293010Sadrian rtwn_write_1(sc, R92C_TXPAUSE, iq_cal_regs.txpause); 3057293010Sadrian rtwn_write_1(sc, R92C_BCN_CTRL, iq_cal_regs.bcn_ctrl); 3058293010Sadrian rtwn_write_1(sc, R92C_USTIME_TSF, iq_cal_regs.ustime_tsf); 3059293010Sadrian rtwn_write_4(sc, R92C_GPIO_MUXCFG, iq_cal_regs.gpio_muxcfg); 3060293010Sadrian } 3061293010Sadrian} 3062293010Sadrian 3063293010Sadrian#define RTWN_IQ_CAL_MAX_TOLERANCE 5 3064293010Sadrianstatic int 3065293010Sadrianrtwn_iq_calib_compare_results(uint16_t tx1[2][2], uint16_t rx1[2][2], 3066293010Sadrian uint16_t tx2[2][2], uint16_t rx2[2][2], int ntxchains) 3067293010Sadrian{ 3068293010Sadrian int chain, i, tx_ok[2], rx_ok[2]; 3069293010Sadrian 3070293010Sadrian tx_ok[0] = tx_ok[1] = rx_ok[0] = rx_ok[1] = 0; 3071293010Sadrian for (chain = 0; chain < ntxchains; chain++) { 3072293010Sadrian for (i = 0; i < 2; i++) { 3073293010Sadrian if (tx1[chain][i] == 0xff || tx2[chain][i] == 0xff || 3074293010Sadrian rx1[chain][i] == 0xff || rx2[chain][i] == 0xff) 3075293010Sadrian continue; 3076293010Sadrian 3077293010Sadrian tx_ok[chain] = (abs(tx1[chain][i] - tx2[chain][i]) <= 3078293010Sadrian RTWN_IQ_CAL_MAX_TOLERANCE); 3079293010Sadrian 3080293010Sadrian rx_ok[chain] = (abs(rx1[chain][i] - rx2[chain][i]) <= 3081293010Sadrian RTWN_IQ_CAL_MAX_TOLERANCE); 3082293010Sadrian } 3083293010Sadrian } 3084293010Sadrian 3085293010Sadrian if (ntxchains > 1) 3086293010Sadrian return (tx_ok[0] && tx_ok[1] && rx_ok[0] && rx_ok[1]); 3087293010Sadrian else 3088293010Sadrian return (tx_ok[0] && rx_ok[0]); 3089293010Sadrian} 3090293010Sadrian#undef RTWN_IQ_CAL_MAX_TOLERANCE 3091293010Sadrian 3092293010Sadrianstatic void 3093293010Sadrianrtwn_iq_calib_write_results(struct rtwn_softc *sc, uint16_t tx[2], 3094293010Sadrian uint16_t rx[2], int chain) 3095293010Sadrian{ 3096293010Sadrian uint32_t reg, val, x; 3097293010Sadrian long y, tx_c; 3098293010Sadrian 3099293010Sadrian if (tx[0] == 0xff || tx[1] == 0xff) 3100293010Sadrian return; 3101293010Sadrian 3102293010Sadrian reg = rtwn_bb_read(sc, R92C_OFDM0_TXIQIMBALANCE(chain)); 3103293010Sadrian val = ((reg >> 22) & 0x3ff); 3104293010Sadrian x = tx[0]; 3105293010Sadrian if (x & 0x0200) 3106293010Sadrian x |= 0xfc00; 3107293010Sadrian reg = (((x * val) >> 8) & 0x3ff); 3108293010Sadrian rtwn_bb_write(sc, R92C_OFDM0_TXIQIMBALANCE(chain), reg); 3109293010Sadrian 3110293010Sadrian reg = rtwn_bb_read(sc, R92C_OFDM0_ECCATHRESHOLD); 3111293010Sadrian if (((x * val) >> 7) & 0x01) 3112293010Sadrian reg |= 0x80000000; 3113293010Sadrian else 3114293010Sadrian reg &= ~0x80000000; 3115293010Sadrian rtwn_bb_write(sc, R92C_OFDM0_ECCATHRESHOLD, reg); 3116293010Sadrian 3117293010Sadrian y = tx[1]; 3118293010Sadrian if (y & 0x00000200) 3119293010Sadrian y |= 0xfffffc00; 3120293010Sadrian tx_c = (y * val) >> 8; 3121293010Sadrian reg = rtwn_bb_read(sc, R92C_OFDM0_TXAFE(chain)); 3122293010Sadrian reg |= ((((tx_c & 0x3c0) >> 6) << 24) & 0xf0000000); 3123293010Sadrian rtwn_bb_write(sc, R92C_OFDM0_TXAFE(chain), reg); 3124293010Sadrian 3125293010Sadrian reg = rtwn_bb_read(sc, R92C_OFDM0_TXIQIMBALANCE(chain)); 3126293010Sadrian reg |= (((tx_c & 0x3f) << 16) & 0x003F0000); 3127293010Sadrian rtwn_bb_write(sc, R92C_OFDM0_TXIQIMBALANCE(chain), reg); 3128293010Sadrian 3129293010Sadrian reg = rtwn_bb_read(sc, R92C_OFDM0_ECCATHRESHOLD); 3130293010Sadrian if (((y * val) >> 7) & 0x01) 3131293010Sadrian reg |= 0x20000000; 3132293010Sadrian else 3133293010Sadrian reg &= ~0x20000000; 3134293010Sadrian rtwn_bb_write(sc, R92C_OFDM0_ECCATHRESHOLD, reg); 3135293010Sadrian 3136293010Sadrian if (rx[0] == 0xff || rx[1] == 0xff) 3137293010Sadrian return; 3138293010Sadrian 3139293010Sadrian reg = rtwn_bb_read(sc, R92C_OFDM0_RXIQIMBALANCE(chain)); 3140293010Sadrian reg |= (rx[0] & 0x3ff); 3141293010Sadrian rtwn_bb_write(sc, R92C_OFDM0_RXIQIMBALANCE(chain), reg); 3142293010Sadrian reg |= (((rx[1] & 0x03f) << 8) & 0xFC00); 3143293010Sadrian rtwn_bb_write(sc, R92C_OFDM0_RXIQIMBALANCE(chain), reg); 3144293010Sadrian 3145293010Sadrian if (chain == 0) { 3146293010Sadrian reg = rtwn_bb_read(sc, R92C_OFDM0_RXIQEXTANTA); 3147293010Sadrian reg |= (((rx[1] & 0xf) >> 6) & 0x000f); 3148293010Sadrian rtwn_bb_write(sc, R92C_OFDM0_RXIQEXTANTA, reg); 3149293010Sadrian } else { 3150293010Sadrian reg = rtwn_bb_read(sc, R92C_OFDM0_AGCRSSITABLE); 3151293010Sadrian reg |= ((((rx[1] & 0xf) >> 6) << 12) & 0xf000); 3152293010Sadrian rtwn_bb_write(sc, R92C_OFDM0_AGCRSSITABLE, reg); 3153293010Sadrian } 3154293010Sadrian} 3155293010Sadrian 3156293010Sadrian#define RTWN_IQ_CAL_NRUN 3 3157293010Sadrianstatic void 3158293010Sadrianrtwn_iq_calib(struct rtwn_softc *sc) 3159293010Sadrian{ 3160293010Sadrian uint16_t tx[RTWN_IQ_CAL_NRUN][2][2], rx[RTWN_IQ_CAL_NRUN][2][2]; 3161293010Sadrian int n, valid; 3162293010Sadrian 3163293010Sadrian valid = 0; 3164293010Sadrian for (n = 0; n < RTWN_IQ_CAL_NRUN; n++) { 3165293010Sadrian rtwn_iq_calib_run(sc, n, tx[n], rx[n]); 3166293010Sadrian 3167293010Sadrian if (n == 0) 3168293010Sadrian continue; 3169293010Sadrian 3170293010Sadrian /* Valid results remain stable after consecutive runs. */ 3171293010Sadrian valid = rtwn_iq_calib_compare_results(tx[n - 1], rx[n - 1], 3172293010Sadrian tx[n], rx[n], sc->ntxchains); 3173293010Sadrian if (valid) 3174293010Sadrian break; 3175293010Sadrian } 3176293010Sadrian 3177293010Sadrian if (valid) { 3178293010Sadrian rtwn_iq_calib_write_results(sc, tx[n][0], rx[n][0], 0); 3179293010Sadrian if (sc->ntxchains > 1) 3180293010Sadrian rtwn_iq_calib_write_results(sc, tx[n][1], rx[n][1], 1); 3181293010Sadrian } 3182293010Sadrian} 3183293010Sadrian#undef RTWN_IQ_CAL_NRUN 3184293010Sadrian 3185293010Sadrianstatic void 3186293010Sadrianrtwn_lc_calib(struct rtwn_softc *sc) 3187293010Sadrian{ 3188293010Sadrian uint32_t rf_ac[2]; 3189293010Sadrian uint8_t txmode; 3190293010Sadrian int i; 3191293010Sadrian 3192293010Sadrian txmode = rtwn_read_1(sc, R92C_OFDM1_LSTF + 3); 3193293010Sadrian if ((txmode & 0x70) != 0) { 3194293010Sadrian /* Disable all continuous Tx. */ 3195293010Sadrian rtwn_write_1(sc, R92C_OFDM1_LSTF + 3, txmode & ~0x70); 3196293010Sadrian 3197293010Sadrian /* Set RF mode to standby mode. */ 3198293010Sadrian for (i = 0; i < sc->nrxchains; i++) { 3199293010Sadrian rf_ac[i] = rtwn_rf_read(sc, i, R92C_RF_AC); 3200293010Sadrian rtwn_rf_write(sc, i, R92C_RF_AC, 3201293010Sadrian RW(rf_ac[i], R92C_RF_AC_MODE, 3202293010Sadrian R92C_RF_AC_MODE_STANDBY)); 3203293010Sadrian } 3204293010Sadrian } else { 3205293010Sadrian /* Block all Tx queues. */ 3206293010Sadrian rtwn_write_1(sc, R92C_TXPAUSE, 0xff); 3207293010Sadrian } 3208293010Sadrian /* Start calibration. */ 3209293010Sadrian rtwn_rf_write(sc, 0, R92C_RF_CHNLBW, 3210293010Sadrian rtwn_rf_read(sc, 0, R92C_RF_CHNLBW) | R92C_RF_CHNLBW_LCSTART); 3211293010Sadrian 3212293010Sadrian /* Give calibration the time to complete. */ 3213293010Sadrian DELAY(100); 3214293010Sadrian 3215293010Sadrian /* Restore configuration. */ 3216293010Sadrian if ((txmode & 0x70) != 0) { 3217293010Sadrian /* Restore Tx mode. */ 3218293010Sadrian rtwn_write_1(sc, R92C_OFDM1_LSTF + 3, txmode); 3219293010Sadrian /* Restore RF mode. */ 3220293010Sadrian for (i = 0; i < sc->nrxchains; i++) 3221293010Sadrian rtwn_rf_write(sc, i, R92C_RF_AC, rf_ac[i]); 3222293010Sadrian } else { 3223293010Sadrian /* Unblock all Tx queues. */ 3224293010Sadrian rtwn_write_1(sc, R92C_TXPAUSE, 0x00); 3225293010Sadrian } 3226293010Sadrian} 3227293010Sadrian 3228293010Sadrianstatic void 3229293010Sadrianrtwn_temp_calib(struct rtwn_softc *sc) 3230293010Sadrian{ 3231293010Sadrian int temp; 3232293010Sadrian 3233293010Sadrian if (sc->thcal_state == 0) { 3234293010Sadrian /* Start measuring temperature. */ 3235293010Sadrian rtwn_rf_write(sc, 0, R92C_RF_T_METER, 0x60); 3236293010Sadrian sc->thcal_state = 1; 3237293010Sadrian return; 3238293010Sadrian } 3239293010Sadrian sc->thcal_state = 0; 3240293010Sadrian 3241293010Sadrian /* Read measured temperature. */ 3242293010Sadrian temp = rtwn_rf_read(sc, 0, R92C_RF_T_METER) & 0x1f; 3243293010Sadrian if (temp == 0) /* Read failed, skip. */ 3244293010Sadrian return; 3245293010Sadrian DPRINTFN(2, ("temperature=%d\n", temp)); 3246293010Sadrian 3247293010Sadrian /* 3248293010Sadrian * Redo IQ and LC calibration if temperature changed significantly 3249293010Sadrian * since last calibration. 3250293010Sadrian */ 3251293010Sadrian if (sc->thcal_lctemp == 0) { 3252293010Sadrian /* First calibration is performed in rtwn_init(). */ 3253293010Sadrian sc->thcal_lctemp = temp; 3254293010Sadrian } else if (abs(temp - sc->thcal_lctemp) > 1) { 3255293010Sadrian DPRINTF(("IQ/LC calib triggered by temp: %d -> %d\n", 3256293010Sadrian sc->thcal_lctemp, temp)); 3257293010Sadrian rtwn_iq_calib(sc); 3258293010Sadrian rtwn_lc_calib(sc); 3259293010Sadrian /* Record temperature of last calibration. */ 3260293010Sadrian sc->thcal_lctemp = temp; 3261293010Sadrian } 3262293010Sadrian} 3263293010Sadrian 3264294842Savosstatic int 3265294842Savosrtwn_init(struct rtwn_softc *sc) 3266293010Sadrian{ 3267293010Sadrian struct ieee80211com *ic = &sc->sc_ic; 3268293010Sadrian struct ieee80211vap *vap = TAILQ_FIRST(&ic->ic_vaps); 3269293010Sadrian uint32_t reg; 3270293010Sadrian uint8_t macaddr[IEEE80211_ADDR_LEN]; 3271293010Sadrian int i, error; 3272293010Sadrian 3273294842Savos RTWN_LOCK(sc); 3274293010Sadrian 3275294842Savos if (sc->sc_flags & RTWN_RUNNING) { 3276294842Savos RTWN_UNLOCK(sc); 3277294842Savos return 0; 3278294842Savos } 3279294842Savos sc->sc_flags |= RTWN_RUNNING; 3280294842Savos 3281293010Sadrian /* Init firmware commands ring. */ 3282293010Sadrian sc->fwcur = 0; 3283293010Sadrian 3284293010Sadrian /* Power on adapter. */ 3285293010Sadrian error = rtwn_power_on(sc); 3286293010Sadrian if (error != 0) { 3287293010Sadrian device_printf(sc->sc_dev, "could not power on adapter\n"); 3288293010Sadrian goto fail; 3289293010Sadrian } 3290293010Sadrian 3291293010Sadrian /* Initialize DMA. */ 3292293010Sadrian error = rtwn_dma_init(sc); 3293293010Sadrian if (error != 0) { 3294293010Sadrian device_printf(sc->sc_dev, "could not initialize DMA\n"); 3295293010Sadrian goto fail; 3296293010Sadrian } 3297293010Sadrian 3298293010Sadrian /* Set info size in Rx descriptors (in 64-bit words). */ 3299293010Sadrian rtwn_write_1(sc, R92C_RX_DRVINFO_SZ, 4); 3300293010Sadrian 3301293010Sadrian /* Disable interrupts. */ 3302293010Sadrian rtwn_write_4(sc, R92C_HISR, 0x00000000); 3303293010Sadrian rtwn_write_4(sc, R92C_HIMR, 0x00000000); 3304293010Sadrian 3305293010Sadrian /* Set MAC address. */ 3306293010Sadrian IEEE80211_ADDR_COPY(macaddr, vap ? vap->iv_myaddr : ic->ic_macaddr); 3307293010Sadrian for (i = 0; i < IEEE80211_ADDR_LEN; i++) 3308293010Sadrian rtwn_write_1(sc, R92C_MACID + i, macaddr[i]); 3309293010Sadrian 3310293010Sadrian /* Set initial network type. */ 3311293010Sadrian reg = rtwn_read_4(sc, R92C_CR); 3312293010Sadrian reg = RW(reg, R92C_CR_NETTYPE, R92C_CR_NETTYPE_INFRA); 3313293010Sadrian rtwn_write_4(sc, R92C_CR, reg); 3314293010Sadrian 3315293010Sadrian rtwn_rxfilter_init(sc); 3316293010Sadrian 3317293010Sadrian reg = rtwn_read_4(sc, R92C_RRSR); 3318293010Sadrian reg = RW(reg, R92C_RRSR_RATE_BITMAP, R92C_RRSR_RATE_ALL); 3319293010Sadrian rtwn_write_4(sc, R92C_RRSR, reg); 3320293010Sadrian 3321293010Sadrian /* Set short/long retry limits. */ 3322293010Sadrian rtwn_write_2(sc, R92C_RL, 3323293010Sadrian SM(R92C_RL_SRL, 0x07) | SM(R92C_RL_LRL, 0x07)); 3324293010Sadrian 3325293010Sadrian /* Initialize EDCA parameters. */ 3326293010Sadrian rtwn_edca_init(sc); 3327293010Sadrian 3328293010Sadrian /* Set data and response automatic rate fallback retry counts. */ 3329293010Sadrian rtwn_write_4(sc, R92C_DARFRC + 0, 0x01000000); 3330293010Sadrian rtwn_write_4(sc, R92C_DARFRC + 4, 0x07060504); 3331293010Sadrian rtwn_write_4(sc, R92C_RARFRC + 0, 0x01000000); 3332293010Sadrian rtwn_write_4(sc, R92C_RARFRC + 4, 0x07060504); 3333293010Sadrian 3334293010Sadrian rtwn_write_2(sc, R92C_FWHW_TXQ_CTRL, 0x1f80); 3335293010Sadrian 3336293010Sadrian /* Set ACK timeout. */ 3337293010Sadrian rtwn_write_1(sc, R92C_ACKTO, 0x40); 3338293010Sadrian 3339293010Sadrian /* Initialize beacon parameters. */ 3340293010Sadrian rtwn_write_2(sc, R92C_TBTT_PROHIBIT, 0x6404); 3341293010Sadrian rtwn_write_1(sc, R92C_DRVERLYINT, 0x05); 3342293010Sadrian rtwn_write_1(sc, R92C_BCNDMATIM, 0x02); 3343293010Sadrian rtwn_write_2(sc, R92C_BCNTCFG, 0x660f); 3344293010Sadrian 3345293010Sadrian /* Setup AMPDU aggregation. */ 3346293010Sadrian rtwn_write_4(sc, R92C_AGGLEN_LMT, 0x99997631); /* MCS7~0 */ 3347293010Sadrian rtwn_write_1(sc, R92C_AGGR_BREAK_TIME, 0x16); 3348293010Sadrian 3349293010Sadrian rtwn_write_1(sc, R92C_BCN_MAX_ERR, 0xff); 3350293010Sadrian rtwn_write_1(sc, R92C_BCN_CTRL, R92C_BCN_CTRL_DIS_TSF_UDT0); 3351293010Sadrian 3352293010Sadrian rtwn_write_4(sc, R92C_PIFS, 0x1c); 3353293010Sadrian rtwn_write_4(sc, R92C_MCUTST_1, 0x0); 3354293010Sadrian 3355293010Sadrian /* Load 8051 microcode. */ 3356293010Sadrian error = rtwn_load_firmware(sc); 3357293010Sadrian if (error != 0) 3358293010Sadrian goto fail; 3359293010Sadrian 3360293010Sadrian /* Initialize MAC/BB/RF blocks. */ 3361293010Sadrian rtwn_mac_init(sc); 3362293010Sadrian rtwn_bb_init(sc); 3363293010Sadrian rtwn_rf_init(sc); 3364293010Sadrian 3365293010Sadrian /* Turn CCK and OFDM blocks on. */ 3366293010Sadrian reg = rtwn_bb_read(sc, R92C_FPGA0_RFMOD); 3367293010Sadrian reg |= R92C_RFMOD_CCK_EN; 3368293010Sadrian rtwn_bb_write(sc, R92C_FPGA0_RFMOD, reg); 3369293010Sadrian reg = rtwn_bb_read(sc, R92C_FPGA0_RFMOD); 3370293010Sadrian reg |= R92C_RFMOD_OFDM_EN; 3371293010Sadrian rtwn_bb_write(sc, R92C_FPGA0_RFMOD, reg); 3372293010Sadrian 3373293010Sadrian /* Clear per-station keys table. */ 3374293010Sadrian rtwn_cam_init(sc); 3375293010Sadrian 3376293010Sadrian /* Enable hardware sequence numbering. */ 3377293010Sadrian rtwn_write_1(sc, R92C_HWSEQ_CTRL, 0xff); 3378293010Sadrian 3379293010Sadrian /* Perform LO and IQ calibrations. */ 3380293010Sadrian rtwn_iq_calib(sc); 3381293010Sadrian /* Perform LC calibration. */ 3382293010Sadrian rtwn_lc_calib(sc); 3383293010Sadrian 3384293010Sadrian rtwn_pa_bias_init(sc); 3385293010Sadrian 3386293010Sadrian /* Initialize GPIO setting. */ 3387293010Sadrian rtwn_write_1(sc, R92C_GPIO_MUXCFG, 3388293010Sadrian rtwn_read_1(sc, R92C_GPIO_MUXCFG) & ~R92C_GPIO_MUXCFG_ENBT); 3389293010Sadrian 3390293010Sadrian /* Fix for lower temperature. */ 3391293010Sadrian rtwn_write_1(sc, 0x15, 0xe9); 3392293010Sadrian 3393293010Sadrian /* CLear pending interrupts. */ 3394293010Sadrian rtwn_write_4(sc, R92C_HISR, 0xffffffff); 3395293010Sadrian 3396293010Sadrian /* Enable interrupts. */ 3397293010Sadrian rtwn_write_4(sc, R92C_HIMR, RTWN_INT_ENABLE); 3398293010Sadrian 3399293010Sadrian callout_reset(&sc->watchdog_to, hz, rtwn_watchdog, sc); 3400293010Sadrian 3401293010Sadrianfail: 3402294842Savos if (error != 0) 3403294842Savos rtwn_stop_locked(sc); 3404294842Savos 3405294842Savos RTWN_UNLOCK(sc); 3406294842Savos 3407294842Savos return error; 3408293010Sadrian} 3409293010Sadrian 3410293010Sadrianstatic void 3411293010Sadrianrtwn_stop_locked(struct rtwn_softc *sc) 3412293010Sadrian{ 3413293010Sadrian uint16_t reg; 3414293010Sadrian int i; 3415293010Sadrian 3416293010Sadrian RTWN_LOCK_ASSERT(sc); 3417293010Sadrian 3418294842Savos if (!(sc->sc_flags & RTWN_RUNNING)) 3419294842Savos return; 3420294842Savos 3421293010Sadrian sc->sc_tx_timer = 0; 3422293010Sadrian callout_stop(&sc->watchdog_to); 3423293010Sadrian callout_stop(&sc->calib_to); 3424293010Sadrian sc->sc_flags &= ~RTWN_RUNNING; 3425293010Sadrian 3426293010Sadrian /* Disable interrupts. */ 3427293010Sadrian rtwn_write_4(sc, R92C_HISR, 0x00000000); 3428293010Sadrian rtwn_write_4(sc, R92C_HIMR, 0x00000000); 3429293010Sadrian 3430293010Sadrian /* Stop hardware. */ 3431293010Sadrian rtwn_write_1(sc, R92C_TXPAUSE, 0xff); 3432293010Sadrian rtwn_write_1(sc, R92C_RF_CTRL, 0x00); 3433293010Sadrian reg = rtwn_read_1(sc, R92C_SYS_FUNC_EN); 3434293010Sadrian reg |= R92C_SYS_FUNC_EN_BB_GLB_RST; 3435293010Sadrian rtwn_write_1(sc, R92C_SYS_FUNC_EN, reg); 3436293010Sadrian reg &= ~R92C_SYS_FUNC_EN_BB_GLB_RST; 3437293010Sadrian rtwn_write_1(sc, R92C_SYS_FUNC_EN, reg); 3438293010Sadrian reg = rtwn_read_2(sc, R92C_CR); 3439293010Sadrian reg &= ~(R92C_CR_HCI_TXDMA_EN | R92C_CR_HCI_RXDMA_EN | 3440293010Sadrian R92C_CR_TXDMA_EN | R92C_CR_RXDMA_EN | R92C_CR_PROTOCOL_EN | 3441293010Sadrian R92C_CR_SCHEDULE_EN | R92C_CR_MACTXEN | R92C_CR_MACRXEN | 3442293010Sadrian R92C_CR_ENSEC); 3443293010Sadrian rtwn_write_2(sc, R92C_CR, reg); 3444293010Sadrian if (rtwn_read_1(sc, R92C_MCUFWDL) & R92C_MCUFWDL_RAM_DL_SEL) 3445293010Sadrian rtwn_fw_reset(sc); 3446293010Sadrian /* TODO: linux does additional btcoex stuff here */ 3447293010Sadrian rtwn_write_2(sc, R92C_AFE_PLL_CTRL, 0x80); /* linux magic number */ 3448293010Sadrian rtwn_write_1(sc, R92C_SPS0_CTRL, 0x23); /* ditto */ 3449293010Sadrian rtwn_write_1(sc, R92C_AFE_XTAL_CTRL, 0x0e); /* different with btcoex */ 3450293010Sadrian rtwn_write_1(sc, R92C_RSV_CTRL, 0x0e); 3451293010Sadrian rtwn_write_1(sc, R92C_APS_FSMCO, R92C_APS_FSMCO_PDN_EN); 3452293010Sadrian 3453293010Sadrian for (i = 0; i < RTWN_NTXQUEUES; i++) 3454293010Sadrian rtwn_reset_tx_list(sc, i); 3455293010Sadrian rtwn_reset_rx_list(sc); 3456293010Sadrian} 3457293010Sadrian 3458293010Sadrianstatic void 3459293010Sadrianrtwn_stop(struct rtwn_softc *sc) 3460293010Sadrian{ 3461293010Sadrian RTWN_LOCK(sc); 3462293010Sadrian rtwn_stop_locked(sc); 3463293010Sadrian RTWN_UNLOCK(sc); 3464293010Sadrian} 3465293010Sadrian 3466293010Sadrianstatic void 3467293010Sadrianrtwn_intr(void *arg) 3468293010Sadrian{ 3469293010Sadrian struct rtwn_softc *sc = arg; 3470293010Sadrian uint32_t status; 3471293010Sadrian int i; 3472293010Sadrian 3473293010Sadrian RTWN_LOCK(sc); 3474293010Sadrian status = rtwn_read_4(sc, R92C_HISR); 3475293010Sadrian if (status == 0 || status == 0xffffffff) { 3476293010Sadrian RTWN_UNLOCK(sc); 3477293010Sadrian return; 3478293010Sadrian } 3479293010Sadrian 3480293010Sadrian /* Disable interrupts. */ 3481293010Sadrian rtwn_write_4(sc, R92C_HIMR, 0x00000000); 3482293010Sadrian 3483293010Sadrian /* Ack interrupts. */ 3484293010Sadrian rtwn_write_4(sc, R92C_HISR, status); 3485293010Sadrian 3486293010Sadrian /* Vendor driver treats RX errors like ROK... */ 3487293010Sadrian if (status & (R92C_IMR_ROK | R92C_IMR_RXFOVW | R92C_IMR_RDU)) { 3488293010Sadrian bus_dmamap_sync(sc->rx_ring.desc_dmat, sc->rx_ring.desc_map, 3489293010Sadrian BUS_DMASYNC_POSTREAD); 3490293010Sadrian 3491293010Sadrian for (i = 0; i < RTWN_RX_LIST_COUNT; i++) { 3492293010Sadrian struct r92c_rx_desc *rx_desc = &sc->rx_ring.desc[i]; 3493293010Sadrian struct rtwn_rx_data *rx_data = &sc->rx_ring.rx_data[i]; 3494293010Sadrian 3495293010Sadrian if (le32toh(rx_desc->rxdw0) & R92C_RXDW0_OWN) 3496293010Sadrian continue; 3497293010Sadrian 3498293010Sadrian rtwn_rx_frame(sc, rx_desc, rx_data, i); 3499293010Sadrian } 3500293010Sadrian } 3501293010Sadrian 3502293010Sadrian if (status & R92C_IMR_BDOK) 3503293010Sadrian rtwn_tx_done(sc, RTWN_BEACON_QUEUE); 3504293010Sadrian if (status & R92C_IMR_HIGHDOK) 3505293010Sadrian rtwn_tx_done(sc, RTWN_HIGH_QUEUE); 3506293010Sadrian if (status & R92C_IMR_MGNTDOK) 3507293010Sadrian rtwn_tx_done(sc, RTWN_MGNT_QUEUE); 3508293010Sadrian if (status & R92C_IMR_BKDOK) 3509293010Sadrian rtwn_tx_done(sc, RTWN_BK_QUEUE); 3510293010Sadrian if (status & R92C_IMR_BEDOK) 3511293010Sadrian rtwn_tx_done(sc, RTWN_BE_QUEUE); 3512293010Sadrian if (status & R92C_IMR_VIDOK) 3513293010Sadrian rtwn_tx_done(sc, RTWN_VI_QUEUE); 3514293010Sadrian if (status & R92C_IMR_VODOK) 3515293010Sadrian rtwn_tx_done(sc, RTWN_VO_QUEUE); 3516293010Sadrian 3517293010Sadrian /* Enable interrupts. */ 3518293010Sadrian rtwn_write_4(sc, R92C_HIMR, RTWN_INT_ENABLE); 3519293010Sadrian 3520293010Sadrian RTWN_UNLOCK(sc); 3521293010Sadrian} 3522