1/* $OpenBSD: if_rtwn.c,v 1.6 2015/08/28 00:03:53 deraadt Exp $ */ 2 3/*- 4 * Copyright (c) 2010 Damien Bergamini <damien.bergamini@free.fr> 5 * Copyright (c) 2015 Stefan Sperling <stsp@openbsd.org> 6 * 7 * Permission to use, copy, modify, and distribute this software for any 8 * purpose with or without fee is hereby granted, provided that the above 9 * copyright notice and this permission notice appear in all copies. 10 * 11 * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES 12 * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF 13 * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR 14 * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES 15 * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN 16 * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF 17 * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. 18 */ 19 20#include <sys/cdefs.h> 21__FBSDID("$FreeBSD: stable/11/sys/dev/rtwn/if_rtwn.c 345636 2019-03-28 09:50:25Z avos $"); 22 23/* 24 * Driver for Realtek RTL8188CE 25 */ 26 27#include <sys/param.h> 28#include <sys/sysctl.h> 29#include <sys/sockio.h> 30#include <sys/mbuf.h> 31#include <sys/kernel.h> 32#include <sys/socket.h> 33#include <sys/systm.h> 34#include <sys/malloc.h> 35#include <sys/lock.h> 36#include <sys/mutex.h> 37#include <sys/module.h> 38#include <sys/bus.h> 39#include <sys/endian.h> 40#include <sys/firmware.h> 41 42#include <machine/bus.h> 43#include <machine/resource.h> 44#include <sys/rman.h> 45 46#include <dev/pci/pcireg.h> 47#include <dev/pci/pcivar.h> 48 49#include <net/bpf.h> 50#include <net/if.h> 51#include <net/if_var.h> 52#include <net/if_arp.h> 53#include <net/ethernet.h> 54#include <net/if_dl.h> 55#include <net/if_media.h> 56#include <net/if_types.h> 57 58#include <net80211/ieee80211_var.h> 59#include <net80211/ieee80211_radiotap.h> 60#include <net80211/ieee80211_regdomain.h> 61#include <net80211/ieee80211_ratectl.h> 62 63#include <netinet/in.h> 64#include <netinet/in_systm.h> 65#include <netinet/in_var.h> 66#include <netinet/ip.h> 67#include <netinet/if_ether.h> 68 69#include <dev/rtwn/if_rtwnreg.h> 70 71#define RTWN_DEBUG 72#ifdef RTWN_DEBUG 73#define DPRINTF(x) do { if (sc->sc_debug > 0) printf x; } while (0) 74#define DPRINTFN(n, x) do { if (sc->sc_debug >= (n)) printf x; } while (0) 75#else 76#define DPRINTF(x) 77#define DPRINTFN(n, x) 78#endif 79 80/* 81 * PCI configuration space registers. 82 */ 83#define RTWN_PCI_IOBA 0x10 /* i/o mapped base */ 84#define RTWN_PCI_MMBA 0x18 /* memory mapped base */ 85 86#define RTWN_INT_ENABLE (R92C_IMR_ROK | R92C_IMR_VODOK | R92C_IMR_VIDOK | \ 87 R92C_IMR_BEDOK | R92C_IMR_BKDOK | R92C_IMR_MGNTDOK | \ 88 R92C_IMR_HIGHDOK | R92C_IMR_BDOK | R92C_IMR_RDU | \ 89 R92C_IMR_RXFOVW) 90 91struct rtwn_ident { 92 uint16_t vendor; 93 uint16_t device; 94 const char *name; 95}; 96 97 98static const struct rtwn_ident rtwn_ident_table[] = { 99 { 0x10ec, 0x8176, "Realtek RTL8188CE" }, 100 { 0, 0, NULL } 101}; 102 103 104static void rtwn_dma_map_addr(void *, bus_dma_segment_t *, int, int); 105static void rtwn_setup_rx_desc(struct rtwn_softc *, struct r92c_rx_desc *, 106 bus_addr_t, size_t, int); 107static int rtwn_alloc_rx_list(struct rtwn_softc *); 108static void rtwn_reset_rx_list(struct rtwn_softc *); 109static void rtwn_free_rx_list(struct rtwn_softc *); 110static int rtwn_alloc_tx_list(struct rtwn_softc *, int); 111static void rtwn_reset_tx_list(struct rtwn_softc *, int); 112static void rtwn_free_tx_list(struct rtwn_softc *, int); 113static struct ieee80211vap *rtwn_vap_create(struct ieee80211com *, 114 const char [IFNAMSIZ], int, enum ieee80211_opmode, int, 115 const uint8_t [IEEE80211_ADDR_LEN], 116 const uint8_t [IEEE80211_ADDR_LEN]); 117static void rtwn_vap_delete(struct ieee80211vap *); 118static void rtwn_write_1(struct rtwn_softc *, uint16_t, uint8_t); 119static void rtwn_write_2(struct rtwn_softc *, uint16_t, uint16_t); 120static void rtwn_write_4(struct rtwn_softc *, uint16_t, uint32_t); 121static uint8_t rtwn_read_1(struct rtwn_softc *, uint16_t); 122static uint16_t rtwn_read_2(struct rtwn_softc *, uint16_t); 123static uint32_t rtwn_read_4(struct rtwn_softc *, uint16_t); 124static int rtwn_fw_cmd(struct rtwn_softc *, uint8_t, const void *, int); 125static void rtwn_rf_write(struct rtwn_softc *, int, uint8_t, uint32_t); 126static uint32_t rtwn_rf_read(struct rtwn_softc *, int, uint8_t); 127static int rtwn_llt_write(struct rtwn_softc *, uint32_t, uint32_t); 128static uint8_t rtwn_efuse_read_1(struct rtwn_softc *, uint16_t); 129static void rtwn_efuse_read(struct rtwn_softc *); 130static int rtwn_read_chipid(struct rtwn_softc *); 131static void rtwn_read_rom(struct rtwn_softc *); 132static int rtwn_ra_init(struct rtwn_softc *); 133static void rtwn_tsf_sync_enable(struct rtwn_softc *); 134static void rtwn_set_led(struct rtwn_softc *, int, int); 135static void rtwn_calib_to(void *); 136static int rtwn_newstate(struct ieee80211vap *, enum ieee80211_state, int); 137static int rtwn_updateedca(struct ieee80211com *); 138static void rtwn_update_avgrssi(struct rtwn_softc *, int, int8_t); 139static int8_t rtwn_get_rssi(struct rtwn_softc *, int, void *); 140static void rtwn_rx_frame(struct rtwn_softc *, struct r92c_rx_desc *, 141 struct rtwn_rx_data *, int); 142static int rtwn_tx(struct rtwn_softc *, struct mbuf *, 143 struct ieee80211_node *); 144static void rtwn_tx_done(struct rtwn_softc *, int); 145static int rtwn_raw_xmit(struct ieee80211_node *, struct mbuf *, 146 const struct ieee80211_bpf_params *); 147static int rtwn_transmit(struct ieee80211com *, struct mbuf *); 148static void rtwn_parent(struct ieee80211com *); 149static void rtwn_start(struct rtwn_softc *sc); 150static void rtwn_watchdog(void *); 151static int rtwn_power_on(struct rtwn_softc *); 152static int rtwn_llt_init(struct rtwn_softc *); 153static void rtwn_fw_reset(struct rtwn_softc *); 154static void rtwn_fw_loadpage(struct rtwn_softc *, int, const uint8_t *, 155 int); 156static int rtwn_load_firmware(struct rtwn_softc *); 157static int rtwn_dma_init(struct rtwn_softc *); 158static void rtwn_mac_init(struct rtwn_softc *); 159static void rtwn_bb_init(struct rtwn_softc *); 160static void rtwn_rf_init(struct rtwn_softc *); 161static void rtwn_cam_init(struct rtwn_softc *); 162static void rtwn_pa_bias_init(struct rtwn_softc *); 163static void rtwn_rxfilter_init(struct rtwn_softc *); 164static void rtwn_edca_init(struct rtwn_softc *); 165static void rtwn_write_txpower(struct rtwn_softc *, int, uint16_t[]); 166static void rtwn_get_txpower(struct rtwn_softc *, int, 167 struct ieee80211_channel *, struct ieee80211_channel *, 168 uint16_t[]); 169static void rtwn_set_txpower(struct rtwn_softc *, 170 struct ieee80211_channel *, struct ieee80211_channel *); 171static void rtwn_set_rx_bssid_all(struct rtwn_softc *, int); 172static void rtwn_set_gain(struct rtwn_softc *, uint8_t); 173static void rtwn_scan_start(struct ieee80211com *); 174static void rtwn_scan_end(struct ieee80211com *); 175static void rtwn_getradiocaps(struct ieee80211com *, int, int *, 176 struct ieee80211_channel[]); 177static void rtwn_set_channel(struct ieee80211com *); 178static void rtwn_update_mcast(struct ieee80211com *); 179static void rtwn_set_chan(struct rtwn_softc *, 180 struct ieee80211_channel *, struct ieee80211_channel *); 181static int rtwn_iq_calib_chain(struct rtwn_softc *, int, uint16_t[2], 182 uint16_t[2]); 183static void rtwn_iq_calib_run(struct rtwn_softc *, int, uint16_t[2][2], 184 uint16_t[2][2]); 185static int rtwn_iq_calib_compare_results(uint16_t[2][2], uint16_t[2][2], 186 uint16_t[2][2], uint16_t[2][2], int); 187static void rtwn_iq_calib_write_results(struct rtwn_softc *, uint16_t[2], 188 uint16_t[2], int); 189static void rtwn_iq_calib(struct rtwn_softc *); 190static void rtwn_lc_calib(struct rtwn_softc *); 191static void rtwn_temp_calib(struct rtwn_softc *); 192static int rtwn_init(struct rtwn_softc *); 193static void rtwn_stop_locked(struct rtwn_softc *); 194static void rtwn_stop(struct rtwn_softc *); 195static void rtwn_intr(void *); 196 197/* Aliases. */ 198#define rtwn_bb_write rtwn_write_4 199#define rtwn_bb_read rtwn_read_4 200 201static int rtwn_probe(device_t); 202static int rtwn_attach(device_t); 203static int rtwn_detach(device_t); 204static int rtwn_shutdown(device_t); 205static int rtwn_suspend(device_t); 206static int rtwn_resume(device_t); 207 208static device_method_t rtwn_methods[] = { 209 /* Device interface */ 210 DEVMETHOD(device_probe, rtwn_probe), 211 DEVMETHOD(device_attach, rtwn_attach), 212 DEVMETHOD(device_detach, rtwn_detach), 213 DEVMETHOD(device_shutdown, rtwn_shutdown), 214 DEVMETHOD(device_suspend, rtwn_suspend), 215 DEVMETHOD(device_resume, rtwn_resume), 216 217 DEVMETHOD_END 218}; 219 220static driver_t rtwn_driver = { 221 "rtwn", 222 rtwn_methods, 223 sizeof (struct rtwn_softc) 224}; 225static devclass_t rtwn_devclass; 226 227DRIVER_MODULE(rtwn, pci, rtwn_driver, rtwn_devclass, NULL, NULL); 228 229MODULE_VERSION(rtwn, 1); 230 231MODULE_DEPEND(rtwn, pci, 1, 1, 1); 232MODULE_DEPEND(rtwn, wlan, 1, 1, 1); 233MODULE_DEPEND(rtwn, firmware, 1, 1, 1); 234 235static int 236rtwn_probe(device_t dev) 237{ 238 const struct rtwn_ident *ident; 239 240 for (ident = rtwn_ident_table; ident->name != NULL; ident++) { 241 if (pci_get_vendor(dev) == ident->vendor && 242 pci_get_device(dev) == ident->device) { 243 device_set_desc(dev, ident->name); 244 return (BUS_PROBE_DEFAULT); 245 } 246 } 247 return (ENXIO); 248} 249 250static int 251rtwn_attach(device_t dev) 252{ 253 struct rtwn_softc *sc = device_get_softc(dev); 254 struct ieee80211com *ic = &sc->sc_ic; 255 uint32_t lcsr; 256 int i, count, error, rid; 257 258 sc->sc_dev = dev; 259 sc->sc_debug = 0; 260 261 /* 262 * Get the offset of the PCI Express Capability Structure in PCI 263 * Configuration Space. 264 */ 265 error = pci_find_cap(dev, PCIY_EXPRESS, &sc->sc_cap_off); 266 if (error != 0) { 267 device_printf(dev, "PCIe capability structure not found!\n"); 268 return (error); 269 } 270 271 /* Enable bus-mastering. */ 272 pci_enable_busmaster(dev); 273 274 rid = PCIR_BAR(2); 275 sc->mem = bus_alloc_resource_any(dev, SYS_RES_MEMORY, &rid, 276 RF_ACTIVE); 277 if (sc->mem == NULL) { 278 device_printf(dev, "can't map mem space\n"); 279 return (ENOMEM); 280 } 281 sc->sc_st = rman_get_bustag(sc->mem); 282 sc->sc_sh = rman_get_bushandle(sc->mem); 283 284 /* Install interrupt handler. */ 285 count = 1; 286 rid = 0; 287 if (pci_alloc_msi(dev, &count) == 0) 288 rid = 1; 289 sc->irq = bus_alloc_resource_any(dev, SYS_RES_IRQ, &rid, RF_ACTIVE | 290 (rid != 0 ? 0 : RF_SHAREABLE)); 291 if (sc->irq == NULL) { 292 device_printf(dev, "can't map interrupt\n"); 293 return (ENXIO); 294 } 295 296 RTWN_LOCK_INIT(sc); 297 callout_init_mtx(&sc->calib_to, &sc->sc_mtx, 0); 298 callout_init_mtx(&sc->watchdog_to, &sc->sc_mtx, 0); 299 mbufq_init(&sc->sc_snd, ifqmaxlen); 300 301 error = rtwn_read_chipid(sc); 302 if (error != 0) { 303 device_printf(dev, "unsupported test chip\n"); 304 goto fail; 305 } 306 307 /* Disable PCIe Active State Power Management (ASPM). */ 308 lcsr = pci_read_config(sc->sc_dev, sc->sc_cap_off + PCIER_LINK_CTL, 4); 309 lcsr &= ~PCIEM_LINK_CTL_ASPMC; 310 pci_write_config(sc->sc_dev, sc->sc_cap_off + PCIER_LINK_CTL, lcsr, 4); 311 312 /* Allocate Tx/Rx buffers. */ 313 error = rtwn_alloc_rx_list(sc); 314 if (error != 0) { 315 device_printf(dev, "could not allocate Rx buffers\n"); 316 goto fail; 317 } 318 for (i = 0; i < RTWN_NTXQUEUES; i++) { 319 error = rtwn_alloc_tx_list(sc, i); 320 if (error != 0) { 321 device_printf(dev, "could not allocate Tx buffers\n"); 322 goto fail; 323 } 324 } 325 326 /* Determine number of Tx/Rx chains. */ 327 if (sc->chip & RTWN_CHIP_92C) { 328 sc->ntxchains = (sc->chip & RTWN_CHIP_92C_1T2R) ? 1 : 2; 329 sc->nrxchains = 2; 330 } else { 331 sc->ntxchains = 1; 332 sc->nrxchains = 1; 333 } 334 rtwn_read_rom(sc); 335 336 device_printf(sc->sc_dev, "MAC/BB RTL%s, RF 6052 %dT%dR\n", 337 (sc->chip & RTWN_CHIP_92C) ? "8192CE" : "8188CE", 338 sc->ntxchains, sc->nrxchains); 339 340 ic->ic_softc = sc; 341 ic->ic_name = device_get_nameunit(dev); 342 ic->ic_opmode = IEEE80211_M_STA; 343 ic->ic_phytype = IEEE80211_T_OFDM; /* not only, but not used */ 344 345 /* set device capabilities */ 346 ic->ic_caps = 347 IEEE80211_C_STA /* station mode */ 348 | IEEE80211_C_MONITOR /* monitor mode */ 349 | IEEE80211_C_SHPREAMBLE /* short preamble supported */ 350 | IEEE80211_C_SHSLOT /* short slot time supported */ 351 | IEEE80211_C_WPA /* capable of WPA1+WPA2 */ 352 | IEEE80211_C_BGSCAN /* capable of bg scanning */ 353 | IEEE80211_C_WME /* 802.11e */ 354 ; 355 356 /* XXX TODO: setup regdomain if R92C_CHANNEL_PLAN_BY_HW bit is set. */ 357 358 rtwn_getradiocaps(ic, IEEE80211_CHAN_MAX, &ic->ic_nchans, 359 ic->ic_channels); 360 361 ieee80211_ifattach(ic); 362 363 ic->ic_wme.wme_update = rtwn_updateedca; 364 ic->ic_update_mcast = rtwn_update_mcast; 365 ic->ic_scan_start = rtwn_scan_start; 366 ic->ic_scan_end = rtwn_scan_end; 367 ic->ic_getradiocaps = rtwn_getradiocaps; 368 ic->ic_set_channel = rtwn_set_channel; 369 ic->ic_raw_xmit = rtwn_raw_xmit; 370 ic->ic_transmit = rtwn_transmit; 371 ic->ic_parent = rtwn_parent; 372 ic->ic_vap_create = rtwn_vap_create; 373 ic->ic_vap_delete = rtwn_vap_delete; 374 375 ieee80211_radiotap_attach(ic, 376 &sc->sc_txtap.wt_ihdr, sizeof(sc->sc_txtap), 377 RTWN_TX_RADIOTAP_PRESENT, 378 &sc->sc_rxtap.wr_ihdr, sizeof(sc->sc_rxtap), 379 RTWN_RX_RADIOTAP_PRESENT); 380 381 /* 382 * Hook our interrupt after all initialization is complete. 383 */ 384 error = bus_setup_intr(dev, sc->irq, INTR_TYPE_NET | INTR_MPSAFE, 385 NULL, rtwn_intr, sc, &sc->sc_ih); 386 if (error != 0) { 387 device_printf(dev, "can't establish interrupt, error %d\n", 388 error); 389 goto fail; 390 } 391 392 if (bootverbose) 393 ieee80211_announce(ic); 394 395 return (0); 396 397fail: 398 rtwn_detach(dev); 399 return (error); 400} 401 402 403static int 404rtwn_detach(device_t dev) 405{ 406 struct rtwn_softc *sc = device_get_softc(dev); 407 int i; 408 409 if (sc->sc_ic.ic_softc != NULL) { 410 rtwn_stop(sc); 411 412 callout_drain(&sc->calib_to); 413 callout_drain(&sc->watchdog_to); 414 ieee80211_ifdetach(&sc->sc_ic); 415 mbufq_drain(&sc->sc_snd); 416 } 417 418 /* Uninstall interrupt handler. */ 419 if (sc->irq != NULL) { 420 bus_teardown_intr(dev, sc->irq, sc->sc_ih); 421 bus_release_resource(dev, SYS_RES_IRQ, rman_get_rid(sc->irq), 422 sc->irq); 423 pci_release_msi(dev); 424 } 425 426 /* Free Tx/Rx buffers. */ 427 for (i = 0; i < RTWN_NTXQUEUES; i++) 428 rtwn_free_tx_list(sc, i); 429 rtwn_free_rx_list(sc); 430 431 if (sc->mem != NULL) 432 bus_release_resource(dev, SYS_RES_MEMORY, 433 rman_get_rid(sc->mem), sc->mem); 434 435 RTWN_LOCK_DESTROY(sc); 436 return (0); 437} 438 439static int 440rtwn_shutdown(device_t dev) 441{ 442 443 return (0); 444} 445 446static int 447rtwn_suspend(device_t dev) 448{ 449 return (0); 450} 451 452static int 453rtwn_resume(device_t dev) 454{ 455 456 return (0); 457} 458 459static void 460rtwn_dma_map_addr(void *arg, bus_dma_segment_t *segs, int nsegs, int error) 461{ 462 463 if (error != 0) 464 return; 465 KASSERT(nsegs == 1, ("too many DMA segments, %d should be 1", nsegs)); 466 *(bus_addr_t *)arg = segs[0].ds_addr; 467} 468 469static void 470rtwn_setup_rx_desc(struct rtwn_softc *sc, struct r92c_rx_desc *desc, 471 bus_addr_t addr, size_t len, int idx) 472{ 473 474 memset(desc, 0, sizeof(*desc)); 475 desc->rxdw0 = htole32(SM(R92C_RXDW0_PKTLEN, len) | 476 ((idx == RTWN_RX_LIST_COUNT - 1) ? R92C_RXDW0_EOR : 0)); 477 desc->rxbufaddr = htole32(addr); 478 bus_space_barrier(sc->sc_st, sc->sc_sh, 0, sc->sc_mapsize, 479 BUS_SPACE_BARRIER_WRITE); 480 desc->rxdw0 |= htole32(R92C_RXDW0_OWN); 481} 482 483static int 484rtwn_alloc_rx_list(struct rtwn_softc *sc) 485{ 486 struct rtwn_rx_ring *rx_ring = &sc->rx_ring; 487 struct rtwn_rx_data *rx_data; 488 bus_size_t size; 489 int i, error; 490 491 /* Allocate Rx descriptors. */ 492 size = sizeof(struct r92c_rx_desc) * RTWN_RX_LIST_COUNT; 493 error = bus_dma_tag_create(bus_get_dma_tag(sc->sc_dev), 1, 0, 494 BUS_SPACE_MAXADDR_32BIT, BUS_SPACE_MAXADDR, NULL, NULL, 495 size, 1, size, 0, NULL, NULL, &rx_ring->desc_dmat); 496 if (error != 0) { 497 device_printf(sc->sc_dev, "could not create rx desc DMA tag\n"); 498 goto fail; 499 } 500 501 error = bus_dmamem_alloc(rx_ring->desc_dmat, (void **)&rx_ring->desc, 502 BUS_DMA_NOWAIT | BUS_DMA_ZERO | BUS_DMA_COHERENT, 503 &rx_ring->desc_map); 504 if (error != 0) { 505 device_printf(sc->sc_dev, "could not allocate rx desc\n"); 506 goto fail; 507 } 508 error = bus_dmamap_load(rx_ring->desc_dmat, rx_ring->desc_map, 509 rx_ring->desc, size, rtwn_dma_map_addr, &rx_ring->paddr, 0); 510 if (error != 0) { 511 device_printf(sc->sc_dev, "could not load rx desc DMA map\n"); 512 goto fail; 513 } 514 bus_dmamap_sync(rx_ring->desc_dmat, rx_ring->desc_map, 515 BUS_DMASYNC_PREWRITE); 516 517 /* Create RX buffer DMA tag. */ 518 error = bus_dma_tag_create(bus_get_dma_tag(sc->sc_dev), 1, 0, 519 BUS_SPACE_MAXADDR_32BIT, BUS_SPACE_MAXADDR, NULL, NULL, MCLBYTES, 520 1, MCLBYTES, 0, NULL, NULL, &rx_ring->data_dmat); 521 if (error != 0) { 522 device_printf(sc->sc_dev, "could not create rx buf DMA tag\n"); 523 goto fail; 524 } 525 526 /* Allocate Rx buffers. */ 527 for (i = 0; i < RTWN_RX_LIST_COUNT; i++) { 528 rx_data = &rx_ring->rx_data[i]; 529 error = bus_dmamap_create(rx_ring->data_dmat, 0, &rx_data->map); 530 if (error != 0) { 531 device_printf(sc->sc_dev, 532 "could not create rx buf DMA map\n"); 533 goto fail; 534 } 535 536 rx_data->m = m_getcl(M_NOWAIT, MT_DATA, M_PKTHDR); 537 if (rx_data->m == NULL) { 538 device_printf(sc->sc_dev, 539 "could not allocate rx mbuf\n"); 540 error = ENOMEM; 541 goto fail; 542 } 543 544 error = bus_dmamap_load(rx_ring->data_dmat, rx_data->map, 545 mtod(rx_data->m, void *), MCLBYTES, rtwn_dma_map_addr, 546 &rx_data->paddr, BUS_DMA_NOWAIT); 547 if (error != 0) { 548 device_printf(sc->sc_dev, 549 "could not load rx buf DMA map"); 550 goto fail; 551 } 552 553 rtwn_setup_rx_desc(sc, &rx_ring->desc[i], rx_data->paddr, 554 MCLBYTES, i); 555 } 556 return (0); 557 558fail: 559 rtwn_free_rx_list(sc); 560 return (error); 561} 562 563static void 564rtwn_reset_rx_list(struct rtwn_softc *sc) 565{ 566 struct rtwn_rx_ring *rx_ring = &sc->rx_ring; 567 struct rtwn_rx_data *rx_data; 568 int i; 569 570 for (i = 0; i < RTWN_RX_LIST_COUNT; i++) { 571 rx_data = &rx_ring->rx_data[i]; 572 rtwn_setup_rx_desc(sc, &rx_ring->desc[i], rx_data->paddr, 573 MCLBYTES, i); 574 } 575} 576 577static void 578rtwn_free_rx_list(struct rtwn_softc *sc) 579{ 580 struct rtwn_rx_ring *rx_ring = &sc->rx_ring; 581 struct rtwn_rx_data *rx_data; 582 int i; 583 584 if (rx_ring->desc_dmat != NULL) { 585 if (rx_ring->desc != NULL) { 586 bus_dmamap_sync(rx_ring->desc_dmat, 587 rx_ring->desc_map, 588 BUS_DMASYNC_POSTREAD | BUS_DMASYNC_POSTWRITE); 589 bus_dmamap_unload(rx_ring->desc_dmat, 590 rx_ring->desc_map); 591 bus_dmamem_free(rx_ring->desc_dmat, rx_ring->desc, 592 rx_ring->desc_map); 593 rx_ring->desc = NULL; 594 } 595 bus_dma_tag_destroy(rx_ring->desc_dmat); 596 rx_ring->desc_dmat = NULL; 597 } 598 599 for (i = 0; i < RTWN_RX_LIST_COUNT; i++) { 600 rx_data = &rx_ring->rx_data[i]; 601 602 if (rx_data->m != NULL) { 603 bus_dmamap_sync(rx_ring->data_dmat, 604 rx_data->map, BUS_DMASYNC_POSTREAD); 605 bus_dmamap_unload(rx_ring->data_dmat, rx_data->map); 606 m_freem(rx_data->m); 607 rx_data->m = NULL; 608 } 609 bus_dmamap_destroy(rx_ring->data_dmat, rx_data->map); 610 rx_data->map = NULL; 611 } 612 if (rx_ring->data_dmat != NULL) { 613 bus_dma_tag_destroy(rx_ring->data_dmat); 614 rx_ring->data_dmat = NULL; 615 } 616} 617 618static int 619rtwn_alloc_tx_list(struct rtwn_softc *sc, int qid) 620{ 621 struct rtwn_tx_ring *tx_ring = &sc->tx_ring[qid]; 622 struct rtwn_tx_data *tx_data; 623 bus_size_t size; 624 int i, error; 625 626 size = sizeof(struct r92c_tx_desc) * RTWN_TX_LIST_COUNT; 627 error = bus_dma_tag_create(bus_get_dma_tag(sc->sc_dev), PAGE_SIZE, 0, 628 BUS_SPACE_MAXADDR_32BIT, BUS_SPACE_MAXADDR, NULL, NULL, 629 size, 1, size, 0, NULL, NULL, &tx_ring->desc_dmat); 630 if (error != 0) { 631 device_printf(sc->sc_dev, "could not create tx ring DMA tag\n"); 632 goto fail; 633 } 634 635 error = bus_dmamem_alloc(tx_ring->desc_dmat, (void **)&tx_ring->desc, 636 BUS_DMA_NOWAIT | BUS_DMA_ZERO, &tx_ring->desc_map); 637 if (error != 0) { 638 device_printf(sc->sc_dev, "can't map tx ring DMA memory\n"); 639 goto fail; 640 } 641 error = bus_dmamap_load(tx_ring->desc_dmat, tx_ring->desc_map, 642 tx_ring->desc, size, rtwn_dma_map_addr, &tx_ring->paddr, 643 BUS_DMA_NOWAIT); 644 if (error != 0) { 645 device_printf(sc->sc_dev, "could not load desc DMA map\n"); 646 goto fail; 647 } 648 bus_dmamap_sync(tx_ring->desc_dmat, tx_ring->desc_map, 649 BUS_DMASYNC_PREWRITE); 650 651 error = bus_dma_tag_create(bus_get_dma_tag(sc->sc_dev), 1, 0, 652 BUS_SPACE_MAXADDR_32BIT, BUS_SPACE_MAXADDR, NULL, NULL, MCLBYTES, 653 1, MCLBYTES, 0, NULL, NULL, &tx_ring->data_dmat); 654 if (error != 0) { 655 device_printf(sc->sc_dev, "could not create tx buf DMA tag\n"); 656 goto fail; 657 } 658 659 for (i = 0; i < RTWN_TX_LIST_COUNT; i++) { 660 struct r92c_tx_desc *desc = &tx_ring->desc[i]; 661 662 /* setup tx desc */ 663 desc->nextdescaddr = htole32(tx_ring->paddr + 664 + sizeof(struct r92c_tx_desc) 665 * ((i + 1) % RTWN_TX_LIST_COUNT)); 666 tx_data = &tx_ring->tx_data[i]; 667 error = bus_dmamap_create(tx_ring->data_dmat, 0, &tx_data->map); 668 if (error != 0) { 669 device_printf(sc->sc_dev, 670 "could not create tx buf DMA map\n"); 671 goto fail; 672 } 673 tx_data->m = NULL; 674 tx_data->ni = NULL; 675 } 676 return (0); 677 678fail: 679 rtwn_free_tx_list(sc, qid); 680 return (error); 681} 682 683static void 684rtwn_reset_tx_list(struct rtwn_softc *sc, int qid) 685{ 686 struct rtwn_tx_ring *tx_ring = &sc->tx_ring[qid]; 687 int i; 688 689 for (i = 0; i < RTWN_TX_LIST_COUNT; i++) { 690 struct r92c_tx_desc *desc = &tx_ring->desc[i]; 691 struct rtwn_tx_data *tx_data = &tx_ring->tx_data[i]; 692 693 memset(desc, 0, sizeof(*desc) - 694 (sizeof(desc->reserved) + sizeof(desc->nextdescaddr64) + 695 sizeof(desc->nextdescaddr))); 696 697 if (tx_data->m != NULL) { 698 bus_dmamap_sync(tx_ring->data_dmat, tx_data->map, 699 BUS_DMASYNC_POSTWRITE); 700 bus_dmamap_unload(tx_ring->data_dmat, tx_data->map); 701 m_freem(tx_data->m); 702 tx_data->m = NULL; 703 } 704 if (tx_data->ni != NULL) { 705 ieee80211_free_node(tx_data->ni); 706 tx_data->ni = NULL; 707 } 708 } 709 710 bus_dmamap_sync(tx_ring->desc_dmat, tx_ring->desc_map, 711 BUS_DMASYNC_POSTWRITE); 712 713 sc->qfullmsk &= ~(1 << qid); 714 tx_ring->queued = 0; 715 tx_ring->cur = 0; 716} 717 718static void 719rtwn_free_tx_list(struct rtwn_softc *sc, int qid) 720{ 721 struct rtwn_tx_ring *tx_ring = &sc->tx_ring[qid]; 722 struct rtwn_tx_data *tx_data; 723 int i; 724 725 if (tx_ring->desc_dmat != NULL) { 726 if (tx_ring->desc != NULL) { 727 bus_dmamap_sync(tx_ring->desc_dmat, 728 tx_ring->desc_map, BUS_DMASYNC_POSTWRITE); 729 bus_dmamap_unload(tx_ring->desc_dmat, 730 tx_ring->desc_map); 731 bus_dmamem_free(tx_ring->desc_dmat, tx_ring->desc, 732 tx_ring->desc_map); 733 } 734 bus_dma_tag_destroy(tx_ring->desc_dmat); 735 } 736 737 for (i = 0; i < RTWN_TX_LIST_COUNT; i++) { 738 tx_data = &tx_ring->tx_data[i]; 739 740 if (tx_data->m != NULL) { 741 bus_dmamap_sync(tx_ring->data_dmat, tx_data->map, 742 BUS_DMASYNC_POSTWRITE); 743 bus_dmamap_unload(tx_ring->data_dmat, tx_data->map); 744 m_freem(tx_data->m); 745 tx_data->m = NULL; 746 } 747 } 748 if (tx_ring->data_dmat != NULL) { 749 bus_dma_tag_destroy(tx_ring->data_dmat); 750 tx_ring->data_dmat = NULL; 751 } 752 753 sc->qfullmsk &= ~(1 << qid); 754 tx_ring->queued = 0; 755 tx_ring->cur = 0; 756} 757 758 759static struct ieee80211vap * 760rtwn_vap_create(struct ieee80211com *ic, const char name[IFNAMSIZ], int unit, 761 enum ieee80211_opmode opmode, int flags, 762 const uint8_t bssid[IEEE80211_ADDR_LEN], 763 const uint8_t mac[IEEE80211_ADDR_LEN]) 764{ 765 struct rtwn_vap *rvp; 766 struct ieee80211vap *vap; 767 768 if (!TAILQ_EMPTY(&ic->ic_vaps)) 769 return (NULL); 770 771 rvp = malloc(sizeof(struct rtwn_vap), M_80211_VAP, M_WAITOK | M_ZERO); 772 vap = &rvp->vap; 773 if (ieee80211_vap_setup(ic, vap, name, unit, opmode, 774 flags | IEEE80211_CLONE_NOBEACONS, bssid) != 0) { 775 /* out of memory */ 776 free(rvp, M_80211_VAP); 777 return (NULL); 778 } 779 780 /* Override state transition machine. */ 781 rvp->newstate = vap->iv_newstate; 782 vap->iv_newstate = rtwn_newstate; 783 784 /* Complete setup. */ 785 ieee80211_vap_attach(vap, ieee80211_media_change, 786 ieee80211_media_status, mac); 787 ic->ic_opmode = opmode; 788 return (vap); 789} 790 791static void 792rtwn_vap_delete(struct ieee80211vap *vap) 793{ 794 struct rtwn_vap *rvp = RTWN_VAP(vap); 795 796 ieee80211_vap_detach(vap); 797 free(rvp, M_80211_VAP); 798} 799 800static void 801rtwn_write_1(struct rtwn_softc *sc, uint16_t addr, uint8_t val) 802{ 803 804 bus_space_write_1(sc->sc_st, sc->sc_sh, addr, val); 805} 806 807static void 808rtwn_write_2(struct rtwn_softc *sc, uint16_t addr, uint16_t val) 809{ 810 811 val = htole16(val); 812 bus_space_write_2(sc->sc_st, sc->sc_sh, addr, val); 813} 814 815static void 816rtwn_write_4(struct rtwn_softc *sc, uint16_t addr, uint32_t val) 817{ 818 819 val = htole32(val); 820 bus_space_write_4(sc->sc_st, sc->sc_sh, addr, val); 821} 822 823static uint8_t 824rtwn_read_1(struct rtwn_softc *sc, uint16_t addr) 825{ 826 827 return (bus_space_read_1(sc->sc_st, sc->sc_sh, addr)); 828} 829 830static uint16_t 831rtwn_read_2(struct rtwn_softc *sc, uint16_t addr) 832{ 833 834 return (bus_space_read_2(sc->sc_st, sc->sc_sh, addr)); 835} 836 837static uint32_t 838rtwn_read_4(struct rtwn_softc *sc, uint16_t addr) 839{ 840 841 return (bus_space_read_4(sc->sc_st, sc->sc_sh, addr)); 842} 843 844static int 845rtwn_fw_cmd(struct rtwn_softc *sc, uint8_t id, const void *buf, int len) 846{ 847 struct r92c_fw_cmd cmd; 848 int ntries; 849 850 /* Wait for current FW box to be empty. */ 851 for (ntries = 0; ntries < 100; ntries++) { 852 if (!(rtwn_read_1(sc, R92C_HMETFR) & (1 << sc->fwcur))) 853 break; 854 DELAY(1); 855 } 856 if (ntries == 100) { 857 device_printf(sc->sc_dev, 858 "could not send firmware command %d\n", id); 859 return (ETIMEDOUT); 860 } 861 memset(&cmd, 0, sizeof(cmd)); 862 cmd.id = id; 863 if (len > 3) 864 cmd.id |= R92C_CMD_FLAG_EXT; 865 KASSERT(len <= sizeof(cmd.msg), ("rtwn_fw_cmd\n")); 866 memcpy(cmd.msg, buf, len); 867 868 /* Write the first word last since that will trigger the FW. */ 869 rtwn_write_2(sc, R92C_HMEBOX_EXT(sc->fwcur), *((uint8_t *)&cmd + 4)); 870 rtwn_write_4(sc, R92C_HMEBOX(sc->fwcur), *((uint8_t *)&cmd + 0)); 871 872 sc->fwcur = (sc->fwcur + 1) % R92C_H2C_NBOX; 873 874 /* Give firmware some time for processing. */ 875 DELAY(2000); 876 877 return (0); 878} 879 880static void 881rtwn_rf_write(struct rtwn_softc *sc, int chain, uint8_t addr, uint32_t val) 882{ 883 rtwn_bb_write(sc, R92C_LSSI_PARAM(chain), 884 SM(R92C_LSSI_PARAM_ADDR, addr) | 885 SM(R92C_LSSI_PARAM_DATA, val)); 886} 887 888static uint32_t 889rtwn_rf_read(struct rtwn_softc *sc, int chain, uint8_t addr) 890{ 891 uint32_t reg[R92C_MAX_CHAINS], val; 892 893 reg[0] = rtwn_bb_read(sc, R92C_HSSI_PARAM2(0)); 894 if (chain != 0) 895 reg[chain] = rtwn_bb_read(sc, R92C_HSSI_PARAM2(chain)); 896 897 rtwn_bb_write(sc, R92C_HSSI_PARAM2(0), 898 reg[0] & ~R92C_HSSI_PARAM2_READ_EDGE); 899 DELAY(1000); 900 901 rtwn_bb_write(sc, R92C_HSSI_PARAM2(chain), 902 RW(reg[chain], R92C_HSSI_PARAM2_READ_ADDR, addr) | 903 R92C_HSSI_PARAM2_READ_EDGE); 904 DELAY(1000); 905 906 rtwn_bb_write(sc, R92C_HSSI_PARAM2(0), 907 reg[0] | R92C_HSSI_PARAM2_READ_EDGE); 908 DELAY(1000); 909 910 if (rtwn_bb_read(sc, R92C_HSSI_PARAM1(chain)) & R92C_HSSI_PARAM1_PI) 911 val = rtwn_bb_read(sc, R92C_HSPI_READBACK(chain)); 912 else 913 val = rtwn_bb_read(sc, R92C_LSSI_READBACK(chain)); 914 return (MS(val, R92C_LSSI_READBACK_DATA)); 915} 916 917static int 918rtwn_llt_write(struct rtwn_softc *sc, uint32_t addr, uint32_t data) 919{ 920 int ntries; 921 922 rtwn_write_4(sc, R92C_LLT_INIT, 923 SM(R92C_LLT_INIT_OP, R92C_LLT_INIT_OP_WRITE) | 924 SM(R92C_LLT_INIT_ADDR, addr) | 925 SM(R92C_LLT_INIT_DATA, data)); 926 /* Wait for write operation to complete. */ 927 for (ntries = 0; ntries < 20; ntries++) { 928 if (MS(rtwn_read_4(sc, R92C_LLT_INIT), R92C_LLT_INIT_OP) == 929 R92C_LLT_INIT_OP_NO_ACTIVE) 930 return (0); 931 DELAY(5); 932 } 933 return (ETIMEDOUT); 934} 935 936static uint8_t 937rtwn_efuse_read_1(struct rtwn_softc *sc, uint16_t addr) 938{ 939 uint32_t reg; 940 int ntries; 941 942 reg = rtwn_read_4(sc, R92C_EFUSE_CTRL); 943 reg = RW(reg, R92C_EFUSE_CTRL_ADDR, addr); 944 reg &= ~R92C_EFUSE_CTRL_VALID; 945 rtwn_write_4(sc, R92C_EFUSE_CTRL, reg); 946 /* Wait for read operation to complete. */ 947 for (ntries = 0; ntries < 100; ntries++) { 948 reg = rtwn_read_4(sc, R92C_EFUSE_CTRL); 949 if (reg & R92C_EFUSE_CTRL_VALID) 950 return (MS(reg, R92C_EFUSE_CTRL_DATA)); 951 DELAY(5); 952 } 953 device_printf(sc->sc_dev, 954 "could not read efuse byte at address 0x%x\n", addr); 955 return (0xff); 956} 957 958static void 959rtwn_efuse_read(struct rtwn_softc *sc) 960{ 961 uint8_t *rom = (uint8_t *)&sc->rom; 962 uint16_t addr = 0; 963 uint32_t reg; 964 uint8_t off, msk; 965 int i; 966 967 reg = rtwn_read_2(sc, R92C_SYS_ISO_CTRL); 968 if (!(reg & R92C_SYS_ISO_CTRL_PWC_EV12V)) { 969 rtwn_write_2(sc, R92C_SYS_ISO_CTRL, 970 reg | R92C_SYS_ISO_CTRL_PWC_EV12V); 971 } 972 reg = rtwn_read_2(sc, R92C_SYS_FUNC_EN); 973 if (!(reg & R92C_SYS_FUNC_EN_ELDR)) { 974 rtwn_write_2(sc, R92C_SYS_FUNC_EN, 975 reg | R92C_SYS_FUNC_EN_ELDR); 976 } 977 reg = rtwn_read_2(sc, R92C_SYS_CLKR); 978 if ((reg & (R92C_SYS_CLKR_LOADER_EN | R92C_SYS_CLKR_ANA8M)) != 979 (R92C_SYS_CLKR_LOADER_EN | R92C_SYS_CLKR_ANA8M)) { 980 rtwn_write_2(sc, R92C_SYS_CLKR, 981 reg | R92C_SYS_CLKR_LOADER_EN | R92C_SYS_CLKR_ANA8M); 982 } 983 memset(&sc->rom, 0xff, sizeof(sc->rom)); 984 while (addr < 512) { 985 reg = rtwn_efuse_read_1(sc, addr); 986 if (reg == 0xff) 987 break; 988 addr++; 989 off = reg >> 4; 990 msk = reg & 0xf; 991 for (i = 0; i < 4; i++) { 992 if (msk & (1 << i)) 993 continue; 994 rom[off * 8 + i * 2 + 0] = 995 rtwn_efuse_read_1(sc, addr); 996 addr++; 997 rom[off * 8 + i * 2 + 1] = 998 rtwn_efuse_read_1(sc, addr); 999 addr++; 1000 } 1001 } 1002#ifdef RTWN_DEBUG 1003 if (sc->sc_debug >= 2) { 1004 /* Dump ROM content. */ 1005 printf("\n"); 1006 for (i = 0; i < sizeof(sc->rom); i++) 1007 printf("%02x:", rom[i]); 1008 printf("\n"); 1009 } 1010#endif 1011} 1012 1013static int 1014rtwn_read_chipid(struct rtwn_softc *sc) 1015{ 1016 uint32_t reg; 1017 1018 reg = rtwn_read_4(sc, R92C_SYS_CFG); 1019 if (reg & R92C_SYS_CFG_TRP_VAUX_EN) 1020 /* Unsupported test chip. */ 1021 return (EIO); 1022 1023 if (reg & R92C_SYS_CFG_TYPE_92C) { 1024 sc->chip |= RTWN_CHIP_92C; 1025 /* Check if it is a castrated 8192C. */ 1026 if (MS(rtwn_read_4(sc, R92C_HPON_FSM), 1027 R92C_HPON_FSM_CHIP_BONDING_ID) == 1028 R92C_HPON_FSM_CHIP_BONDING_ID_92C_1T2R) 1029 sc->chip |= RTWN_CHIP_92C_1T2R; 1030 } 1031 if (reg & R92C_SYS_CFG_VENDOR_UMC) { 1032 sc->chip |= RTWN_CHIP_UMC; 1033 if (MS(reg, R92C_SYS_CFG_CHIP_VER_RTL) == 0) 1034 sc->chip |= RTWN_CHIP_UMC_A_CUT; 1035 } 1036 return (0); 1037} 1038 1039static void 1040rtwn_read_rom(struct rtwn_softc *sc) 1041{ 1042 struct r92c_rom *rom = &sc->rom; 1043 1044 /* Read full ROM image. */ 1045 rtwn_efuse_read(sc); 1046 1047 if (rom->id != 0x8129) 1048 device_printf(sc->sc_dev, "invalid EEPROM ID 0x%x\n", rom->id); 1049 1050 /* XXX Weird but this is what the vendor driver does. */ 1051 sc->pa_setting = rtwn_efuse_read_1(sc, 0x1fa); 1052 DPRINTF(("PA setting=0x%x\n", sc->pa_setting)); 1053 1054 sc->board_type = MS(rom->rf_opt1, R92C_ROM_RF1_BOARD_TYPE); 1055 1056 sc->regulatory = MS(rom->rf_opt1, R92C_ROM_RF1_REGULATORY); 1057 DPRINTF(("regulatory type=%d\n", sc->regulatory)); 1058 1059 IEEE80211_ADDR_COPY(sc->sc_ic.ic_macaddr, rom->macaddr); 1060} 1061 1062static __inline uint8_t 1063rate2ridx(uint8_t rate) 1064{ 1065 switch (rate) { 1066 case 12: return 4; 1067 case 18: return 5; 1068 case 24: return 6; 1069 case 36: return 7; 1070 case 48: return 8; 1071 case 72: return 9; 1072 case 96: return 10; 1073 case 108: return 11; 1074 case 2: return 0; 1075 case 4: return 1; 1076 case 11: return 2; 1077 case 22: return 3; 1078 default: return RTWN_RIDX_UNKNOWN; 1079 } 1080} 1081 1082/* 1083 * Initialize rate adaptation in firmware. 1084 */ 1085static int 1086rtwn_ra_init(struct rtwn_softc *sc) 1087{ 1088 struct ieee80211com *ic = &sc->sc_ic; 1089 struct ieee80211vap *vap = TAILQ_FIRST(&ic->ic_vaps); 1090 struct ieee80211_node *ni = ieee80211_ref_node(vap->iv_bss); 1091 struct ieee80211_rateset *rs = &ni->ni_rates; 1092 struct r92c_fw_cmd_macid_cfg cmd; 1093 uint32_t rates, basicrates; 1094 uint8_t maxrate, maxbasicrate, mode, ridx; 1095 int error, i; 1096 1097 /* Get normal and basic rates mask. */ 1098 rates = basicrates = 0; 1099 maxrate = maxbasicrate = 0; 1100 for (i = 0; i < rs->rs_nrates; i++) { 1101 /* Convert 802.11 rate to HW rate index. */ 1102 ridx = rate2ridx(IEEE80211_RV(rs->rs_rates[i])); 1103 if (ridx == RTWN_RIDX_UNKNOWN) /* Unknown rate, skip. */ 1104 continue; 1105 rates |= 1 << ridx; 1106 if (ridx > maxrate) 1107 maxrate = ridx; 1108 if (rs->rs_rates[i] & IEEE80211_RATE_BASIC) { 1109 basicrates |= 1 << ridx; 1110 if (ridx > maxbasicrate) 1111 maxbasicrate = ridx; 1112 } 1113 } 1114 if (ic->ic_curmode == IEEE80211_MODE_11B) 1115 mode = R92C_RAID_11B; 1116 else 1117 mode = R92C_RAID_11BG; 1118 DPRINTF(("mode=0x%x rates=0x%08x, basicrates=0x%08x\n", 1119 mode, rates, basicrates)); 1120 1121 /* Set rates mask for group addressed frames. */ 1122 cmd.macid = RTWN_MACID_BC | RTWN_MACID_VALID; 1123 cmd.mask = htole32(mode << 28 | basicrates); 1124 error = rtwn_fw_cmd(sc, R92C_CMD_MACID_CONFIG, &cmd, sizeof(cmd)); 1125 if (error != 0) { 1126 device_printf(sc->sc_dev, 1127 "could not add broadcast station\n"); 1128 return (error); 1129 } 1130 /* Set initial MRR rate. */ 1131 DPRINTF(("maxbasicrate=%d\n", maxbasicrate)); 1132 rtwn_write_1(sc, R92C_INIDATA_RATE_SEL(RTWN_MACID_BC), 1133 maxbasicrate); 1134 1135 /* Set rates mask for unicast frames. */ 1136 cmd.macid = RTWN_MACID_BSS | RTWN_MACID_VALID; 1137 cmd.mask = htole32(mode << 28 | rates); 1138 error = rtwn_fw_cmd(sc, R92C_CMD_MACID_CONFIG, &cmd, sizeof(cmd)); 1139 if (error != 0) { 1140 device_printf(sc->sc_dev, "could not add BSS station\n"); 1141 return (error); 1142 } 1143 /* Set initial MRR rate. */ 1144 DPRINTF(("maxrate=%d\n", maxrate)); 1145 rtwn_write_1(sc, R92C_INIDATA_RATE_SEL(RTWN_MACID_BSS), 1146 maxrate); 1147 1148 /* Configure Automatic Rate Fallback Register. */ 1149 if (ic->ic_curmode == IEEE80211_MODE_11B) { 1150 if (rates & 0x0c) 1151 rtwn_write_4(sc, R92C_ARFR(0), htole32(rates & 0x0d)); 1152 else 1153 rtwn_write_4(sc, R92C_ARFR(0), htole32(rates & 0x0f)); 1154 } else 1155 rtwn_write_4(sc, R92C_ARFR(0), htole32(rates & 0x0ff5)); 1156 1157 /* Indicate highest supported rate. */ 1158 ni->ni_txrate = rs->rs_rates[rs->rs_nrates - 1]; 1159 return (0); 1160} 1161 1162static void 1163rtwn_tsf_sync_enable(struct rtwn_softc *sc) 1164{ 1165 struct ieee80211com *ic = &sc->sc_ic; 1166 struct ieee80211vap *vap = TAILQ_FIRST(&ic->ic_vaps); 1167 struct ieee80211_node *ni = vap->iv_bss; 1168 uint64_t tsf; 1169 1170 /* Enable TSF synchronization. */ 1171 rtwn_write_1(sc, R92C_BCN_CTRL, 1172 rtwn_read_1(sc, R92C_BCN_CTRL) & ~R92C_BCN_CTRL_DIS_TSF_UDT0); 1173 1174 rtwn_write_1(sc, R92C_BCN_CTRL, 1175 rtwn_read_1(sc, R92C_BCN_CTRL) & ~R92C_BCN_CTRL_EN_BCN); 1176 1177 /* Set initial TSF. */ 1178 memcpy(&tsf, ni->ni_tstamp.data, 8); 1179 tsf = le64toh(tsf); 1180 tsf = tsf - (tsf % (vap->iv_bss->ni_intval * IEEE80211_DUR_TU)); 1181 tsf -= IEEE80211_DUR_TU; 1182 rtwn_write_4(sc, R92C_TSFTR + 0, tsf); 1183 rtwn_write_4(sc, R92C_TSFTR + 4, tsf >> 32); 1184 1185 rtwn_write_1(sc, R92C_BCN_CTRL, 1186 rtwn_read_1(sc, R92C_BCN_CTRL) | R92C_BCN_CTRL_EN_BCN); 1187} 1188 1189static void 1190rtwn_set_led(struct rtwn_softc *sc, int led, int on) 1191{ 1192 uint8_t reg; 1193 1194 if (led == RTWN_LED_LINK) { 1195 reg = rtwn_read_1(sc, R92C_LEDCFG2) & 0xf0; 1196 if (!on) 1197 reg |= R92C_LEDCFG2_DIS; 1198 else 1199 reg |= R92C_LEDCFG2_EN; 1200 rtwn_write_1(sc, R92C_LEDCFG2, reg); 1201 sc->ledlink = on; /* Save LED state. */ 1202 } 1203} 1204 1205static void 1206rtwn_calib_to(void *arg) 1207{ 1208 struct rtwn_softc *sc = arg; 1209 struct r92c_fw_cmd_rssi cmd; 1210 1211 if (sc->avg_pwdb != -1) { 1212 /* Indicate Rx signal strength to FW for rate adaptation. */ 1213 memset(&cmd, 0, sizeof(cmd)); 1214 cmd.macid = 0; /* BSS. */ 1215 cmd.pwdb = sc->avg_pwdb; 1216 DPRINTFN(3, ("sending RSSI command avg=%d\n", sc->avg_pwdb)); 1217 rtwn_fw_cmd(sc, R92C_CMD_RSSI_SETTING, &cmd, sizeof(cmd)); 1218 } 1219 1220 /* Do temperature compensation. */ 1221 rtwn_temp_calib(sc); 1222 1223 callout_reset(&sc->calib_to, hz * 2, rtwn_calib_to, sc); 1224} 1225 1226static int 1227rtwn_newstate(struct ieee80211vap *vap, enum ieee80211_state nstate, int arg) 1228{ 1229 struct rtwn_vap *rvp = RTWN_VAP(vap); 1230 struct ieee80211com *ic = vap->iv_ic; 1231 struct ieee80211_node *ni = vap->iv_bss; 1232 struct rtwn_softc *sc = ic->ic_softc; 1233 uint32_t reg; 1234 1235 IEEE80211_UNLOCK(ic); 1236 RTWN_LOCK(sc); 1237 1238 if (vap->iv_state == IEEE80211_S_RUN) { 1239 /* Stop calibration. */ 1240 callout_stop(&sc->calib_to); 1241 1242 /* Turn link LED off. */ 1243 rtwn_set_led(sc, RTWN_LED_LINK, 0); 1244 1245 /* Set media status to 'No Link'. */ 1246 reg = rtwn_read_4(sc, R92C_CR); 1247 reg = RW(reg, R92C_CR_NETTYPE, R92C_CR_NETTYPE_NOLINK); 1248 rtwn_write_4(sc, R92C_CR, reg); 1249 1250 /* Stop Rx of data frames. */ 1251 rtwn_write_2(sc, R92C_RXFLTMAP2, 0); 1252 1253 /* Rest TSF. */ 1254 rtwn_write_1(sc, R92C_DUAL_TSF_RST, 0x03); 1255 1256 /* Disable TSF synchronization. */ 1257 rtwn_write_1(sc, R92C_BCN_CTRL, 1258 rtwn_read_1(sc, R92C_BCN_CTRL) | 1259 R92C_BCN_CTRL_DIS_TSF_UDT0); 1260 1261 /* Reset EDCA parameters. */ 1262 rtwn_write_4(sc, R92C_EDCA_VO_PARAM, 0x002f3217); 1263 rtwn_write_4(sc, R92C_EDCA_VI_PARAM, 0x005e4317); 1264 rtwn_write_4(sc, R92C_EDCA_BE_PARAM, 0x00105320); 1265 rtwn_write_4(sc, R92C_EDCA_BK_PARAM, 0x0000a444); 1266 } 1267 switch (nstate) { 1268 case IEEE80211_S_INIT: 1269 /* Turn link LED off. */ 1270 rtwn_set_led(sc, RTWN_LED_LINK, 0); 1271 break; 1272 case IEEE80211_S_SCAN: 1273 /* Make link LED blink during scan. */ 1274 rtwn_set_led(sc, RTWN_LED_LINK, !sc->ledlink); 1275 1276 /* Pause AC Tx queues. */ 1277 rtwn_write_1(sc, R92C_TXPAUSE, 1278 rtwn_read_1(sc, R92C_TXPAUSE) | 0x0f); 1279 break; 1280 case IEEE80211_S_AUTH: 1281 rtwn_set_chan(sc, ic->ic_curchan, NULL); 1282 break; 1283 case IEEE80211_S_RUN: 1284 if (ic->ic_opmode == IEEE80211_M_MONITOR) { 1285 /* Enable Rx of data frames. */ 1286 rtwn_write_2(sc, R92C_RXFLTMAP2, 0xffff); 1287 1288 /* Turn link LED on. */ 1289 rtwn_set_led(sc, RTWN_LED_LINK, 1); 1290 break; 1291 } 1292 1293 /* Set media status to 'Associated'. */ 1294 reg = rtwn_read_4(sc, R92C_CR); 1295 reg = RW(reg, R92C_CR_NETTYPE, R92C_CR_NETTYPE_INFRA); 1296 rtwn_write_4(sc, R92C_CR, reg); 1297 1298 /* Set BSSID. */ 1299 rtwn_write_4(sc, R92C_BSSID + 0, le32dec(&ni->ni_bssid[0])); 1300 rtwn_write_4(sc, R92C_BSSID + 4, le16dec(&ni->ni_bssid[4])); 1301 1302 if (ic->ic_curmode == IEEE80211_MODE_11B) 1303 rtwn_write_1(sc, R92C_INIRTS_RATE_SEL, 0); 1304 else /* 802.11b/g */ 1305 rtwn_write_1(sc, R92C_INIRTS_RATE_SEL, 3); 1306 1307 /* Enable Rx of data frames. */ 1308 rtwn_write_2(sc, R92C_RXFLTMAP2, 0xffff); 1309 1310 /* Flush all AC queues. */ 1311 rtwn_write_1(sc, R92C_TXPAUSE, 0); 1312 1313 /* Set beacon interval. */ 1314 rtwn_write_2(sc, R92C_BCN_INTERVAL, ni->ni_intval); 1315 1316 /* Allow Rx from our BSSID only. */ 1317 rtwn_write_4(sc, R92C_RCR, 1318 rtwn_read_4(sc, R92C_RCR) | 1319 R92C_RCR_CBSSID_DATA | R92C_RCR_CBSSID_BCN); 1320 1321 /* Enable TSF synchronization. */ 1322 rtwn_tsf_sync_enable(sc); 1323 1324 rtwn_write_1(sc, R92C_SIFS_CCK + 1, 10); 1325 rtwn_write_1(sc, R92C_SIFS_OFDM + 1, 10); 1326 rtwn_write_1(sc, R92C_SPEC_SIFS + 1, 10); 1327 rtwn_write_1(sc, R92C_MAC_SPEC_SIFS + 1, 10); 1328 rtwn_write_1(sc, R92C_R2T_SIFS + 1, 10); 1329 rtwn_write_1(sc, R92C_T2T_SIFS + 1, 10); 1330 1331 /* Intialize rate adaptation. */ 1332 rtwn_ra_init(sc); 1333 /* Turn link LED on. */ 1334 rtwn_set_led(sc, RTWN_LED_LINK, 1); 1335 1336 sc->avg_pwdb = -1; /* Reset average RSSI. */ 1337 /* Reset temperature calibration state machine. */ 1338 sc->thcal_state = 0; 1339 sc->thcal_lctemp = 0; 1340 /* Start periodic calibration. */ 1341 callout_reset(&sc->calib_to, hz * 2, rtwn_calib_to, sc); 1342 break; 1343 default: 1344 break; 1345 } 1346 RTWN_UNLOCK(sc); 1347 IEEE80211_LOCK(ic); 1348 return (rvp->newstate(vap, nstate, arg)); 1349} 1350 1351static int 1352rtwn_updateedca(struct ieee80211com *ic) 1353{ 1354 struct rtwn_softc *sc = ic->ic_softc; 1355 const uint16_t aci2reg[WME_NUM_AC] = { 1356 R92C_EDCA_BE_PARAM, 1357 R92C_EDCA_BK_PARAM, 1358 R92C_EDCA_VI_PARAM, 1359 R92C_EDCA_VO_PARAM 1360 }; 1361 int aci, aifs, slottime; 1362 1363 IEEE80211_LOCK(ic); 1364 slottime = (ic->ic_flags & IEEE80211_F_SHSLOT) ? 9 : 20; 1365 for (aci = 0; aci < WME_NUM_AC; aci++) { 1366 const struct wmeParams *ac = 1367 &ic->ic_wme.wme_chanParams.cap_wmeParams[aci]; 1368 /* AIFS[AC] = AIFSN[AC] * aSlotTime + aSIFSTime. */ 1369 aifs = ac->wmep_aifsn * slottime + 10; 1370 rtwn_write_4(sc, aci2reg[aci], 1371 SM(R92C_EDCA_PARAM_TXOP, ac->wmep_txopLimit) | 1372 SM(R92C_EDCA_PARAM_ECWMIN, ac->wmep_logcwmin) | 1373 SM(R92C_EDCA_PARAM_ECWMAX, ac->wmep_logcwmax) | 1374 SM(R92C_EDCA_PARAM_AIFS, aifs)); 1375 } 1376 IEEE80211_UNLOCK(ic); 1377 return (0); 1378} 1379 1380static void 1381rtwn_update_avgrssi(struct rtwn_softc *sc, int rate, int8_t rssi) 1382{ 1383 int pwdb; 1384 1385 /* Convert antenna signal to percentage. */ 1386 if (rssi <= -100 || rssi >= 20) 1387 pwdb = 0; 1388 else if (rssi >= 0) 1389 pwdb = 100; 1390 else 1391 pwdb = 100 + rssi; 1392 if (RTWN_RATE_IS_CCK(rate)) { 1393 /* CCK gain is smaller than OFDM/MCS gain. */ 1394 pwdb += 6; 1395 if (pwdb > 100) 1396 pwdb = 100; 1397 if (pwdb <= 14) 1398 pwdb -= 4; 1399 else if (pwdb <= 26) 1400 pwdb -= 8; 1401 else if (pwdb <= 34) 1402 pwdb -= 6; 1403 else if (pwdb <= 42) 1404 pwdb -= 2; 1405 } 1406 if (sc->avg_pwdb == -1) /* Init. */ 1407 sc->avg_pwdb = pwdb; 1408 else if (sc->avg_pwdb < pwdb) 1409 sc->avg_pwdb = ((sc->avg_pwdb * 19 + pwdb) / 20) + 1; 1410 else 1411 sc->avg_pwdb = ((sc->avg_pwdb * 19 + pwdb) / 20); 1412 DPRINTFN(4, ("PWDB=%d EMA=%d\n", pwdb, sc->avg_pwdb)); 1413} 1414 1415static int8_t 1416rtwn_get_rssi(struct rtwn_softc *sc, int rate, void *physt) 1417{ 1418 static const int8_t cckoff[] = { 16, -12, -26, -46 }; 1419 struct r92c_rx_phystat *phy; 1420 struct r92c_rx_cck *cck; 1421 uint8_t rpt; 1422 int8_t rssi; 1423 1424 if (RTWN_RATE_IS_CCK(rate)) { 1425 cck = (struct r92c_rx_cck *)physt; 1426 if (sc->sc_flags & RTWN_FLAG_CCK_HIPWR) { 1427 rpt = (cck->agc_rpt >> 5) & 0x3; 1428 rssi = (cck->agc_rpt & 0x1f) << 1; 1429 } else { 1430 rpt = (cck->agc_rpt >> 6) & 0x3; 1431 rssi = cck->agc_rpt & 0x3e; 1432 } 1433 rssi = cckoff[rpt] - rssi; 1434 } else { /* OFDM/HT. */ 1435 phy = (struct r92c_rx_phystat *)physt; 1436 rssi = ((le32toh(phy->phydw1) >> 1) & 0x7f) - 110; 1437 } 1438 return (rssi); 1439} 1440 1441static void 1442rtwn_rx_frame(struct rtwn_softc *sc, struct r92c_rx_desc *rx_desc, 1443 struct rtwn_rx_data *rx_data, int desc_idx) 1444{ 1445 struct ieee80211com *ic = &sc->sc_ic; 1446 struct ieee80211_frame_min *wh; 1447 struct ieee80211_node *ni; 1448 struct r92c_rx_phystat *phy = NULL; 1449 uint32_t rxdw0, rxdw3; 1450 struct mbuf *m, *m1; 1451 bus_dma_segment_t segs[1]; 1452 bus_addr_t physaddr; 1453 uint8_t rate; 1454 int8_t rssi = 0, nf; 1455 int infosz, nsegs, pktlen, shift, error; 1456 1457 rxdw0 = le32toh(rx_desc->rxdw0); 1458 rxdw3 = le32toh(rx_desc->rxdw3); 1459 1460 if (__predict_false(rxdw0 & (R92C_RXDW0_CRCERR | R92C_RXDW0_ICVERR))) { 1461 /* 1462 * This should not happen since we setup our Rx filter 1463 * to not receive these frames. 1464 */ 1465 counter_u64_add(ic->ic_ierrors, 1); 1466 return; 1467 } 1468 1469 pktlen = MS(rxdw0, R92C_RXDW0_PKTLEN); 1470 if (__predict_false(pktlen < sizeof(struct ieee80211_frame_ack) || 1471 pktlen > MCLBYTES)) { 1472 counter_u64_add(ic->ic_ierrors, 1); 1473 return; 1474 } 1475 1476 rate = MS(rxdw3, R92C_RXDW3_RATE); 1477 infosz = MS(rxdw0, R92C_RXDW0_INFOSZ) * 8; 1478 if (infosz > sizeof(struct r92c_rx_phystat)) 1479 infosz = sizeof(struct r92c_rx_phystat); 1480 shift = MS(rxdw0, R92C_RXDW0_SHIFT); 1481 1482 /* Get RSSI from PHY status descriptor if present. */ 1483 if (infosz != 0 && (rxdw0 & R92C_RXDW0_PHYST)) { 1484 phy = mtod(rx_data->m, struct r92c_rx_phystat *); 1485 rssi = rtwn_get_rssi(sc, rate, phy); 1486 /* Update our average RSSI. */ 1487 rtwn_update_avgrssi(sc, rate, rssi); 1488 } 1489 1490 DPRINTFN(5, ("Rx frame len=%d rate=%d infosz=%d shift=%d rssi=%d\n", 1491 pktlen, rate, infosz, shift, rssi)); 1492 1493 m1 = m_getcl(M_NOWAIT, MT_DATA, M_PKTHDR); 1494 if (m1 == NULL) { 1495 counter_u64_add(ic->ic_ierrors, 1); 1496 return; 1497 } 1498 bus_dmamap_unload(sc->rx_ring.data_dmat, rx_data->map); 1499 1500 error = bus_dmamap_load(sc->rx_ring.data_dmat, rx_data->map, 1501 mtod(m1, void *), MCLBYTES, rtwn_dma_map_addr, 1502 &physaddr, 0); 1503 if (error != 0) { 1504 m_freem(m1); 1505 1506 if (bus_dmamap_load_mbuf_sg(sc->rx_ring.data_dmat, 1507 rx_data->map, rx_data->m, segs, &nsegs, 0)) 1508 panic("%s: could not load old RX mbuf", 1509 device_get_name(sc->sc_dev)); 1510 1511 /* Physical address may have changed. */ 1512 rtwn_setup_rx_desc(sc, rx_desc, physaddr, MCLBYTES, desc_idx); 1513 counter_u64_add(ic->ic_ierrors, 1); 1514 return; 1515 } 1516 1517 /* Finalize mbuf. */ 1518 m = rx_data->m; 1519 rx_data->m = m1; 1520 m->m_pkthdr.len = m->m_len = pktlen + infosz + shift; 1521 1522 /* Update RX descriptor. */ 1523 rtwn_setup_rx_desc(sc, rx_desc, physaddr, MCLBYTES, desc_idx); 1524 1525 /* Get ieee80211 frame header. */ 1526 if (rxdw0 & R92C_RXDW0_PHYST) 1527 m_adj(m, infosz + shift); 1528 else 1529 m_adj(m, shift); 1530 1531 nf = -95; 1532 if (ieee80211_radiotap_active(ic)) { 1533 struct rtwn_rx_radiotap_header *tap = &sc->sc_rxtap; 1534 1535 tap->wr_flags = 0; 1536 if (!(rxdw3 & R92C_RXDW3_HT)) { 1537 tap->wr_rate = ridx2rate[rate]; 1538 } else if (rate >= 12) { /* MCS0~15. */ 1539 /* Bit 7 set means HT MCS instead of rate. */ 1540 tap->wr_rate = 0x80 | (rate - 12); 1541 } 1542 tap->wr_dbm_antsignal = rssi; 1543 } 1544 1545 RTWN_UNLOCK(sc); 1546 wh = mtod(m, struct ieee80211_frame_min *); 1547 if (m->m_len >= sizeof(*wh)) 1548 ni = ieee80211_find_rxnode(ic, wh); 1549 else 1550 ni = NULL; 1551 1552 /* Send the frame to the 802.11 layer. */ 1553 if (ni != NULL) { 1554 (void)ieee80211_input(ni, m, rssi - nf, nf); 1555 /* Node is no longer needed. */ 1556 ieee80211_free_node(ni); 1557 } else 1558 (void)ieee80211_input_all(ic, m, rssi - nf, nf); 1559 1560 RTWN_LOCK(sc); 1561} 1562 1563static int 1564rtwn_tx(struct rtwn_softc *sc, struct mbuf *m, struct ieee80211_node *ni) 1565{ 1566 struct ieee80211com *ic = &sc->sc_ic; 1567 struct ieee80211vap *vap = ni->ni_vap; 1568 struct ieee80211_frame *wh; 1569 struct ieee80211_key *k = NULL; 1570 struct rtwn_tx_ring *tx_ring; 1571 struct rtwn_tx_data *data; 1572 struct r92c_tx_desc *txd; 1573 bus_dma_segment_t segs[1]; 1574 uint16_t qos; 1575 uint8_t raid, type, tid, qid; 1576 int nsegs, error; 1577 1578 wh = mtod(m, struct ieee80211_frame *); 1579 type = wh->i_fc[0] & IEEE80211_FC0_TYPE_MASK; 1580 1581 /* Encrypt the frame if need be. */ 1582 if (wh->i_fc[1] & IEEE80211_FC1_PROTECTED) { 1583 k = ieee80211_crypto_encap(ni, m); 1584 if (k == NULL) { 1585 m_freem(m); 1586 return (ENOBUFS); 1587 } 1588 /* 802.11 header may have moved. */ 1589 wh = mtod(m, struct ieee80211_frame *); 1590 } 1591 1592 if (IEEE80211_QOS_HAS_SEQ(wh)) { 1593 qos = ((const struct ieee80211_qosframe *)wh)->i_qos[0]; 1594 tid = qos & IEEE80211_QOS_TID; 1595 } else { 1596 qos = 0; 1597 tid = 0; 1598 } 1599 1600 switch (type) { 1601 case IEEE80211_FC0_TYPE_CTL: 1602 case IEEE80211_FC0_TYPE_MGT: 1603 qid = RTWN_VO_QUEUE; 1604 break; 1605 default: 1606 qid = M_WME_GETAC(m); 1607 break; 1608 } 1609 1610 /* Grab a Tx buffer from the ring. */ 1611 tx_ring = &sc->tx_ring[qid]; 1612 data = &tx_ring->tx_data[tx_ring->cur]; 1613 if (data->m != NULL) { 1614 m_freem(m); 1615 return (ENOBUFS); 1616 } 1617 1618 /* Fill Tx descriptor. */ 1619 txd = &tx_ring->desc[tx_ring->cur]; 1620 if (htole32(txd->txdw0) & R92C_RXDW0_OWN) { 1621 m_freem(m); 1622 return (ENOBUFS); 1623 } 1624 txd->txdw0 = htole32( 1625 SM(R92C_TXDW0_PKTLEN, m->m_pkthdr.len) | 1626 SM(R92C_TXDW0_OFFSET, sizeof(*txd)) | 1627 R92C_TXDW0_FSG | R92C_TXDW0_LSG); 1628 if (IEEE80211_IS_MULTICAST(wh->i_addr1)) 1629 txd->txdw0 |= htole32(R92C_TXDW0_BMCAST); 1630 1631 txd->txdw1 = 0; 1632 txd->txdw4 = 0; 1633 txd->txdw5 = 0; 1634 1635 /* XXX TODO: rate control; implement low-rate for EAPOL */ 1636 if (!IEEE80211_IS_MULTICAST(wh->i_addr1) && 1637 type == IEEE80211_FC0_TYPE_DATA) { 1638 if (ic->ic_curmode == IEEE80211_MODE_11B) 1639 raid = R92C_RAID_11B; 1640 else 1641 raid = R92C_RAID_11BG; 1642 txd->txdw1 |= htole32( 1643 SM(R92C_TXDW1_MACID, RTWN_MACID_BSS) | 1644 SM(R92C_TXDW1_QSEL, R92C_TXDW1_QSEL_BE) | 1645 SM(R92C_TXDW1_RAID, raid) | 1646 R92C_TXDW1_AGGBK); 1647 1648 if (ic->ic_flags & IEEE80211_F_USEPROT) { 1649 if (ic->ic_protmode == IEEE80211_PROT_CTSONLY) { 1650 txd->txdw4 |= htole32(R92C_TXDW4_CTS2SELF | 1651 R92C_TXDW4_HWRTSEN); 1652 } else if (ic->ic_protmode == IEEE80211_PROT_RTSCTS) { 1653 txd->txdw4 |= htole32(R92C_TXDW4_RTSEN | 1654 R92C_TXDW4_HWRTSEN); 1655 } 1656 } 1657 1658 /* XXX TODO: implement rate control */ 1659 1660 /* Send RTS at OFDM24. */ 1661 txd->txdw4 |= htole32(SM(R92C_TXDW4_RTSRATE, 1662 RTWN_RIDX_OFDM24)); 1663 txd->txdw5 |= htole32(SM(R92C_TXDW5_RTSRATE_FBLIMIT, 0xf)); 1664 /* Send data at OFDM54. */ 1665 txd->txdw5 |= htole32(SM(R92C_TXDW5_DATARATE, 1666 RTWN_RIDX_OFDM54)); 1667 txd->txdw5 |= htole32(SM(R92C_TXDW5_DATARATE_FBLIMIT, 0x1f)); 1668 1669 } else { 1670 txd->txdw1 |= htole32( 1671 SM(R92C_TXDW1_MACID, 0) | 1672 SM(R92C_TXDW1_QSEL, R92C_TXDW1_QSEL_MGNT) | 1673 SM(R92C_TXDW1_RAID, R92C_RAID_11B)); 1674 1675 /* Force CCK1. */ 1676 txd->txdw4 |= htole32(R92C_TXDW4_DRVRATE); 1677 txd->txdw5 |= htole32(SM(R92C_TXDW5_DATARATE, RTWN_RIDX_CCK1)); 1678 } 1679 /* Set sequence number (already little endian). */ 1680 txd->txdseq = htole16(M_SEQNO_GET(m) % IEEE80211_SEQ_RANGE); 1681 1682 if (!qos) { 1683 /* Use HW sequence numbering for non-QoS frames. */ 1684 txd->txdw4 |= htole32(R92C_TXDW4_HWSEQ); 1685 txd->txdseq |= htole16(0x8000); 1686 } else 1687 txd->txdw4 |= htole32(R92C_TXDW4_QOS); 1688 1689 error = bus_dmamap_load_mbuf_sg(tx_ring->data_dmat, data->map, m, segs, 1690 &nsegs, BUS_DMA_NOWAIT); 1691 if (error != 0 && error != EFBIG) { 1692 device_printf(sc->sc_dev, "can't map mbuf (error %d)\n", error); 1693 m_freem(m); 1694 return (error); 1695 } 1696 if (error != 0) { 1697 struct mbuf *mnew; 1698 1699 mnew = m_defrag(m, M_NOWAIT); 1700 if (mnew == NULL) { 1701 device_printf(sc->sc_dev, 1702 "can't defragment mbuf\n"); 1703 m_freem(m); 1704 return (ENOBUFS); 1705 } 1706 m = mnew; 1707 1708 error = bus_dmamap_load_mbuf_sg(tx_ring->data_dmat, data->map, 1709 m, segs, &nsegs, BUS_DMA_NOWAIT); 1710 if (error != 0) { 1711 device_printf(sc->sc_dev, 1712 "can't map mbuf (error %d)\n", error); 1713 m_freem(m); 1714 return (error); 1715 } 1716 } 1717 1718 txd->txbufaddr = htole32(segs[0].ds_addr); 1719 txd->txbufsize = htole16(m->m_pkthdr.len); 1720 bus_space_barrier(sc->sc_st, sc->sc_sh, 0, sc->sc_mapsize, 1721 BUS_SPACE_BARRIER_WRITE); 1722 txd->txdw0 |= htole32(R92C_TXDW0_OWN); 1723 1724 bus_dmamap_sync(tx_ring->desc_dmat, tx_ring->desc_map, 1725 BUS_DMASYNC_POSTWRITE); 1726 bus_dmamap_sync(tx_ring->data_dmat, data->map, BUS_DMASYNC_POSTWRITE); 1727 1728 data->m = m; 1729 data->ni = ni; 1730 1731 if (ieee80211_radiotap_active_vap(vap)) { 1732 struct rtwn_tx_radiotap_header *tap = &sc->sc_txtap; 1733 1734 tap->wt_flags = 0; 1735 1736 ieee80211_radiotap_tx(vap, m); 1737 } 1738 1739 tx_ring->cur = (tx_ring->cur + 1) % RTWN_TX_LIST_COUNT; 1740 tx_ring->queued++; 1741 1742 if (tx_ring->queued >= (RTWN_TX_LIST_COUNT - 1)) 1743 sc->qfullmsk |= (1 << qid); 1744 1745 /* Kick TX. */ 1746 rtwn_write_2(sc, R92C_PCIE_CTRL_REG, (1 << qid)); 1747 return (0); 1748} 1749 1750static void 1751rtwn_tx_done(struct rtwn_softc *sc, int qid) 1752{ 1753 struct rtwn_tx_ring *tx_ring = &sc->tx_ring[qid]; 1754 struct rtwn_tx_data *tx_data; 1755 struct r92c_tx_desc *tx_desc; 1756 int i; 1757 1758 bus_dmamap_sync(tx_ring->desc_dmat, tx_ring->desc_map, 1759 BUS_DMASYNC_POSTREAD); 1760 1761 for (i = 0; i < RTWN_TX_LIST_COUNT; i++) { 1762 tx_data = &tx_ring->tx_data[i]; 1763 if (tx_data->m == NULL) 1764 continue; 1765 1766 tx_desc = &tx_ring->desc[i]; 1767 if (le32toh(tx_desc->txdw0) & R92C_TXDW0_OWN) 1768 continue; 1769 1770 /* Unmap and free mbuf. */ 1771 bus_dmamap_sync(tx_ring->data_dmat, tx_data->map, 1772 BUS_DMASYNC_POSTWRITE); 1773 bus_dmamap_unload(tx_ring->data_dmat, tx_data->map); 1774 1775 /* 1776 * XXX TODO: figure out whether the transmit succeeded or not. 1777 * .. and then notify rate control. 1778 */ 1779 ieee80211_tx_complete(tx_data->ni, tx_data->m, 0); 1780 tx_data->ni = NULL; 1781 tx_data->m = NULL; 1782 1783 if (--tx_ring->queued) 1784 sc->sc_tx_timer = 5; 1785 else 1786 sc->sc_tx_timer = 0; 1787 } 1788 1789 if (tx_ring->queued < (RTWN_TX_LIST_COUNT - 1)) 1790 sc->qfullmsk &= ~(1 << qid); 1791 rtwn_start(sc); 1792} 1793 1794static int 1795rtwn_raw_xmit(struct ieee80211_node *ni, struct mbuf *m, 1796 const struct ieee80211_bpf_params *params) 1797{ 1798 struct ieee80211com *ic = ni->ni_ic; 1799 struct rtwn_softc *sc = ic->ic_softc; 1800 1801 RTWN_LOCK(sc); 1802 1803 /* Prevent management frames from being sent if we're not ready. */ 1804 if (!(sc->sc_flags & RTWN_RUNNING)) { 1805 RTWN_UNLOCK(sc); 1806 m_freem(m); 1807 return (ENETDOWN); 1808 } 1809 1810 if (rtwn_tx(sc, m, ni) != 0) { 1811 RTWN_UNLOCK(sc); 1812 return (EIO); 1813 } 1814 sc->sc_tx_timer = 5; 1815 RTWN_UNLOCK(sc); 1816 return (0); 1817} 1818 1819static int 1820rtwn_transmit(struct ieee80211com *ic, struct mbuf *m) 1821{ 1822 struct rtwn_softc *sc = ic->ic_softc; 1823 int error; 1824 1825 RTWN_LOCK(sc); 1826 if ((sc->sc_flags & RTWN_RUNNING) == 0) { 1827 RTWN_UNLOCK(sc); 1828 return (ENXIO); 1829 } 1830 error = mbufq_enqueue(&sc->sc_snd, m); 1831 if (error) { 1832 RTWN_UNLOCK(sc); 1833 return (error); 1834 } 1835 rtwn_start(sc); 1836 RTWN_UNLOCK(sc); 1837 return (0); 1838} 1839 1840static void 1841rtwn_parent(struct ieee80211com *ic) 1842{ 1843 struct rtwn_softc *sc = ic->ic_softc; 1844 struct ieee80211vap *vap = TAILQ_FIRST(&ic->ic_vaps); 1845 1846 if (ic->ic_nrunning > 0) { 1847 if (rtwn_init(sc) == 0) 1848 ieee80211_start_all(ic); 1849 else 1850 ieee80211_stop(vap); 1851 } else 1852 rtwn_stop(sc); 1853} 1854 1855static void 1856rtwn_start(struct rtwn_softc *sc) 1857{ 1858 struct ieee80211_node *ni; 1859 struct mbuf *m; 1860 1861 RTWN_LOCK_ASSERT(sc); 1862 1863 if ((sc->sc_flags & RTWN_RUNNING) == 0) 1864 return; 1865 1866 while (sc->qfullmsk == 0 && (m = mbufq_dequeue(&sc->sc_snd)) != NULL) { 1867 ni = (struct ieee80211_node *)m->m_pkthdr.rcvif; 1868 if (rtwn_tx(sc, m, ni) != 0) { 1869 if_inc_counter(ni->ni_vap->iv_ifp, 1870 IFCOUNTER_OERRORS, 1); 1871 ieee80211_free_node(ni); 1872 continue; 1873 } 1874 sc->sc_tx_timer = 5; 1875 } 1876} 1877 1878static void 1879rtwn_watchdog(void *arg) 1880{ 1881 struct rtwn_softc *sc = arg; 1882 struct ieee80211com *ic = &sc->sc_ic; 1883 1884 RTWN_LOCK_ASSERT(sc); 1885 1886 KASSERT(sc->sc_flags & RTWN_RUNNING, ("not running")); 1887 1888 if (sc->sc_tx_timer != 0 && --sc->sc_tx_timer == 0) { 1889 ic_printf(ic, "device timeout\n"); 1890 ieee80211_restart_all(ic); 1891 return; 1892 } 1893 callout_reset(&sc->watchdog_to, hz, rtwn_watchdog, sc); 1894} 1895 1896static int 1897rtwn_power_on(struct rtwn_softc *sc) 1898{ 1899 uint32_t reg; 1900 int ntries; 1901 1902 /* Wait for autoload done bit. */ 1903 for (ntries = 0; ntries < 1000; ntries++) { 1904 if (rtwn_read_1(sc, R92C_APS_FSMCO) & R92C_APS_FSMCO_PFM_ALDN) 1905 break; 1906 DELAY(5); 1907 } 1908 if (ntries == 1000) { 1909 device_printf(sc->sc_dev, 1910 "timeout waiting for chip autoload\n"); 1911 return (ETIMEDOUT); 1912 } 1913 1914 /* Unlock ISO/CLK/Power control register. */ 1915 rtwn_write_1(sc, R92C_RSV_CTRL, 0); 1916 1917 /* TODO: check if we need this for 8188CE */ 1918 if (sc->board_type != R92C_BOARD_TYPE_DONGLE) { 1919 /* bt coex */ 1920 reg = rtwn_read_4(sc, R92C_APS_FSMCO); 1921 reg |= (R92C_APS_FSMCO_SOP_ABG | 1922 R92C_APS_FSMCO_SOP_AMB | 1923 R92C_APS_FSMCO_XOP_BTCK); 1924 rtwn_write_4(sc, R92C_APS_FSMCO, reg); 1925 } 1926 1927 /* Move SPS into PWM mode. */ 1928 rtwn_write_1(sc, R92C_SPS0_CTRL, 0x2b); 1929 1930 /* Set low byte to 0x0f, leave others unchanged. */ 1931 rtwn_write_4(sc, R92C_AFE_XTAL_CTRL, 1932 (rtwn_read_4(sc, R92C_AFE_XTAL_CTRL) & 0xffffff00) | 0x0f); 1933 1934 /* TODO: check if we need this for 8188CE */ 1935 if (sc->board_type != R92C_BOARD_TYPE_DONGLE) { 1936 /* bt coex */ 1937 reg = rtwn_read_4(sc, R92C_AFE_XTAL_CTRL); 1938 reg &= (~0x00024800); /* XXX magic from linux */ 1939 rtwn_write_4(sc, R92C_AFE_XTAL_CTRL, reg); 1940 } 1941 1942 rtwn_write_2(sc, R92C_SYS_ISO_CTRL, 1943 (rtwn_read_2(sc, R92C_SYS_ISO_CTRL) & 0xff) | 1944 R92C_SYS_ISO_CTRL_PWC_EV12V | R92C_SYS_ISO_CTRL_DIOR); 1945 DELAY(200); 1946 1947 /* TODO: linux does additional btcoex stuff here */ 1948 1949 /* Auto enable WLAN. */ 1950 rtwn_write_2(sc, R92C_APS_FSMCO, 1951 rtwn_read_2(sc, R92C_APS_FSMCO) | R92C_APS_FSMCO_APFM_ONMAC); 1952 for (ntries = 0; ntries < 1000; ntries++) { 1953 if (!(rtwn_read_2(sc, R92C_APS_FSMCO) & 1954 R92C_APS_FSMCO_APFM_ONMAC)) 1955 break; 1956 DELAY(5); 1957 } 1958 if (ntries == 1000) { 1959 device_printf(sc->sc_dev, "timeout waiting for MAC auto ON\n"); 1960 return (ETIMEDOUT); 1961 } 1962 1963 /* Enable radio, GPIO and LED functions. */ 1964 rtwn_write_2(sc, R92C_APS_FSMCO, 1965 R92C_APS_FSMCO_AFSM_PCIE | 1966 R92C_APS_FSMCO_PDN_EN | 1967 R92C_APS_FSMCO_PFM_ALDN); 1968 /* Release RF digital isolation. */ 1969 rtwn_write_2(sc, R92C_SYS_ISO_CTRL, 1970 rtwn_read_2(sc, R92C_SYS_ISO_CTRL) & ~R92C_SYS_ISO_CTRL_DIOR); 1971 1972 if (sc->chip & RTWN_CHIP_92C) 1973 rtwn_write_1(sc, R92C_PCIE_CTRL_REG + 3, 0x77); 1974 else 1975 rtwn_write_1(sc, R92C_PCIE_CTRL_REG + 3, 0x22); 1976 1977 rtwn_write_4(sc, R92C_INT_MIG, 0); 1978 1979 if (sc->board_type != R92C_BOARD_TYPE_DONGLE) { 1980 /* bt coex */ 1981 reg = rtwn_read_4(sc, R92C_AFE_XTAL_CTRL + 2); 1982 reg &= 0xfd; /* XXX magic from linux */ 1983 rtwn_write_4(sc, R92C_AFE_XTAL_CTRL + 2, reg); 1984 } 1985 1986 rtwn_write_1(sc, R92C_GPIO_MUXCFG, 1987 rtwn_read_1(sc, R92C_GPIO_MUXCFG) & ~R92C_GPIO_MUXCFG_RFKILL); 1988 1989 reg = rtwn_read_1(sc, R92C_GPIO_IO_SEL); 1990 if (!(reg & R92C_GPIO_IO_SEL_RFKILL)) { 1991 device_printf(sc->sc_dev, 1992 "radio is disabled by hardware switch\n"); 1993 return (EPERM); 1994 } 1995 1996 /* Initialize MAC. */ 1997 reg = rtwn_read_1(sc, R92C_APSD_CTRL); 1998 rtwn_write_1(sc, R92C_APSD_CTRL, 1999 rtwn_read_1(sc, R92C_APSD_CTRL) & ~R92C_APSD_CTRL_OFF); 2000 for (ntries = 0; ntries < 200; ntries++) { 2001 if (!(rtwn_read_1(sc, R92C_APSD_CTRL) & 2002 R92C_APSD_CTRL_OFF_STATUS)) 2003 break; 2004 DELAY(500); 2005 } 2006 if (ntries == 200) { 2007 device_printf(sc->sc_dev, 2008 "timeout waiting for MAC initialization\n"); 2009 return (ETIMEDOUT); 2010 } 2011 2012 /* Enable MAC DMA/WMAC/SCHEDULE/SEC blocks. */ 2013 reg = rtwn_read_2(sc, R92C_CR); 2014 reg |= R92C_CR_HCI_TXDMA_EN | R92C_CR_HCI_RXDMA_EN | 2015 R92C_CR_TXDMA_EN | R92C_CR_RXDMA_EN | R92C_CR_PROTOCOL_EN | 2016 R92C_CR_SCHEDULE_EN | R92C_CR_MACTXEN | R92C_CR_MACRXEN | 2017 R92C_CR_ENSEC; 2018 rtwn_write_2(sc, R92C_CR, reg); 2019 2020 rtwn_write_1(sc, 0xfe10, 0x19); 2021 2022 return (0); 2023} 2024 2025static int 2026rtwn_llt_init(struct rtwn_softc *sc) 2027{ 2028 int i, error; 2029 2030 /* Reserve pages [0; R92C_TX_PAGE_COUNT]. */ 2031 for (i = 0; i < R92C_TX_PAGE_COUNT; i++) { 2032 if ((error = rtwn_llt_write(sc, i, i + 1)) != 0) 2033 return (error); 2034 } 2035 /* NB: 0xff indicates end-of-list. */ 2036 if ((error = rtwn_llt_write(sc, i, 0xff)) != 0) 2037 return (error); 2038 /* 2039 * Use pages [R92C_TX_PAGE_COUNT + 1; R92C_TXPKTBUF_COUNT - 1] 2040 * as ring buffer. 2041 */ 2042 for (++i; i < R92C_TXPKTBUF_COUNT - 1; i++) { 2043 if ((error = rtwn_llt_write(sc, i, i + 1)) != 0) 2044 return (error); 2045 } 2046 /* Make the last page point to the beginning of the ring buffer. */ 2047 error = rtwn_llt_write(sc, i, R92C_TX_PAGE_COUNT + 1); 2048 return (error); 2049} 2050 2051static void 2052rtwn_fw_reset(struct rtwn_softc *sc) 2053{ 2054 uint16_t reg; 2055 int ntries; 2056 2057 /* Tell 8051 to reset itself. */ 2058 rtwn_write_1(sc, R92C_HMETFR + 3, 0x20); 2059 2060 /* Wait until 8051 resets by itself. */ 2061 for (ntries = 0; ntries < 100; ntries++) { 2062 reg = rtwn_read_2(sc, R92C_SYS_FUNC_EN); 2063 if (!(reg & R92C_SYS_FUNC_EN_CPUEN)) 2064 goto sleep; 2065 DELAY(50); 2066 } 2067 /* Force 8051 reset. */ 2068 rtwn_write_2(sc, R92C_SYS_FUNC_EN, reg & ~R92C_SYS_FUNC_EN_CPUEN); 2069sleep: 2070 /* 2071 * We must sleep for one second to let the firmware settle. 2072 * Accessing registers too early will hang the whole system. 2073 */ 2074 if (msleep(®, &sc->sc_mtx, 0, "rtwnrst", hz)) { 2075 device_printf(sc->sc_dev, "timeout waiting for firmware " 2076 "initialization to complete\n"); 2077 } 2078} 2079 2080static void 2081rtwn_fw_loadpage(struct rtwn_softc *sc, int page, const uint8_t *buf, int len) 2082{ 2083 uint32_t reg; 2084 int off, mlen, i; 2085 2086 reg = rtwn_read_4(sc, R92C_MCUFWDL); 2087 reg = RW(reg, R92C_MCUFWDL_PAGE, page); 2088 rtwn_write_4(sc, R92C_MCUFWDL, reg); 2089 2090 DELAY(5); 2091 2092 off = R92C_FW_START_ADDR; 2093 while (len > 0) { 2094 if (len > 196) 2095 mlen = 196; 2096 else if (len > 4) 2097 mlen = 4; 2098 else 2099 mlen = 1; 2100 for (i = 0; i < mlen; i++) 2101 rtwn_write_1(sc, off++, buf[i]); 2102 buf += mlen; 2103 len -= mlen; 2104 } 2105} 2106 2107static int 2108rtwn_load_firmware(struct rtwn_softc *sc) 2109{ 2110 const struct firmware *fw; 2111 const struct r92c_fw_hdr *hdr; 2112 const char *name; 2113 const u_char *ptr; 2114 size_t len; 2115 uint32_t reg; 2116 int mlen, ntries, page, error = 0; 2117 2118 /* Read firmware image from the filesystem. */ 2119 if ((sc->chip & (RTWN_CHIP_UMC_A_CUT | RTWN_CHIP_92C)) == 2120 RTWN_CHIP_UMC_A_CUT) 2121 name = "rtwn-rtl8192cfwU"; 2122 else 2123 name = "rtwn-rtl8192cfwU_B"; 2124 RTWN_UNLOCK(sc); 2125 fw = firmware_get(name); 2126 RTWN_LOCK(sc); 2127 if (fw == NULL) { 2128 device_printf(sc->sc_dev, 2129 "could not read firmware %s\n", name); 2130 return (ENOENT); 2131 } 2132 len = fw->datasize; 2133 if (len < sizeof(*hdr)) { 2134 device_printf(sc->sc_dev, "firmware too short\n"); 2135 error = EINVAL; 2136 goto fail; 2137 } 2138 ptr = fw->data; 2139 hdr = (const struct r92c_fw_hdr *)ptr; 2140 /* Check if there is a valid FW header and skip it. */ 2141 if ((le16toh(hdr->signature) >> 4) == 0x88c || 2142 (le16toh(hdr->signature) >> 4) == 0x92c) { 2143 DPRINTF(("FW V%d.%d %02d-%02d %02d:%02d\n", 2144 le16toh(hdr->version), le16toh(hdr->subversion), 2145 hdr->month, hdr->date, hdr->hour, hdr->minute)); 2146 ptr += sizeof(*hdr); 2147 len -= sizeof(*hdr); 2148 } 2149 2150 if (rtwn_read_1(sc, R92C_MCUFWDL) & R92C_MCUFWDL_RAM_DL_SEL) 2151 rtwn_fw_reset(sc); 2152 2153 /* Enable FW download. */ 2154 rtwn_write_2(sc, R92C_SYS_FUNC_EN, 2155 rtwn_read_2(sc, R92C_SYS_FUNC_EN) | 2156 R92C_SYS_FUNC_EN_CPUEN); 2157 rtwn_write_1(sc, R92C_MCUFWDL, 2158 rtwn_read_1(sc, R92C_MCUFWDL) | R92C_MCUFWDL_EN); 2159 rtwn_write_1(sc, R92C_MCUFWDL + 2, 2160 rtwn_read_1(sc, R92C_MCUFWDL + 2) & ~0x08); 2161 2162 /* Reset the FWDL checksum. */ 2163 rtwn_write_1(sc, R92C_MCUFWDL, 2164 rtwn_read_1(sc, R92C_MCUFWDL) | R92C_MCUFWDL_CHKSUM_RPT); 2165 2166 for (page = 0; len > 0; page++) { 2167 mlen = MIN(len, R92C_FW_PAGE_SIZE); 2168 rtwn_fw_loadpage(sc, page, ptr, mlen); 2169 ptr += mlen; 2170 len -= mlen; 2171 } 2172 2173 /* Disable FW download. */ 2174 rtwn_write_1(sc, R92C_MCUFWDL, 2175 rtwn_read_1(sc, R92C_MCUFWDL) & ~R92C_MCUFWDL_EN); 2176 rtwn_write_1(sc, R92C_MCUFWDL + 1, 0); 2177 2178 /* Wait for checksum report. */ 2179 for (ntries = 0; ntries < 1000; ntries++) { 2180 if (rtwn_read_4(sc, R92C_MCUFWDL) & R92C_MCUFWDL_CHKSUM_RPT) 2181 break; 2182 DELAY(5); 2183 } 2184 if (ntries == 1000) { 2185 device_printf(sc->sc_dev, 2186 "timeout waiting for checksum report\n"); 2187 error = ETIMEDOUT; 2188 goto fail; 2189 } 2190 2191 reg = rtwn_read_4(sc, R92C_MCUFWDL); 2192 reg = (reg & ~R92C_MCUFWDL_WINTINI_RDY) | R92C_MCUFWDL_RDY; 2193 rtwn_write_4(sc, R92C_MCUFWDL, reg); 2194 /* Wait for firmware readiness. */ 2195 for (ntries = 0; ntries < 2000; ntries++) { 2196 if (rtwn_read_4(sc, R92C_MCUFWDL) & R92C_MCUFWDL_WINTINI_RDY) 2197 break; 2198 DELAY(50); 2199 } 2200 if (ntries == 1000) { 2201 device_printf(sc->sc_dev, 2202 "timeout waiting for firmware readiness\n"); 2203 error = ETIMEDOUT; 2204 goto fail; 2205 } 2206fail: 2207 firmware_put(fw, FIRMWARE_UNLOAD); 2208 return (error); 2209} 2210 2211static int 2212rtwn_dma_init(struct rtwn_softc *sc) 2213{ 2214 uint32_t reg; 2215 int error; 2216 2217 /* Initialize LLT table. */ 2218 error = rtwn_llt_init(sc); 2219 if (error != 0) 2220 return error; 2221 2222 /* Set number of pages for normal priority queue. */ 2223 rtwn_write_2(sc, R92C_RQPN_NPQ, 0); 2224 rtwn_write_4(sc, R92C_RQPN, 2225 /* Set number of pages for public queue. */ 2226 SM(R92C_RQPN_PUBQ, R92C_PUBQ_NPAGES) | 2227 /* Set number of pages for high priority queue. */ 2228 SM(R92C_RQPN_HPQ, R92C_HPQ_NPAGES) | 2229 /* Set number of pages for low priority queue. */ 2230 SM(R92C_RQPN_LPQ, R92C_LPQ_NPAGES) | 2231 /* Load values. */ 2232 R92C_RQPN_LD); 2233 2234 rtwn_write_1(sc, R92C_TXPKTBUF_BCNQ_BDNY, R92C_TX_PAGE_BOUNDARY); 2235 rtwn_write_1(sc, R92C_TXPKTBUF_MGQ_BDNY, R92C_TX_PAGE_BOUNDARY); 2236 rtwn_write_1(sc, R92C_TXPKTBUF_WMAC_LBK_BF_HD, R92C_TX_PAGE_BOUNDARY); 2237 rtwn_write_1(sc, R92C_TRXFF_BNDY, R92C_TX_PAGE_BOUNDARY); 2238 rtwn_write_1(sc, R92C_TDECTRL + 1, R92C_TX_PAGE_BOUNDARY); 2239 2240 reg = rtwn_read_2(sc, R92C_TRXDMA_CTRL); 2241 reg &= ~R92C_TRXDMA_CTRL_QMAP_M; 2242 reg |= 0xF771; 2243 rtwn_write_2(sc, R92C_TRXDMA_CTRL, reg); 2244 2245 rtwn_write_4(sc, R92C_TCR, R92C_TCR_CFENDFORM | (1 << 12) | (1 << 13)); 2246 2247 /* Configure Tx DMA. */ 2248 rtwn_write_4(sc, R92C_BKQ_DESA, sc->tx_ring[RTWN_BK_QUEUE].paddr); 2249 rtwn_write_4(sc, R92C_BEQ_DESA, sc->tx_ring[RTWN_BE_QUEUE].paddr); 2250 rtwn_write_4(sc, R92C_VIQ_DESA, sc->tx_ring[RTWN_VI_QUEUE].paddr); 2251 rtwn_write_4(sc, R92C_VOQ_DESA, sc->tx_ring[RTWN_VO_QUEUE].paddr); 2252 rtwn_write_4(sc, R92C_BCNQ_DESA, sc->tx_ring[RTWN_BEACON_QUEUE].paddr); 2253 rtwn_write_4(sc, R92C_MGQ_DESA, sc->tx_ring[RTWN_MGNT_QUEUE].paddr); 2254 rtwn_write_4(sc, R92C_HQ_DESA, sc->tx_ring[RTWN_HIGH_QUEUE].paddr); 2255 2256 /* Configure Rx DMA. */ 2257 rtwn_write_4(sc, R92C_RX_DESA, sc->rx_ring.paddr); 2258 2259 /* Set Tx/Rx transfer page boundary. */ 2260 rtwn_write_2(sc, R92C_TRXFF_BNDY + 2, 0x27ff); 2261 2262 /* Set Tx/Rx transfer page size. */ 2263 rtwn_write_1(sc, R92C_PBP, 2264 SM(R92C_PBP_PSRX, R92C_PBP_128) | 2265 SM(R92C_PBP_PSTX, R92C_PBP_128)); 2266 return (0); 2267} 2268 2269static void 2270rtwn_mac_init(struct rtwn_softc *sc) 2271{ 2272 int i; 2273 2274 /* Write MAC initialization values. */ 2275 for (i = 0; i < nitems(rtl8192ce_mac); i++) 2276 rtwn_write_1(sc, rtl8192ce_mac[i].reg, rtl8192ce_mac[i].val); 2277} 2278 2279static void 2280rtwn_bb_init(struct rtwn_softc *sc) 2281{ 2282 const struct rtwn_bb_prog *prog; 2283 uint32_t reg; 2284 int i; 2285 2286 /* Enable BB and RF. */ 2287 rtwn_write_2(sc, R92C_SYS_FUNC_EN, 2288 rtwn_read_2(sc, R92C_SYS_FUNC_EN) | 2289 R92C_SYS_FUNC_EN_BBRSTB | R92C_SYS_FUNC_EN_BB_GLB_RST | 2290 R92C_SYS_FUNC_EN_DIO_RF); 2291 2292 rtwn_write_2(sc, R92C_AFE_PLL_CTRL, 0xdb83); 2293 2294 rtwn_write_1(sc, R92C_RF_CTRL, 2295 R92C_RF_CTRL_EN | R92C_RF_CTRL_RSTB | R92C_RF_CTRL_SDMRSTB); 2296 2297 rtwn_write_1(sc, R92C_SYS_FUNC_EN, 2298 R92C_SYS_FUNC_EN_DIO_PCIE | R92C_SYS_FUNC_EN_PCIEA | 2299 R92C_SYS_FUNC_EN_PPLL | R92C_SYS_FUNC_EN_BB_GLB_RST | 2300 R92C_SYS_FUNC_EN_BBRSTB); 2301 2302 rtwn_write_1(sc, R92C_AFE_XTAL_CTRL + 1, 0x80); 2303 2304 rtwn_write_4(sc, R92C_LEDCFG0, 2305 rtwn_read_4(sc, R92C_LEDCFG0) | 0x00800000); 2306 2307 /* Select BB programming. */ 2308 prog = (sc->chip & RTWN_CHIP_92C) ? 2309 &rtl8192ce_bb_prog_2t : &rtl8192ce_bb_prog_1t; 2310 2311 /* Write BB initialization values. */ 2312 for (i = 0; i < prog->count; i++) { 2313 rtwn_bb_write(sc, prog->regs[i], prog->vals[i]); 2314 DELAY(1); 2315 } 2316 2317 if (sc->chip & RTWN_CHIP_92C_1T2R) { 2318 /* 8192C 1T only configuration. */ 2319 reg = rtwn_bb_read(sc, R92C_FPGA0_TXINFO); 2320 reg = (reg & ~0x00000003) | 0x2; 2321 rtwn_bb_write(sc, R92C_FPGA0_TXINFO, reg); 2322 2323 reg = rtwn_bb_read(sc, R92C_FPGA1_TXINFO); 2324 reg = (reg & ~0x00300033) | 0x00200022; 2325 rtwn_bb_write(sc, R92C_FPGA1_TXINFO, reg); 2326 2327 reg = rtwn_bb_read(sc, R92C_CCK0_AFESETTING); 2328 reg = (reg & ~0xff000000) | 0x45 << 24; 2329 rtwn_bb_write(sc, R92C_CCK0_AFESETTING, reg); 2330 2331 reg = rtwn_bb_read(sc, R92C_OFDM0_TRXPATHENA); 2332 reg = (reg & ~0x000000ff) | 0x23; 2333 rtwn_bb_write(sc, R92C_OFDM0_TRXPATHENA, reg); 2334 2335 reg = rtwn_bb_read(sc, R92C_OFDM0_AGCPARAM1); 2336 reg = (reg & ~0x00000030) | 1 << 4; 2337 rtwn_bb_write(sc, R92C_OFDM0_AGCPARAM1, reg); 2338 2339 reg = rtwn_bb_read(sc, 0xe74); 2340 reg = (reg & ~0x0c000000) | 2 << 26; 2341 rtwn_bb_write(sc, 0xe74, reg); 2342 reg = rtwn_bb_read(sc, 0xe78); 2343 reg = (reg & ~0x0c000000) | 2 << 26; 2344 rtwn_bb_write(sc, 0xe78, reg); 2345 reg = rtwn_bb_read(sc, 0xe7c); 2346 reg = (reg & ~0x0c000000) | 2 << 26; 2347 rtwn_bb_write(sc, 0xe7c, reg); 2348 reg = rtwn_bb_read(sc, 0xe80); 2349 reg = (reg & ~0x0c000000) | 2 << 26; 2350 rtwn_bb_write(sc, 0xe80, reg); 2351 reg = rtwn_bb_read(sc, 0xe88); 2352 reg = (reg & ~0x0c000000) | 2 << 26; 2353 rtwn_bb_write(sc, 0xe88, reg); 2354 } 2355 2356 /* Write AGC values. */ 2357 for (i = 0; i < prog->agccount; i++) { 2358 rtwn_bb_write(sc, R92C_OFDM0_AGCRSSITABLE, 2359 prog->agcvals[i]); 2360 DELAY(1); 2361 } 2362 2363 if (rtwn_bb_read(sc, R92C_HSSI_PARAM2(0)) & 2364 R92C_HSSI_PARAM2_CCK_HIPWR) 2365 sc->sc_flags |= RTWN_FLAG_CCK_HIPWR; 2366} 2367 2368static void 2369rtwn_rf_init(struct rtwn_softc *sc) 2370{ 2371 const struct rtwn_rf_prog *prog; 2372 uint32_t reg, type; 2373 int i, j, idx, off; 2374 2375 /* Select RF programming based on board type. */ 2376 if (!(sc->chip & RTWN_CHIP_92C)) { 2377 if (sc->board_type == R92C_BOARD_TYPE_MINICARD) 2378 prog = rtl8188ce_rf_prog; 2379 else if (sc->board_type == R92C_BOARD_TYPE_HIGHPA) 2380 prog = rtl8188ru_rf_prog; 2381 else 2382 prog = rtl8188cu_rf_prog; 2383 } else 2384 prog = rtl8192ce_rf_prog; 2385 2386 for (i = 0; i < sc->nrxchains; i++) { 2387 /* Save RF_ENV control type. */ 2388 idx = i / 2; 2389 off = (i % 2) * 16; 2390 reg = rtwn_bb_read(sc, R92C_FPGA0_RFIFACESW(idx)); 2391 type = (reg >> off) & 0x10; 2392 2393 /* Set RF_ENV enable. */ 2394 reg = rtwn_bb_read(sc, R92C_FPGA0_RFIFACEOE(i)); 2395 reg |= 0x100000; 2396 rtwn_bb_write(sc, R92C_FPGA0_RFIFACEOE(i), reg); 2397 DELAY(1); 2398 /* Set RF_ENV output high. */ 2399 reg = rtwn_bb_read(sc, R92C_FPGA0_RFIFACEOE(i)); 2400 reg |= 0x10; 2401 rtwn_bb_write(sc, R92C_FPGA0_RFIFACEOE(i), reg); 2402 DELAY(1); 2403 /* Set address and data lengths of RF registers. */ 2404 reg = rtwn_bb_read(sc, R92C_HSSI_PARAM2(i)); 2405 reg &= ~R92C_HSSI_PARAM2_ADDR_LENGTH; 2406 rtwn_bb_write(sc, R92C_HSSI_PARAM2(i), reg); 2407 DELAY(1); 2408 reg = rtwn_bb_read(sc, R92C_HSSI_PARAM2(i)); 2409 reg &= ~R92C_HSSI_PARAM2_DATA_LENGTH; 2410 rtwn_bb_write(sc, R92C_HSSI_PARAM2(i), reg); 2411 DELAY(1); 2412 2413 /* Write RF initialization values for this chain. */ 2414 for (j = 0; j < prog[i].count; j++) { 2415 if (prog[i].regs[j] >= 0xf9 && 2416 prog[i].regs[j] <= 0xfe) { 2417 /* 2418 * These are fake RF registers offsets that 2419 * indicate a delay is required. 2420 */ 2421 DELAY(50); 2422 continue; 2423 } 2424 rtwn_rf_write(sc, i, prog[i].regs[j], 2425 prog[i].vals[j]); 2426 DELAY(1); 2427 } 2428 2429 /* Restore RF_ENV control type. */ 2430 reg = rtwn_bb_read(sc, R92C_FPGA0_RFIFACESW(idx)); 2431 reg &= ~(0x10 << off) | (type << off); 2432 rtwn_bb_write(sc, R92C_FPGA0_RFIFACESW(idx), reg); 2433 2434 /* Cache RF register CHNLBW. */ 2435 sc->rf_chnlbw[i] = rtwn_rf_read(sc, i, R92C_RF_CHNLBW); 2436 } 2437 2438 if ((sc->chip & (RTWN_CHIP_UMC_A_CUT | RTWN_CHIP_92C)) == 2439 RTWN_CHIP_UMC_A_CUT) { 2440 rtwn_rf_write(sc, 0, R92C_RF_RX_G1, 0x30255); 2441 rtwn_rf_write(sc, 0, R92C_RF_RX_G2, 0x50a00); 2442 } 2443} 2444 2445static void 2446rtwn_cam_init(struct rtwn_softc *sc) 2447{ 2448 /* Invalidate all CAM entries. */ 2449 rtwn_write_4(sc, R92C_CAMCMD, 2450 R92C_CAMCMD_POLLING | R92C_CAMCMD_CLR); 2451} 2452 2453static void 2454rtwn_pa_bias_init(struct rtwn_softc *sc) 2455{ 2456 uint8_t reg; 2457 int i; 2458 2459 for (i = 0; i < sc->nrxchains; i++) { 2460 if (sc->pa_setting & (1 << i)) 2461 continue; 2462 rtwn_rf_write(sc, i, R92C_RF_IPA, 0x0f406); 2463 rtwn_rf_write(sc, i, R92C_RF_IPA, 0x4f406); 2464 rtwn_rf_write(sc, i, R92C_RF_IPA, 0x8f406); 2465 rtwn_rf_write(sc, i, R92C_RF_IPA, 0xcf406); 2466 } 2467 if (!(sc->pa_setting & 0x10)) { 2468 reg = rtwn_read_1(sc, 0x16); 2469 reg = (reg & ~0xf0) | 0x90; 2470 rtwn_write_1(sc, 0x16, reg); 2471 } 2472} 2473 2474static void 2475rtwn_rxfilter_init(struct rtwn_softc *sc) 2476{ 2477 /* Initialize Rx filter. */ 2478 /* TODO: use better filter for monitor mode. */ 2479 rtwn_write_4(sc, R92C_RCR, 2480 R92C_RCR_AAP | R92C_RCR_APM | R92C_RCR_AM | R92C_RCR_AB | 2481 R92C_RCR_APP_ICV | R92C_RCR_AMF | R92C_RCR_HTC_LOC_CTRL | 2482 R92C_RCR_APP_MIC | R92C_RCR_APP_PHYSTS); 2483 /* Accept all multicast frames. */ 2484 rtwn_write_4(sc, R92C_MAR + 0, 0xffffffff); 2485 rtwn_write_4(sc, R92C_MAR + 4, 0xffffffff); 2486 /* Accept all management frames. */ 2487 rtwn_write_2(sc, R92C_RXFLTMAP0, 0xffff); 2488 /* Reject all control frames. */ 2489 rtwn_write_2(sc, R92C_RXFLTMAP1, 0x0000); 2490 /* Accept all data frames. */ 2491 rtwn_write_2(sc, R92C_RXFLTMAP2, 0xffff); 2492} 2493 2494static void 2495rtwn_edca_init(struct rtwn_softc *sc) 2496{ 2497 2498 rtwn_write_2(sc, R92C_SPEC_SIFS, 0x1010); 2499 rtwn_write_2(sc, R92C_MAC_SPEC_SIFS, 0x1010); 2500 rtwn_write_2(sc, R92C_SIFS_CCK, 0x1010); 2501 rtwn_write_2(sc, R92C_SIFS_OFDM, 0x0e0e); 2502 rtwn_write_4(sc, R92C_EDCA_BE_PARAM, 0x005ea42b); 2503 rtwn_write_4(sc, R92C_EDCA_BK_PARAM, 0x0000a44f); 2504 rtwn_write_4(sc, R92C_EDCA_VI_PARAM, 0x005e4322); 2505 rtwn_write_4(sc, R92C_EDCA_VO_PARAM, 0x002f3222); 2506} 2507 2508static void 2509rtwn_write_txpower(struct rtwn_softc *sc, int chain, 2510 uint16_t power[RTWN_RIDX_COUNT]) 2511{ 2512 uint32_t reg; 2513 2514 /* Write per-CCK rate Tx power. */ 2515 if (chain == 0) { 2516 reg = rtwn_bb_read(sc, R92C_TXAGC_A_CCK1_MCS32); 2517 reg = RW(reg, R92C_TXAGC_A_CCK1, power[0]); 2518 rtwn_bb_write(sc, R92C_TXAGC_A_CCK1_MCS32, reg); 2519 reg = rtwn_bb_read(sc, R92C_TXAGC_B_CCK11_A_CCK2_11); 2520 reg = RW(reg, R92C_TXAGC_A_CCK2, power[1]); 2521 reg = RW(reg, R92C_TXAGC_A_CCK55, power[2]); 2522 reg = RW(reg, R92C_TXAGC_A_CCK11, power[3]); 2523 rtwn_bb_write(sc, R92C_TXAGC_B_CCK11_A_CCK2_11, reg); 2524 } else { 2525 reg = rtwn_bb_read(sc, R92C_TXAGC_B_CCK1_55_MCS32); 2526 reg = RW(reg, R92C_TXAGC_B_CCK1, power[0]); 2527 reg = RW(reg, R92C_TXAGC_B_CCK2, power[1]); 2528 reg = RW(reg, R92C_TXAGC_B_CCK55, power[2]); 2529 rtwn_bb_write(sc, R92C_TXAGC_B_CCK1_55_MCS32, reg); 2530 reg = rtwn_bb_read(sc, R92C_TXAGC_B_CCK11_A_CCK2_11); 2531 reg = RW(reg, R92C_TXAGC_B_CCK11, power[3]); 2532 rtwn_bb_write(sc, R92C_TXAGC_B_CCK11_A_CCK2_11, reg); 2533 } 2534 /* Write per-OFDM rate Tx power. */ 2535 rtwn_bb_write(sc, R92C_TXAGC_RATE18_06(chain), 2536 SM(R92C_TXAGC_RATE06, power[ 4]) | 2537 SM(R92C_TXAGC_RATE09, power[ 5]) | 2538 SM(R92C_TXAGC_RATE12, power[ 6]) | 2539 SM(R92C_TXAGC_RATE18, power[ 7])); 2540 rtwn_bb_write(sc, R92C_TXAGC_RATE54_24(chain), 2541 SM(R92C_TXAGC_RATE24, power[ 8]) | 2542 SM(R92C_TXAGC_RATE36, power[ 9]) | 2543 SM(R92C_TXAGC_RATE48, power[10]) | 2544 SM(R92C_TXAGC_RATE54, power[11])); 2545 /* Write per-MCS Tx power. */ 2546 rtwn_bb_write(sc, R92C_TXAGC_MCS03_MCS00(chain), 2547 SM(R92C_TXAGC_MCS00, power[12]) | 2548 SM(R92C_TXAGC_MCS01, power[13]) | 2549 SM(R92C_TXAGC_MCS02, power[14]) | 2550 SM(R92C_TXAGC_MCS03, power[15])); 2551 rtwn_bb_write(sc, R92C_TXAGC_MCS07_MCS04(chain), 2552 SM(R92C_TXAGC_MCS04, power[16]) | 2553 SM(R92C_TXAGC_MCS05, power[17]) | 2554 SM(R92C_TXAGC_MCS06, power[18]) | 2555 SM(R92C_TXAGC_MCS07, power[19])); 2556 rtwn_bb_write(sc, R92C_TXAGC_MCS11_MCS08(chain), 2557 SM(R92C_TXAGC_MCS08, power[20]) | 2558 SM(R92C_TXAGC_MCS09, power[21]) | 2559 SM(R92C_TXAGC_MCS10, power[22]) | 2560 SM(R92C_TXAGC_MCS11, power[23])); 2561 rtwn_bb_write(sc, R92C_TXAGC_MCS15_MCS12(chain), 2562 SM(R92C_TXAGC_MCS12, power[24]) | 2563 SM(R92C_TXAGC_MCS13, power[25]) | 2564 SM(R92C_TXAGC_MCS14, power[26]) | 2565 SM(R92C_TXAGC_MCS15, power[27])); 2566} 2567 2568static void 2569rtwn_get_txpower(struct rtwn_softc *sc, int chain, 2570 struct ieee80211_channel *c, struct ieee80211_channel *extc, 2571 uint16_t power[RTWN_RIDX_COUNT]) 2572{ 2573 struct ieee80211com *ic = &sc->sc_ic; 2574 struct r92c_rom *rom = &sc->rom; 2575 uint16_t cckpow, ofdmpow, htpow, diff, max; 2576 const struct rtwn_txpwr *base; 2577 int ridx, chan, group; 2578 2579 /* Determine channel group. */ 2580 chan = ieee80211_chan2ieee(ic, c); /* XXX center freq! */ 2581 if (chan <= 3) 2582 group = 0; 2583 else if (chan <= 9) 2584 group = 1; 2585 else 2586 group = 2; 2587 2588 /* Get original Tx power based on board type and RF chain. */ 2589 if (!(sc->chip & RTWN_CHIP_92C)) { 2590 if (sc->board_type == R92C_BOARD_TYPE_HIGHPA) 2591 base = &rtl8188ru_txagc[chain]; 2592 else 2593 base = &rtl8192cu_txagc[chain]; 2594 } else 2595 base = &rtl8192cu_txagc[chain]; 2596 2597 memset(power, 0, RTWN_RIDX_COUNT * sizeof(power[0])); 2598 if (sc->regulatory == 0) { 2599 for (ridx = RTWN_RIDX_CCK1; ridx <= RTWN_RIDX_CCK11; ridx++) 2600 power[ridx] = base->pwr[0][ridx]; 2601 } 2602 for (ridx = RTWN_RIDX_OFDM6; ridx < RTWN_RIDX_COUNT; ridx++) { 2603 if (sc->regulatory == 3) { 2604 power[ridx] = base->pwr[0][ridx]; 2605 /* Apply vendor limits. */ 2606 if (extc != NULL) 2607 max = rom->ht40_max_pwr[group]; 2608 else 2609 max = rom->ht20_max_pwr[group]; 2610 max = (max >> (chain * 4)) & 0xf; 2611 if (power[ridx] > max) 2612 power[ridx] = max; 2613 } else if (sc->regulatory == 1) { 2614 if (extc == NULL) 2615 power[ridx] = base->pwr[group][ridx]; 2616 } else if (sc->regulatory != 2) 2617 power[ridx] = base->pwr[0][ridx]; 2618 } 2619 2620 /* Compute per-CCK rate Tx power. */ 2621 cckpow = rom->cck_tx_pwr[chain][group]; 2622 for (ridx = RTWN_RIDX_CCK1; ridx <= RTWN_RIDX_CCK11; ridx++) { 2623 power[ridx] += cckpow; 2624 if (power[ridx] > R92C_MAX_TX_PWR) 2625 power[ridx] = R92C_MAX_TX_PWR; 2626 } 2627 2628 htpow = rom->ht40_1s_tx_pwr[chain][group]; 2629 if (sc->ntxchains > 1) { 2630 /* Apply reduction for 2 spatial streams. */ 2631 diff = rom->ht40_2s_tx_pwr_diff[group]; 2632 diff = (diff >> (chain * 4)) & 0xf; 2633 htpow = (htpow > diff) ? htpow - diff : 0; 2634 } 2635 2636 /* Compute per-OFDM rate Tx power. */ 2637 diff = rom->ofdm_tx_pwr_diff[group]; 2638 diff = (diff >> (chain * 4)) & 0xf; 2639 ofdmpow = htpow + diff; /* HT->OFDM correction. */ 2640 for (ridx = RTWN_RIDX_OFDM6; ridx <= RTWN_RIDX_OFDM54; ridx++) { 2641 power[ridx] += ofdmpow; 2642 if (power[ridx] > R92C_MAX_TX_PWR) 2643 power[ridx] = R92C_MAX_TX_PWR; 2644 } 2645 2646 /* Compute per-MCS Tx power. */ 2647 if (extc == NULL) { 2648 diff = rom->ht20_tx_pwr_diff[group]; 2649 diff = (diff >> (chain * 4)) & 0xf; 2650 htpow += diff; /* HT40->HT20 correction. */ 2651 } 2652 for (ridx = RTWN_RIDX_MCS0; ridx <= RTWN_RIDX_MCS15; ridx++) { 2653 power[ridx] += htpow; 2654 if (power[ridx] > R92C_MAX_TX_PWR) 2655 power[ridx] = R92C_MAX_TX_PWR; 2656 } 2657#ifdef RTWN_DEBUG 2658 if (sc->sc_debug >= 4) { 2659 /* Dump per-rate Tx power values. */ 2660 printf("Tx power for chain %d:\n", chain); 2661 for (ridx = RTWN_RIDX_CCK1; ridx < RTWN_RIDX_COUNT; ridx++) 2662 printf("Rate %d = %u\n", ridx, power[ridx]); 2663 } 2664#endif 2665} 2666 2667static void 2668rtwn_set_txpower(struct rtwn_softc *sc, struct ieee80211_channel *c, 2669 struct ieee80211_channel *extc) 2670{ 2671 uint16_t power[RTWN_RIDX_COUNT]; 2672 int i; 2673 2674 for (i = 0; i < sc->ntxchains; i++) { 2675 /* Compute per-rate Tx power values. */ 2676 rtwn_get_txpower(sc, i, c, extc, power); 2677 /* Write per-rate Tx power values to hardware. */ 2678 rtwn_write_txpower(sc, i, power); 2679 } 2680} 2681 2682static void 2683rtwn_set_rx_bssid_all(struct rtwn_softc *sc, int enable) 2684{ 2685 uint32_t reg; 2686 2687 reg = rtwn_read_4(sc, R92C_RCR); 2688 if (enable) 2689 reg &= ~R92C_RCR_CBSSID_BCN; 2690 else 2691 reg |= R92C_RCR_CBSSID_BCN; 2692 rtwn_write_4(sc, R92C_RCR, reg); 2693} 2694 2695static void 2696rtwn_set_gain(struct rtwn_softc *sc, uint8_t gain) 2697{ 2698 uint32_t reg; 2699 2700 reg = rtwn_bb_read(sc, R92C_OFDM0_AGCCORE1(0)); 2701 reg = RW(reg, R92C_OFDM0_AGCCORE1_GAIN, gain); 2702 rtwn_bb_write(sc, R92C_OFDM0_AGCCORE1(0), reg); 2703 2704 reg = rtwn_bb_read(sc, R92C_OFDM0_AGCCORE1(1)); 2705 reg = RW(reg, R92C_OFDM0_AGCCORE1_GAIN, gain); 2706 rtwn_bb_write(sc, R92C_OFDM0_AGCCORE1(1), reg); 2707} 2708 2709static void 2710rtwn_scan_start(struct ieee80211com *ic) 2711{ 2712 struct rtwn_softc *sc = ic->ic_softc; 2713 2714 RTWN_LOCK(sc); 2715 /* Receive beacons / probe responses from any BSSID. */ 2716 rtwn_set_rx_bssid_all(sc, 1); 2717 /* Set gain for scanning. */ 2718 rtwn_set_gain(sc, 0x20); 2719 RTWN_UNLOCK(sc); 2720} 2721 2722static void 2723rtwn_scan_end(struct ieee80211com *ic) 2724{ 2725 struct rtwn_softc *sc = ic->ic_softc; 2726 2727 RTWN_LOCK(sc); 2728 /* Restore limitations. */ 2729 rtwn_set_rx_bssid_all(sc, 0); 2730 /* Set gain under link. */ 2731 rtwn_set_gain(sc, 0x32); 2732 RTWN_UNLOCK(sc); 2733} 2734 2735static void 2736rtwn_getradiocaps(struct ieee80211com *ic, 2737 int maxchans, int *nchans, struct ieee80211_channel chans[]) 2738{ 2739 uint8_t bands[IEEE80211_MODE_BYTES]; 2740 2741 memset(bands, 0, sizeof(bands)); 2742 setbit(bands, IEEE80211_MODE_11B); 2743 setbit(bands, IEEE80211_MODE_11G); 2744 ieee80211_add_channels_default_2ghz(chans, maxchans, nchans, bands, 0); 2745} 2746 2747static void 2748rtwn_set_channel(struct ieee80211com *ic) 2749{ 2750 struct rtwn_softc *sc = ic->ic_softc; 2751 struct ieee80211vap *vap = TAILQ_FIRST(&ic->ic_vaps); 2752 2753 RTWN_LOCK(sc); 2754 if (vap->iv_state == IEEE80211_S_SCAN) { 2755 /* Make link LED blink during scan. */ 2756 rtwn_set_led(sc, RTWN_LED_LINK, !sc->ledlink); 2757 } 2758 rtwn_set_chan(sc, ic->ic_curchan, NULL); 2759 RTWN_UNLOCK(sc); 2760} 2761 2762static void 2763rtwn_update_mcast(struct ieee80211com *ic) 2764{ 2765 2766 /* XXX do nothing? */ 2767} 2768 2769static void 2770rtwn_set_chan(struct rtwn_softc *sc, struct ieee80211_channel *c, 2771 struct ieee80211_channel *extc) 2772{ 2773 struct ieee80211com *ic = &sc->sc_ic; 2774 u_int chan; 2775 int i; 2776 2777 chan = ieee80211_chan2ieee(ic, c); /* XXX center freq! */ 2778 if (chan == 0 || chan == IEEE80211_CHAN_ANY) { 2779 device_printf(sc->sc_dev, 2780 "%s: invalid channel %x\n", __func__, chan); 2781 return; 2782 } 2783 2784 /* Set Tx power for this new channel. */ 2785 rtwn_set_txpower(sc, c, extc); 2786 2787 for (i = 0; i < sc->nrxchains; i++) { 2788 rtwn_rf_write(sc, i, R92C_RF_CHNLBW, 2789 RW(sc->rf_chnlbw[i], R92C_RF_CHNLBW_CHNL, chan)); 2790 } 2791#ifndef IEEE80211_NO_HT 2792 if (extc != NULL) { 2793 uint32_t reg; 2794 2795 /* Is secondary channel below or above primary? */ 2796 int prichlo = c->ic_freq < extc->ic_freq; 2797 2798 rtwn_write_1(sc, R92C_BWOPMODE, 2799 rtwn_read_1(sc, R92C_BWOPMODE) & ~R92C_BWOPMODE_20MHZ); 2800 2801 reg = rtwn_read_1(sc, R92C_RRSR + 2); 2802 reg = (reg & ~0x6f) | (prichlo ? 1 : 2) << 5; 2803 rtwn_write_1(sc, R92C_RRSR + 2, reg); 2804 2805 rtwn_bb_write(sc, R92C_FPGA0_RFMOD, 2806 rtwn_bb_read(sc, R92C_FPGA0_RFMOD) | R92C_RFMOD_40MHZ); 2807 rtwn_bb_write(sc, R92C_FPGA1_RFMOD, 2808 rtwn_bb_read(sc, R92C_FPGA1_RFMOD) | R92C_RFMOD_40MHZ); 2809 2810 /* Set CCK side band. */ 2811 reg = rtwn_bb_read(sc, R92C_CCK0_SYSTEM); 2812 reg = (reg & ~0x00000010) | (prichlo ? 0 : 1) << 4; 2813 rtwn_bb_write(sc, R92C_CCK0_SYSTEM, reg); 2814 2815 reg = rtwn_bb_read(sc, R92C_OFDM1_LSTF); 2816 reg = (reg & ~0x00000c00) | (prichlo ? 1 : 2) << 10; 2817 rtwn_bb_write(sc, R92C_OFDM1_LSTF, reg); 2818 2819 rtwn_bb_write(sc, R92C_FPGA0_ANAPARAM2, 2820 rtwn_bb_read(sc, R92C_FPGA0_ANAPARAM2) & 2821 ~R92C_FPGA0_ANAPARAM2_CBW20); 2822 2823 reg = rtwn_bb_read(sc, 0x818); 2824 reg = (reg & ~0x0c000000) | (prichlo ? 2 : 1) << 26; 2825 rtwn_bb_write(sc, 0x818, reg); 2826 2827 /* Select 40MHz bandwidth. */ 2828 rtwn_rf_write(sc, 0, R92C_RF_CHNLBW, 2829 (sc->rf_chnlbw[0] & ~0xfff) | chan); 2830 } else 2831#endif 2832 { 2833 rtwn_write_1(sc, R92C_BWOPMODE, 2834 rtwn_read_1(sc, R92C_BWOPMODE) | R92C_BWOPMODE_20MHZ); 2835 2836 rtwn_bb_write(sc, R92C_FPGA0_RFMOD, 2837 rtwn_bb_read(sc, R92C_FPGA0_RFMOD) & ~R92C_RFMOD_40MHZ); 2838 rtwn_bb_write(sc, R92C_FPGA1_RFMOD, 2839 rtwn_bb_read(sc, R92C_FPGA1_RFMOD) & ~R92C_RFMOD_40MHZ); 2840 2841 rtwn_bb_write(sc, R92C_FPGA0_ANAPARAM2, 2842 rtwn_bb_read(sc, R92C_FPGA0_ANAPARAM2) | 2843 R92C_FPGA0_ANAPARAM2_CBW20); 2844 2845 /* Select 20MHz bandwidth. */ 2846 rtwn_rf_write(sc, 0, R92C_RF_CHNLBW, 2847 (sc->rf_chnlbw[0] & ~0xfff) | R92C_RF_CHNLBW_BW20 | chan); 2848 } 2849} 2850 2851static int 2852rtwn_iq_calib_chain(struct rtwn_softc *sc, int chain, uint16_t tx[2], 2853 uint16_t rx[2]) 2854{ 2855 uint32_t status; 2856 int offset = chain * 0x20; 2857 2858 if (chain == 0) { /* IQ calibration for chain 0. */ 2859 /* IQ calibration settings for chain 0. */ 2860 rtwn_bb_write(sc, 0xe30, 0x10008c1f); 2861 rtwn_bb_write(sc, 0xe34, 0x10008c1f); 2862 rtwn_bb_write(sc, 0xe38, 0x82140102); 2863 2864 if (sc->ntxchains > 1) { 2865 rtwn_bb_write(sc, 0xe3c, 0x28160202); /* 2T */ 2866 /* IQ calibration settings for chain 1. */ 2867 rtwn_bb_write(sc, 0xe50, 0x10008c22); 2868 rtwn_bb_write(sc, 0xe54, 0x10008c22); 2869 rtwn_bb_write(sc, 0xe58, 0x82140102); 2870 rtwn_bb_write(sc, 0xe5c, 0x28160202); 2871 } else 2872 rtwn_bb_write(sc, 0xe3c, 0x28160502); /* 1T */ 2873 2874 /* LO calibration settings. */ 2875 rtwn_bb_write(sc, 0xe4c, 0x001028d1); 2876 /* We're doing LO and IQ calibration in one shot. */ 2877 rtwn_bb_write(sc, 0xe48, 0xf9000000); 2878 rtwn_bb_write(sc, 0xe48, 0xf8000000); 2879 2880 } else { /* IQ calibration for chain 1. */ 2881 /* We're doing LO and IQ calibration in one shot. */ 2882 rtwn_bb_write(sc, 0xe60, 0x00000002); 2883 rtwn_bb_write(sc, 0xe60, 0x00000000); 2884 } 2885 2886 /* Give LO and IQ calibrations the time to complete. */ 2887 DELAY(1000); 2888 2889 /* Read IQ calibration status. */ 2890 status = rtwn_bb_read(sc, 0xeac); 2891 2892 if (status & (1 << (28 + chain * 3))) 2893 return (0); /* Tx failed. */ 2894 /* Read Tx IQ calibration results. */ 2895 tx[0] = (rtwn_bb_read(sc, 0xe94 + offset) >> 16) & 0x3ff; 2896 tx[1] = (rtwn_bb_read(sc, 0xe9c + offset) >> 16) & 0x3ff; 2897 if (tx[0] == 0x142 || tx[1] == 0x042) 2898 return (0); /* Tx failed. */ 2899 2900 if (status & (1 << (27 + chain * 3))) 2901 return (1); /* Rx failed. */ 2902 /* Read Rx IQ calibration results. */ 2903 rx[0] = (rtwn_bb_read(sc, 0xea4 + offset) >> 16) & 0x3ff; 2904 rx[1] = (rtwn_bb_read(sc, 0xeac + offset) >> 16) & 0x3ff; 2905 if (rx[0] == 0x132 || rx[1] == 0x036) 2906 return (1); /* Rx failed. */ 2907 2908 return (3); /* Both Tx and Rx succeeded. */ 2909} 2910 2911static void 2912rtwn_iq_calib_run(struct rtwn_softc *sc, int n, uint16_t tx[2][2], 2913 uint16_t rx[2][2]) 2914{ 2915 /* Registers to save and restore during IQ calibration. */ 2916 struct iq_cal_regs { 2917 uint32_t adda[16]; 2918 uint8_t txpause; 2919 uint8_t bcn_ctrl; 2920 uint8_t ustime_tsf; 2921 uint32_t gpio_muxcfg; 2922 uint32_t ofdm0_trxpathena; 2923 uint32_t ofdm0_trmuxpar; 2924 uint32_t fpga0_rfifacesw1; 2925 } iq_cal_regs; 2926 static const uint16_t reg_adda[16] = { 2927 0x85c, 0xe6c, 0xe70, 0xe74, 2928 0xe78, 0xe7c, 0xe80, 0xe84, 2929 0xe88, 0xe8c, 0xed0, 0xed4, 2930 0xed8, 0xedc, 0xee0, 0xeec 2931 }; 2932 int i, chain; 2933 uint32_t hssi_param1; 2934 2935 if (n == 0) { 2936 for (i = 0; i < nitems(reg_adda); i++) 2937 iq_cal_regs.adda[i] = rtwn_bb_read(sc, reg_adda[i]); 2938 2939 iq_cal_regs.txpause = rtwn_read_1(sc, R92C_TXPAUSE); 2940 iq_cal_regs.bcn_ctrl = rtwn_read_1(sc, R92C_BCN_CTRL); 2941 iq_cal_regs.ustime_tsf = rtwn_read_1(sc, R92C_USTIME_TSF); 2942 iq_cal_regs.gpio_muxcfg = rtwn_read_4(sc, R92C_GPIO_MUXCFG); 2943 } 2944 2945 if (sc->ntxchains == 1) { 2946 rtwn_bb_write(sc, reg_adda[0], 0x0b1b25a0); 2947 for (i = 1; i < nitems(reg_adda); i++) 2948 rtwn_bb_write(sc, reg_adda[i], 0x0bdb25a0); 2949 } else { 2950 for (i = 0; i < nitems(reg_adda); i++) 2951 rtwn_bb_write(sc, reg_adda[i], 0x04db25a4); 2952 } 2953 2954 hssi_param1 = rtwn_bb_read(sc, R92C_HSSI_PARAM1(0)); 2955 if (!(hssi_param1 & R92C_HSSI_PARAM1_PI)) { 2956 rtwn_bb_write(sc, R92C_HSSI_PARAM1(0), 2957 hssi_param1 | R92C_HSSI_PARAM1_PI); 2958 rtwn_bb_write(sc, R92C_HSSI_PARAM1(1), 2959 hssi_param1 | R92C_HSSI_PARAM1_PI); 2960 } 2961 2962 if (n == 0) { 2963 iq_cal_regs.ofdm0_trxpathena = 2964 rtwn_bb_read(sc, R92C_OFDM0_TRXPATHENA); 2965 iq_cal_regs.ofdm0_trmuxpar = 2966 rtwn_bb_read(sc, R92C_OFDM0_TRMUXPAR); 2967 iq_cal_regs.fpga0_rfifacesw1 = 2968 rtwn_bb_read(sc, R92C_FPGA0_RFIFACESW(1)); 2969 } 2970 2971 rtwn_bb_write(sc, R92C_OFDM0_TRXPATHENA, 0x03a05600); 2972 rtwn_bb_write(sc, R92C_OFDM0_TRMUXPAR, 0x000800e4); 2973 rtwn_bb_write(sc, R92C_FPGA0_RFIFACESW(1), 0x22204000); 2974 if (sc->ntxchains > 1) { 2975 rtwn_bb_write(sc, R92C_LSSI_PARAM(0), 0x00010000); 2976 rtwn_bb_write(sc, R92C_LSSI_PARAM(1), 0x00010000); 2977 } 2978 2979 rtwn_write_1(sc, R92C_TXPAUSE, 0x3f); 2980 rtwn_write_1(sc, R92C_BCN_CTRL, iq_cal_regs.bcn_ctrl & ~(0x08)); 2981 rtwn_write_1(sc, R92C_USTIME_TSF, iq_cal_regs.ustime_tsf & ~(0x08)); 2982 rtwn_write_1(sc, R92C_GPIO_MUXCFG, 2983 iq_cal_regs.gpio_muxcfg & ~(0x20)); 2984 2985 rtwn_bb_write(sc, 0x0b68, 0x00080000); 2986 if (sc->ntxchains > 1) 2987 rtwn_bb_write(sc, 0x0b6c, 0x00080000); 2988 2989 rtwn_bb_write(sc, 0x0e28, 0x80800000); 2990 rtwn_bb_write(sc, 0x0e40, 0x01007c00); 2991 rtwn_bb_write(sc, 0x0e44, 0x01004800); 2992 2993 rtwn_bb_write(sc, 0x0b68, 0x00080000); 2994 2995 for (chain = 0; chain < sc->ntxchains; chain++) { 2996 if (chain > 0) { 2997 /* Put chain 0 on standby. */ 2998 rtwn_bb_write(sc, 0x0e28, 0x00); 2999 rtwn_bb_write(sc, R92C_LSSI_PARAM(0), 0x00010000); 3000 rtwn_bb_write(sc, 0x0e28, 0x80800000); 3001 3002 /* Enable chain 1. */ 3003 for (i = 0; i < nitems(reg_adda); i++) 3004 rtwn_bb_write(sc, reg_adda[i], 0x0b1b25a4); 3005 } 3006 3007 /* Run IQ calibration twice. */ 3008 for (i = 0; i < 2; i++) { 3009 int ret; 3010 3011 ret = rtwn_iq_calib_chain(sc, chain, 3012 tx[chain], rx[chain]); 3013 if (ret == 0) { 3014 DPRINTF(("%s: chain %d: Tx failed.\n", 3015 __func__, chain)); 3016 tx[chain][0] = 0xff; 3017 tx[chain][1] = 0xff; 3018 rx[chain][0] = 0xff; 3019 rx[chain][1] = 0xff; 3020 } else if (ret == 1) { 3021 DPRINTF(("%s: chain %d: Rx failed.\n", 3022 __func__, chain)); 3023 rx[chain][0] = 0xff; 3024 rx[chain][1] = 0xff; 3025 } else if (ret == 3) { 3026 DPRINTF(("%s: chain %d: Both Tx and Rx " 3027 "succeeded.\n", __func__, chain)); 3028 } 3029 } 3030 3031 DPRINTF(("%s: results for run %d chain %d: tx[0]=0x%x, " 3032 "tx[1]=0x%x rx[0]=0x%x rx[1]=0x%x\n", __func__, n, chain, 3033 tx[chain][0], tx[chain][1], rx[chain][0], rx[chain][1])); 3034 } 3035 3036 rtwn_bb_write(sc, R92C_OFDM0_TRXPATHENA, 3037 iq_cal_regs.ofdm0_trxpathena); 3038 rtwn_bb_write(sc, R92C_FPGA0_RFIFACESW(1), 3039 iq_cal_regs.fpga0_rfifacesw1); 3040 rtwn_bb_write(sc, R92C_OFDM0_TRMUXPAR, iq_cal_regs.ofdm0_trmuxpar); 3041 3042 rtwn_bb_write(sc, 0x0e28, 0x00); 3043 rtwn_bb_write(sc, R92C_LSSI_PARAM(0), 0x00032ed3); 3044 if (sc->ntxchains > 1) 3045 rtwn_bb_write(sc, R92C_LSSI_PARAM(1), 0x00032ed3); 3046 3047 if (n != 0) { 3048 if (!(hssi_param1 & R92C_HSSI_PARAM1_PI)) { 3049 rtwn_bb_write(sc, R92C_HSSI_PARAM1(0), hssi_param1); 3050 rtwn_bb_write(sc, R92C_HSSI_PARAM1(1), hssi_param1); 3051 } 3052 3053 for (i = 0; i < nitems(reg_adda); i++) 3054 rtwn_bb_write(sc, reg_adda[i], iq_cal_regs.adda[i]); 3055 3056 rtwn_write_1(sc, R92C_TXPAUSE, iq_cal_regs.txpause); 3057 rtwn_write_1(sc, R92C_BCN_CTRL, iq_cal_regs.bcn_ctrl); 3058 rtwn_write_1(sc, R92C_USTIME_TSF, iq_cal_regs.ustime_tsf); 3059 rtwn_write_4(sc, R92C_GPIO_MUXCFG, iq_cal_regs.gpio_muxcfg); 3060 } 3061} 3062 3063#define RTWN_IQ_CAL_MAX_TOLERANCE 5 3064static int 3065rtwn_iq_calib_compare_results(uint16_t tx1[2][2], uint16_t rx1[2][2], 3066 uint16_t tx2[2][2], uint16_t rx2[2][2], int ntxchains) 3067{ 3068 int chain, i, tx_ok[2], rx_ok[2]; 3069 3070 tx_ok[0] = tx_ok[1] = rx_ok[0] = rx_ok[1] = 0; 3071 for (chain = 0; chain < ntxchains; chain++) { 3072 for (i = 0; i < 2; i++) { 3073 if (tx1[chain][i] == 0xff || tx2[chain][i] == 0xff || 3074 rx1[chain][i] == 0xff || rx2[chain][i] == 0xff) 3075 continue; 3076 3077 tx_ok[chain] = (abs(tx1[chain][i] - tx2[chain][i]) <= 3078 RTWN_IQ_CAL_MAX_TOLERANCE); 3079 3080 rx_ok[chain] = (abs(rx1[chain][i] - rx2[chain][i]) <= 3081 RTWN_IQ_CAL_MAX_TOLERANCE); 3082 } 3083 } 3084 3085 if (ntxchains > 1) 3086 return (tx_ok[0] && tx_ok[1] && rx_ok[0] && rx_ok[1]); 3087 else 3088 return (tx_ok[0] && rx_ok[0]); 3089} 3090#undef RTWN_IQ_CAL_MAX_TOLERANCE 3091 3092static void 3093rtwn_iq_calib_write_results(struct rtwn_softc *sc, uint16_t tx[2], 3094 uint16_t rx[2], int chain) 3095{ 3096 uint32_t reg, val, x; 3097 long y, tx_c; 3098 3099 if (tx[0] == 0xff || tx[1] == 0xff) 3100 return; 3101 3102 reg = rtwn_bb_read(sc, R92C_OFDM0_TXIQIMBALANCE(chain)); 3103 val = ((reg >> 22) & 0x3ff); 3104 x = tx[0]; 3105 if (x & 0x0200) 3106 x |= 0xfc00; 3107 reg = (((x * val) >> 8) & 0x3ff); 3108 rtwn_bb_write(sc, R92C_OFDM0_TXIQIMBALANCE(chain), reg); 3109 3110 reg = rtwn_bb_read(sc, R92C_OFDM0_ECCATHRESHOLD); 3111 if (((x * val) >> 7) & 0x01) 3112 reg |= 0x80000000; 3113 else 3114 reg &= ~0x80000000; 3115 rtwn_bb_write(sc, R92C_OFDM0_ECCATHRESHOLD, reg); 3116 3117 y = tx[1]; 3118 if (y & 0x00000200) 3119 y |= 0xfffffc00; 3120 tx_c = (y * val) >> 8; 3121 reg = rtwn_bb_read(sc, R92C_OFDM0_TXAFE(chain)); 3122 reg |= ((((tx_c & 0x3c0) >> 6) << 24) & 0xf0000000); 3123 rtwn_bb_write(sc, R92C_OFDM0_TXAFE(chain), reg); 3124 3125 reg = rtwn_bb_read(sc, R92C_OFDM0_TXIQIMBALANCE(chain)); 3126 reg |= (((tx_c & 0x3f) << 16) & 0x003F0000); 3127 rtwn_bb_write(sc, R92C_OFDM0_TXIQIMBALANCE(chain), reg); 3128 3129 reg = rtwn_bb_read(sc, R92C_OFDM0_ECCATHRESHOLD); 3130 if (((y * val) >> 7) & 0x01) 3131 reg |= 0x20000000; 3132 else 3133 reg &= ~0x20000000; 3134 rtwn_bb_write(sc, R92C_OFDM0_ECCATHRESHOLD, reg); 3135 3136 if (rx[0] == 0xff || rx[1] == 0xff) 3137 return; 3138 3139 reg = rtwn_bb_read(sc, R92C_OFDM0_RXIQIMBALANCE(chain)); 3140 reg |= (rx[0] & 0x3ff); 3141 rtwn_bb_write(sc, R92C_OFDM0_RXIQIMBALANCE(chain), reg); 3142 reg |= (((rx[1] & 0x03f) << 8) & 0xFC00); 3143 rtwn_bb_write(sc, R92C_OFDM0_RXIQIMBALANCE(chain), reg); 3144 3145 if (chain == 0) { 3146 reg = rtwn_bb_read(sc, R92C_OFDM0_RXIQEXTANTA); 3147 reg |= (((rx[1] & 0xf) >> 6) & 0x000f); 3148 rtwn_bb_write(sc, R92C_OFDM0_RXIQEXTANTA, reg); 3149 } else { 3150 reg = rtwn_bb_read(sc, R92C_OFDM0_AGCRSSITABLE); 3151 reg |= ((((rx[1] & 0xf) >> 6) << 12) & 0xf000); 3152 rtwn_bb_write(sc, R92C_OFDM0_AGCRSSITABLE, reg); 3153 } 3154} 3155 3156#define RTWN_IQ_CAL_NRUN 3 3157static void 3158rtwn_iq_calib(struct rtwn_softc *sc) 3159{ 3160 uint16_t tx[RTWN_IQ_CAL_NRUN][2][2], rx[RTWN_IQ_CAL_NRUN][2][2]; 3161 int n, valid; 3162 3163 valid = 0; 3164 for (n = 0; n < RTWN_IQ_CAL_NRUN; n++) { 3165 rtwn_iq_calib_run(sc, n, tx[n], rx[n]); 3166 3167 if (n == 0) 3168 continue; 3169 3170 /* Valid results remain stable after consecutive runs. */ 3171 valid = rtwn_iq_calib_compare_results(tx[n - 1], rx[n - 1], 3172 tx[n], rx[n], sc->ntxchains); 3173 if (valid) 3174 break; 3175 } 3176 3177 if (valid) { 3178 rtwn_iq_calib_write_results(sc, tx[n][0], rx[n][0], 0); 3179 if (sc->ntxchains > 1) 3180 rtwn_iq_calib_write_results(sc, tx[n][1], rx[n][1], 1); 3181 } 3182} 3183#undef RTWN_IQ_CAL_NRUN 3184 3185static void 3186rtwn_lc_calib(struct rtwn_softc *sc) 3187{ 3188 uint32_t rf_ac[2]; 3189 uint8_t txmode; 3190 int i; 3191 3192 txmode = rtwn_read_1(sc, R92C_OFDM1_LSTF + 3); 3193 if ((txmode & 0x70) != 0) { 3194 /* Disable all continuous Tx. */ 3195 rtwn_write_1(sc, R92C_OFDM1_LSTF + 3, txmode & ~0x70); 3196 3197 /* Set RF mode to standby mode. */ 3198 for (i = 0; i < sc->nrxchains; i++) { 3199 rf_ac[i] = rtwn_rf_read(sc, i, R92C_RF_AC); 3200 rtwn_rf_write(sc, i, R92C_RF_AC, 3201 RW(rf_ac[i], R92C_RF_AC_MODE, 3202 R92C_RF_AC_MODE_STANDBY)); 3203 } 3204 } else { 3205 /* Block all Tx queues. */ 3206 rtwn_write_1(sc, R92C_TXPAUSE, 0xff); 3207 } 3208 /* Start calibration. */ 3209 rtwn_rf_write(sc, 0, R92C_RF_CHNLBW, 3210 rtwn_rf_read(sc, 0, R92C_RF_CHNLBW) | R92C_RF_CHNLBW_LCSTART); 3211 3212 /* Give calibration the time to complete. */ 3213 DELAY(100); 3214 3215 /* Restore configuration. */ 3216 if ((txmode & 0x70) != 0) { 3217 /* Restore Tx mode. */ 3218 rtwn_write_1(sc, R92C_OFDM1_LSTF + 3, txmode); 3219 /* Restore RF mode. */ 3220 for (i = 0; i < sc->nrxchains; i++) 3221 rtwn_rf_write(sc, i, R92C_RF_AC, rf_ac[i]); 3222 } else { 3223 /* Unblock all Tx queues. */ 3224 rtwn_write_1(sc, R92C_TXPAUSE, 0x00); 3225 } 3226} 3227 3228static void 3229rtwn_temp_calib(struct rtwn_softc *sc) 3230{ 3231 int temp; 3232 3233 if (sc->thcal_state == 0) { 3234 /* Start measuring temperature. */ 3235 rtwn_rf_write(sc, 0, R92C_RF_T_METER, 0x60); 3236 sc->thcal_state = 1; 3237 return; 3238 } 3239 sc->thcal_state = 0; 3240 3241 /* Read measured temperature. */ 3242 temp = rtwn_rf_read(sc, 0, R92C_RF_T_METER) & 0x1f; 3243 if (temp == 0) /* Read failed, skip. */ 3244 return; 3245 DPRINTFN(2, ("temperature=%d\n", temp)); 3246 3247 /* 3248 * Redo IQ and LC calibration if temperature changed significantly 3249 * since last calibration. 3250 */ 3251 if (sc->thcal_lctemp == 0) { 3252 /* First calibration is performed in rtwn_init(). */ 3253 sc->thcal_lctemp = temp; 3254 } else if (abs(temp - sc->thcal_lctemp) > 1) { 3255 DPRINTF(("IQ/LC calib triggered by temp: %d -> %d\n", 3256 sc->thcal_lctemp, temp)); 3257 rtwn_iq_calib(sc); 3258 rtwn_lc_calib(sc); 3259 /* Record temperature of last calibration. */ 3260 sc->thcal_lctemp = temp; 3261 } 3262} 3263 3264static int 3265rtwn_init(struct rtwn_softc *sc) 3266{ 3267 struct ieee80211com *ic = &sc->sc_ic; 3268 struct ieee80211vap *vap = TAILQ_FIRST(&ic->ic_vaps); 3269 uint32_t reg; 3270 uint8_t macaddr[IEEE80211_ADDR_LEN]; 3271 int i, error; 3272 3273 RTWN_LOCK(sc); 3274 3275 if (sc->sc_flags & RTWN_RUNNING) { 3276 RTWN_UNLOCK(sc); 3277 return 0; 3278 } 3279 sc->sc_flags |= RTWN_RUNNING; 3280 3281 /* Init firmware commands ring. */ 3282 sc->fwcur = 0; 3283 3284 /* Power on adapter. */ 3285 error = rtwn_power_on(sc); 3286 if (error != 0) { 3287 device_printf(sc->sc_dev, "could not power on adapter\n"); 3288 goto fail; 3289 } 3290 3291 /* Initialize DMA. */ 3292 error = rtwn_dma_init(sc); 3293 if (error != 0) { 3294 device_printf(sc->sc_dev, "could not initialize DMA\n"); 3295 goto fail; 3296 } 3297 3298 /* Set info size in Rx descriptors (in 64-bit words). */ 3299 rtwn_write_1(sc, R92C_RX_DRVINFO_SZ, 4); 3300 3301 /* Disable interrupts. */ 3302 rtwn_write_4(sc, R92C_HISR, 0x00000000); 3303 rtwn_write_4(sc, R92C_HIMR, 0x00000000); 3304 3305 /* Set MAC address. */ 3306 IEEE80211_ADDR_COPY(macaddr, vap ? vap->iv_myaddr : ic->ic_macaddr); 3307 for (i = 0; i < IEEE80211_ADDR_LEN; i++) 3308 rtwn_write_1(sc, R92C_MACID + i, macaddr[i]); 3309 3310 /* Set initial network type. */ 3311 reg = rtwn_read_4(sc, R92C_CR); 3312 reg = RW(reg, R92C_CR_NETTYPE, R92C_CR_NETTYPE_INFRA); 3313 rtwn_write_4(sc, R92C_CR, reg); 3314 3315 rtwn_rxfilter_init(sc); 3316 3317 reg = rtwn_read_4(sc, R92C_RRSR); 3318 reg = RW(reg, R92C_RRSR_RATE_BITMAP, R92C_RRSR_RATE_ALL); 3319 rtwn_write_4(sc, R92C_RRSR, reg); 3320 3321 /* Set short/long retry limits. */ 3322 rtwn_write_2(sc, R92C_RL, 3323 SM(R92C_RL_SRL, 0x07) | SM(R92C_RL_LRL, 0x07)); 3324 3325 /* Initialize EDCA parameters. */ 3326 rtwn_edca_init(sc); 3327 3328 /* Set data and response automatic rate fallback retry counts. */ 3329 rtwn_write_4(sc, R92C_DARFRC + 0, 0x01000000); 3330 rtwn_write_4(sc, R92C_DARFRC + 4, 0x07060504); 3331 rtwn_write_4(sc, R92C_RARFRC + 0, 0x01000000); 3332 rtwn_write_4(sc, R92C_RARFRC + 4, 0x07060504); 3333 3334 rtwn_write_2(sc, R92C_FWHW_TXQ_CTRL, 0x1f80); 3335 3336 /* Set ACK timeout. */ 3337 rtwn_write_1(sc, R92C_ACKTO, 0x40); 3338 3339 /* Initialize beacon parameters. */ 3340 rtwn_write_2(sc, R92C_TBTT_PROHIBIT, 0x6404); 3341 rtwn_write_1(sc, R92C_DRVERLYINT, 0x05); 3342 rtwn_write_1(sc, R92C_BCNDMATIM, 0x02); 3343 rtwn_write_2(sc, R92C_BCNTCFG, 0x660f); 3344 3345 /* Setup AMPDU aggregation. */ 3346 rtwn_write_4(sc, R92C_AGGLEN_LMT, 0x99997631); /* MCS7~0 */ 3347 rtwn_write_1(sc, R92C_AGGR_BREAK_TIME, 0x16); 3348 3349 rtwn_write_1(sc, R92C_BCN_MAX_ERR, 0xff); 3350 rtwn_write_1(sc, R92C_BCN_CTRL, R92C_BCN_CTRL_DIS_TSF_UDT0); 3351 3352 rtwn_write_4(sc, R92C_PIFS, 0x1c); 3353 rtwn_write_4(sc, R92C_MCUTST_1, 0x0); 3354 3355 /* Load 8051 microcode. */ 3356 error = rtwn_load_firmware(sc); 3357 if (error != 0) 3358 goto fail; 3359 3360 /* Initialize MAC/BB/RF blocks. */ 3361 rtwn_mac_init(sc); 3362 rtwn_bb_init(sc); 3363 rtwn_rf_init(sc); 3364 3365 /* Turn CCK and OFDM blocks on. */ 3366 reg = rtwn_bb_read(sc, R92C_FPGA0_RFMOD); 3367 reg |= R92C_RFMOD_CCK_EN; 3368 rtwn_bb_write(sc, R92C_FPGA0_RFMOD, reg); 3369 reg = rtwn_bb_read(sc, R92C_FPGA0_RFMOD); 3370 reg |= R92C_RFMOD_OFDM_EN; 3371 rtwn_bb_write(sc, R92C_FPGA0_RFMOD, reg); 3372 3373 /* Clear per-station keys table. */ 3374 rtwn_cam_init(sc); 3375 3376 /* Enable hardware sequence numbering. */ 3377 rtwn_write_1(sc, R92C_HWSEQ_CTRL, 0xff); 3378 3379 /* Perform LO and IQ calibrations. */ 3380 rtwn_iq_calib(sc); 3381 /* Perform LC calibration. */ 3382 rtwn_lc_calib(sc); 3383 3384 rtwn_pa_bias_init(sc); 3385 3386 /* Initialize GPIO setting. */ 3387 rtwn_write_1(sc, R92C_GPIO_MUXCFG, 3388 rtwn_read_1(sc, R92C_GPIO_MUXCFG) & ~R92C_GPIO_MUXCFG_ENBT); 3389 3390 /* Fix for lower temperature. */ 3391 rtwn_write_1(sc, 0x15, 0xe9); 3392 3393 /* CLear pending interrupts. */ 3394 rtwn_write_4(sc, R92C_HISR, 0xffffffff); 3395 3396 /* Enable interrupts. */ 3397 rtwn_write_4(sc, R92C_HIMR, RTWN_INT_ENABLE); 3398 3399 callout_reset(&sc->watchdog_to, hz, rtwn_watchdog, sc); 3400 3401fail: 3402 if (error != 0) 3403 rtwn_stop_locked(sc); 3404 3405 RTWN_UNLOCK(sc); 3406 3407 return error; 3408} 3409 3410static void 3411rtwn_stop_locked(struct rtwn_softc *sc) 3412{ 3413 uint16_t reg; 3414 int i; 3415 3416 RTWN_LOCK_ASSERT(sc); 3417 3418 if (!(sc->sc_flags & RTWN_RUNNING)) 3419 return; 3420 3421 sc->sc_tx_timer = 0; 3422 callout_stop(&sc->watchdog_to); 3423 callout_stop(&sc->calib_to); 3424 sc->sc_flags &= ~RTWN_RUNNING; 3425 3426 /* Disable interrupts. */ 3427 rtwn_write_4(sc, R92C_HISR, 0x00000000); 3428 rtwn_write_4(sc, R92C_HIMR, 0x00000000); 3429 3430 /* Stop hardware. */ 3431 rtwn_write_1(sc, R92C_TXPAUSE, 0xff); 3432 rtwn_write_1(sc, R92C_RF_CTRL, 0x00); 3433 reg = rtwn_read_1(sc, R92C_SYS_FUNC_EN); 3434 reg |= R92C_SYS_FUNC_EN_BB_GLB_RST; 3435 rtwn_write_1(sc, R92C_SYS_FUNC_EN, reg); 3436 reg &= ~R92C_SYS_FUNC_EN_BB_GLB_RST; 3437 rtwn_write_1(sc, R92C_SYS_FUNC_EN, reg); 3438 reg = rtwn_read_2(sc, R92C_CR); 3439 reg &= ~(R92C_CR_HCI_TXDMA_EN | R92C_CR_HCI_RXDMA_EN | 3440 R92C_CR_TXDMA_EN | R92C_CR_RXDMA_EN | R92C_CR_PROTOCOL_EN | 3441 R92C_CR_SCHEDULE_EN | R92C_CR_MACTXEN | R92C_CR_MACRXEN | 3442 R92C_CR_ENSEC); 3443 rtwn_write_2(sc, R92C_CR, reg); 3444 if (rtwn_read_1(sc, R92C_MCUFWDL) & R92C_MCUFWDL_RAM_DL_SEL) 3445 rtwn_fw_reset(sc); 3446 /* TODO: linux does additional btcoex stuff here */ 3447 rtwn_write_2(sc, R92C_AFE_PLL_CTRL, 0x80); /* linux magic number */ 3448 rtwn_write_1(sc, R92C_SPS0_CTRL, 0x23); /* ditto */ 3449 rtwn_write_1(sc, R92C_AFE_XTAL_CTRL, 0x0e); /* different with btcoex */ 3450 rtwn_write_1(sc, R92C_RSV_CTRL, 0x0e); 3451 rtwn_write_1(sc, R92C_APS_FSMCO, R92C_APS_FSMCO_PDN_EN); 3452 3453 for (i = 0; i < RTWN_NTXQUEUES; i++) 3454 rtwn_reset_tx_list(sc, i); 3455 rtwn_reset_rx_list(sc); 3456} 3457 3458static void 3459rtwn_stop(struct rtwn_softc *sc) 3460{ 3461 RTWN_LOCK(sc); 3462 rtwn_stop_locked(sc); 3463 RTWN_UNLOCK(sc); 3464} 3465 3466static void 3467rtwn_intr(void *arg) 3468{ 3469 struct rtwn_softc *sc = arg; 3470 uint32_t status; 3471 int i; 3472 3473 RTWN_LOCK(sc); 3474 status = rtwn_read_4(sc, R92C_HISR); 3475 if (status == 0 || status == 0xffffffff) { 3476 RTWN_UNLOCK(sc); 3477 return; 3478 } 3479 3480 /* Disable interrupts. */ 3481 rtwn_write_4(sc, R92C_HIMR, 0x00000000); 3482 3483 /* Ack interrupts. */ 3484 rtwn_write_4(sc, R92C_HISR, status); 3485 3486 /* Vendor driver treats RX errors like ROK... */ 3487 if (status & (R92C_IMR_ROK | R92C_IMR_RXFOVW | R92C_IMR_RDU)) { 3488 bus_dmamap_sync(sc->rx_ring.desc_dmat, sc->rx_ring.desc_map, 3489 BUS_DMASYNC_POSTREAD); 3490 3491 for (i = 0; i < RTWN_RX_LIST_COUNT; i++) { 3492 struct r92c_rx_desc *rx_desc = &sc->rx_ring.desc[i]; 3493 struct rtwn_rx_data *rx_data = &sc->rx_ring.rx_data[i]; 3494 3495 if (le32toh(rx_desc->rxdw0) & R92C_RXDW0_OWN) 3496 continue; 3497 3498 rtwn_rx_frame(sc, rx_desc, rx_data, i); 3499 } 3500 } 3501 3502 if (status & R92C_IMR_BDOK) 3503 rtwn_tx_done(sc, RTWN_BEACON_QUEUE); 3504 if (status & R92C_IMR_HIGHDOK) 3505 rtwn_tx_done(sc, RTWN_HIGH_QUEUE); 3506 if (status & R92C_IMR_MGNTDOK) 3507 rtwn_tx_done(sc, RTWN_MGNT_QUEUE); 3508 if (status & R92C_IMR_BKDOK) 3509 rtwn_tx_done(sc, RTWN_BK_QUEUE); 3510 if (status & R92C_IMR_BEDOK) 3511 rtwn_tx_done(sc, RTWN_BE_QUEUE); 3512 if (status & R92C_IMR_VIDOK) 3513 rtwn_tx_done(sc, RTWN_VI_QUEUE); 3514 if (status & R92C_IMR_VODOK) 3515 rtwn_tx_done(sc, RTWN_VO_QUEUE); 3516 3517 /* Enable interrupts. */ 3518 rtwn_write_4(sc, R92C_HIMR, RTWN_INT_ENABLE); 3519 3520 RTWN_UNLOCK(sc); 3521} 3522