/linux-master/drivers/clk/starfive/ |
H A D | clk-starfive-jh7110-pll.c | 17 * M: frequency dividing ratio of pre-divider, set by prediv[5:0]. 84 unsigned prediv : 6; member in struct:jh7110_pll_preset 97 unsigned int prediv; member in struct:jh7110_pll_info::__anon200 120 .prediv = JH7110_PLL##_idx##_PREDIV_OFFSET, \ 152 u32 prediv; member in struct:jh7110_pll_regvals 164 .prediv = 8, 170 .prediv = 6, 176 .prediv = 24, 182 .prediv = 4, 188 .prediv [all...] |
/linux-master/drivers/clk/mmp/ |
H A D | clk-audio.c | 120 unsigned int prediv; local 137 for (prediv = 0; prediv < ARRAY_SIZE(predivs); prediv++) { 138 if (predivs[prediv].parent_rate != parent_rate) 147 val |= SSPA_AUD_PLL_CTRL0_FRACT(predivs[prediv].fract); 148 val |= SSPA_AUD_PLL_CTRL0_DIV_FBCCLK(predivs[prediv].fbcclk); 149 val |= SSPA_AUD_PLL_CTRL0_DIV_MCLK(predivs[prediv].mclk); 158 freq = predivs[prediv].freq_vco; 170 unsigned int prediv; local 198 unsigned int prediv; local [all...] |
/linux-master/drivers/clk/sunxi-ng/ |
H A D | ccu_gate.c | 85 rate /= cg->common.prediv; 97 div = cg->common.prediv;
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H A D | ccu_gate.h | 77 .prediv = _prediv, \ 105 .prediv = _prediv, \
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H A D | ccu_common.h | 32 u32 prediv; member in struct:ccu_common
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H A D | ccu_mux.c | 21 u16 prediv = 1; local 30 return common->prediv; 43 prediv = cm->fixed_predivs[i].div; 55 prediv = div + 1; 59 return prediv;
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H A D | ccu-sun6i-rtc.c | 229 .prediv = 750,
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H A D | ccu-sun5i.c | 90 .prediv = 8, 164 .prediv = 8,
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/linux-master/drivers/media/dvb-frontends/ |
H A D | tua6100.c | 62 u32 prediv; local 105 prediv = (c->frequency * _R_VAL) / (_ri / 1000); 106 div = prediv / _P_VAL; 113 reg1[3] |= (prediv - (div*_P_VAL)) & 0x7f;
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H A D | dib7000p.c | 493 u8 loopdiv, prediv; local 497 prediv = reg_1856 & 0x3f; 500 if (loopdiv && bw && (bw->pll_prediv != prediv || bw->pll_ratio != loopdiv)) { 501 dprintk("Updating pll (prediv: old = %d new = %d ; loopdiv : old = %d new = %d)\n", prediv, bw->pll_prediv, loopdiv, bw->pll_ratio); 510 xtal = (internal / loopdiv) * prediv;
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/linux-master/drivers/clk/keystone/ |
H A D | pll.c | 81 u32 mult = 0, prediv, postdiv, val; local 96 prediv = (val & pll_data->plld_mask); 109 rate /= (prediv + 1);
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/linux-master/drivers/clk/imx/ |
H A D | clk-composite-8m.c | 52 int *prediv, int *postdiv) 58 *prediv = 1; 66 *prediv = div1; 50 imx8m_clk_composite_compute_dividers(unsigned long rate, unsigned long parent_rate, int *prediv, int *postdiv) argument
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/linux-master/drivers/clk/ |
H A D | clk-vt8500.c | 351 u32 *multiplier, u32 *prediv) 359 *prediv = 1; 363 /* use the prediv to double the resolution */ 364 *prediv = 2; 366 *prediv = 1; 368 *multiplier = rate / (parent_rate / *prediv); 369 tclk = (parent_rate / *prediv) * *multiplier; 350 vt8500_find_pll_bits(unsigned long rate, unsigned long parent_rate, u32 *multiplier, u32 *prediv) argument
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H A D | clk-versaclock3.c | 244 unsigned int prediv, premul; local 248 regmap_read(vc3->regmap, pfd->offs, &prediv); 251 if (prediv & pfd->mdiv1_bitmsk) { 258 mdiv = VC3_PLL1_M_DIV(prediv); 261 if (prediv & pfd->mdiv1_bitmsk) { 269 mdiv = VC3_PLL2_M_DIV(prediv); 272 if (prediv & pfd->mdiv1_bitmsk) 275 mdiv = VC3_PLL3_M_DIV(prediv); 278 if (prediv & pfd->mdiv2_bitmsk)
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H A D | clk-versaclock5.c | 344 unsigned int prediv, div; local 347 ret = regmap_read(vc5->regmap, VC5_VCO_CTRL_AND_PREDIV, &prediv); 352 if (prediv & VC5_VCO_CTRL_AND_PREDIV_BYPASS_PREDIV)
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/linux-master/drivers/clk/pistachio/ |
H A D | clk-pll.c | 273 u64 val, prediv, fbdiv, frac, postdiv1, postdiv2, rate; local 276 prediv = (val >> PLL_CTRL1_REFDIV_SHIFT) & PLL_CTRL1_REFDIV_MASK; 293 rate = do_div_round_closest(rate, (prediv * postdiv1 * postdiv2) << 24); 413 u32 val, prediv, fbdiv, postdiv1, postdiv2; local 417 prediv = (val >> PLL_CTRL1_REFDIV_SHIFT) & PLL_CTRL1_REFDIV_MASK; 425 rate = do_div_round_closest(rate, prediv * postdiv1 * postdiv2);
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/linux-master/drivers/media/i2c/ |
H A D | tc358746.c | 880 dev_dbg(dev, "Found PLL settings: freq:%lu prediv:%u multi:%u postdiv:%u\n", 1100 const unsigned char prediv[] = { 2, 4, 8 }; local 1139 /* First check the prediv */ 1140 for (i = 0; i < ARRAY_SIZE(prediv); i++) { 1141 postdiv = mclkdiv / prediv[i]; 1147 mclk_prediv = prediv[i]; 1149 best_mclk_rate = pll_rate / (prediv[i] * postdiv); 1154 /* No suitable prediv found, so try to adjust the postdiv */ 1181 dev_dbg(dev, "Found MCLK settings: freq:%lu prediv:%u postdiv:%u\n", 1191 unsigned int prediv, postdi local [all...] |
H A D | st-vgxy61.c | 457 static void compute_pll_parameters_by_freq(u32 freq, u8 *prediv, u8 *mult) argument 467 *prediv = predivs[i]; 468 if (freq / *prediv < 12 * HZ_PER_MHZ) 477 *mult = ((804 * HZ_PER_MHZ) * (*prediv) + freq / 2) / freq; 1497 u8 prediv, mult; local 1501 compute_pll_parameters_by_freq(sensor->clk_freq, &prediv, &mult); 1502 sensor_freq = (mult * sensor->clk_freq) / prediv; 1513 cci_write(sensor->regmap, VGXY61_REG_CLK_PLL_PREDIV, prediv, &ret);
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H A D | ov5640.c | 1457 u8 prediv, mult, sysdiv; local 1480 ov5640_calc_sys_clk(sensor, sysclk, &prediv, &mult, &sysdiv); 1538 root_div | prediv); 1581 u8 prediv, mult, sysdiv, pll_rdiv, bit_div, pclk_div; local 1589 ov5640_calc_pclk(sensor, rate, &prediv, &mult, &sysdiv, &pll_rdiv, 1615 0x1f, prediv | ((pll_rdiv - 1) << 4)); 1862 u32 multiplier, prediv, VCO, sysdiv, pll_rdiv; local 1890 prediv = temp1 & 0x0f; 1899 if (!prediv || !sysdiv || !pll_rdiv || !bit_div2x) 1902 VCO = xvclk * multiplier / prediv; [all...] |
H A D | ov2659.c | 897 u32 prediv, postdiv, mult; local 905 prediv = ctrl3[j].div; 909 actual /= prediv;
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/linux-master/drivers/phy/rockchip/ |
H A D | phy-rockchip-inno-hdmi.c | 253 u8 prediv; member in struct:pre_pll_config 268 u8 prediv; member in struct:post_pll_config 799 RK3228_PRE_PLL_PRE_DIV(cfg->prediv)); 953 inno_write(inno, 0xa1, RK3328_PRE_PLL_PRE_DIV(cfg->prediv)); 1071 RK3228_POST_PLL_PRE_DIV(cfg->prediv)); 1184 RK3328_POST_PLL_PRE_DIV(cfg->prediv)); 1192 RK3328_POST_PLL_PRE_DIV(cfg->prediv));
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H A D | phy-rockchip-inno-dsidphy.c | 220 u8 prediv; member in struct:inno_dsidphy::__anon40 318 /* 5Mhz < Fref / prediv < 40MHz */ 358 inno->pll.prediv = best_prediv; 385 REG_PREDIV_MASK, REG_PREDIV(inno->pll.prediv)); 529 u8 prediv = 2; local 543 REG_PREDIV_MASK, REG_PREDIV(prediv));
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/linux-master/drivers/clk/ralink/ |
H A D | clk-mt7621.c | 262 u32 pll, prediv, fbdiv; local 279 prediv = FIELD_GET(CPU_PLL_PREDIV_MASK, pll); 280 cpu_clk = ((fbdiv + 1) * xtal_clk) >> prediv_tbl[prediv];
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/linux-master/drivers/media/usb/dvb-usb/ |
H A D | dib0700_devices.c | 2035 u8 spur = 0, prediv = 0, loopdiv = 0, min_prediv = 1, max_prediv = 1; local 2046 adc->pll_prediv = prediv; 2050 /* Find Min and Max prediv */ 2061 deb_info("MIN prediv = %d : MAX prediv = %d", min_prediv, max_prediv); 2065 for (prediv = min_prediv; prediv < max_prediv; prediv++) { 2066 fcp = xtal / prediv; 2069 fmem = ((xtal/prediv) * loopdi 2548 u8 spur = 0, prediv = 0, loopdiv = 0, min_prediv = 1, max_prediv = 1; local [all...] |
/linux-master/drivers/phy/mediatek/ |
H A D | phy-mtk-hdmi-mt8195.c | 74 static int mtk_hdmi_pll_set_hw(struct clk_hw *hw, u8 prediv, argument 183 prediv_value = ilog2(prediv);
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