1// SPDX-License-Identifier: GPL-2.0 2/* 3 * Copyright (c) 2022 MediaTek Inc. 4 * Copyright (c) 2022 BayLibre, SAS 5 */ 6#include <linux/delay.h> 7#include <linux/io.h> 8#include <linux/mfd/syscon.h> 9#include <linux/module.h> 10#include <linux/phy/phy.h> 11#include <linux/platform_device.h> 12#include <linux/types.h> 13#include <linux/units.h> 14#include <linux/nvmem-consumer.h> 15 16#include "phy-mtk-io.h" 17#include "phy-mtk-hdmi.h" 18#include "phy-mtk-hdmi-mt8195.h" 19 20static void mtk_hdmi_ana_fifo_en(struct mtk_hdmi_phy *hdmi_phy) 21{ 22 /* make data fifo writable for hdmi2.0 */ 23 mtk_phy_set_bits(hdmi_phy->regs + HDMI_ANA_CTL, REG_ANA_HDMI20_FIFO_EN); 24} 25 26static void 27mtk_phy_tmds_clk_ratio(struct mtk_hdmi_phy *hdmi_phy, bool enable) 28{ 29 void __iomem *regs = hdmi_phy->regs; 30 31 mtk_hdmi_ana_fifo_en(hdmi_phy); 32 33 /* HDMI 2.0 specification, 3.4Gbps <= TMDS Bit Rate <= 6G, 34 * clock bit ratio 1:40, under 3.4Gbps, clock bit ratio 1:10 35 */ 36 if (enable) 37 mtk_phy_update_field(regs + HDMI20_CLK_CFG, REG_TXC_DIV, 3); 38 else 39 mtk_phy_clear_bits(regs + HDMI20_CLK_CFG, REG_TXC_DIV); 40} 41 42static void mtk_hdmi_pll_sel_src(struct clk_hw *hw) 43{ 44 struct mtk_hdmi_phy *hdmi_phy = to_mtk_hdmi_phy(hw); 45 void __iomem *regs = hdmi_phy->regs; 46 47 mtk_phy_clear_bits(regs + HDMI_CTL_3, REG_HDMITX_REF_XTAL_SEL); 48 mtk_phy_clear_bits(regs + HDMI_CTL_3, REG_HDMITX_REF_RESPLL_SEL); 49 50 /* DA_HDMITX21_REF_CK for TXPLL input source */ 51 mtk_phy_clear_bits(regs + HDMI_1_CFG_10, RG_HDMITXPLL_REF_CK_SEL); 52} 53 54static void mtk_hdmi_pll_perf(struct clk_hw *hw) 55{ 56 struct mtk_hdmi_phy *hdmi_phy = to_mtk_hdmi_phy(hw); 57 void __iomem *regs = hdmi_phy->regs; 58 59 mtk_phy_set_bits(regs + HDMI_1_PLL_CFG_0, RG_HDMITXPLL_BP2); 60 mtk_phy_set_bits(regs + HDMI_1_PLL_CFG_2, RG_HDMITXPLL_BC); 61 mtk_phy_update_field(regs + HDMI_1_PLL_CFG_2, RG_HDMITXPLL_IC, 0x1); 62 mtk_phy_update_field(regs + HDMI_1_PLL_CFG_2, RG_HDMITXPLL_BR, 0x2); 63 mtk_phy_update_field(regs + HDMI_1_PLL_CFG_2, RG_HDMITXPLL_IR, 0x2); 64 mtk_phy_set_bits(regs + HDMI_1_PLL_CFG_2, RG_HDMITXPLL_BP); 65 mtk_phy_clear_bits(regs + HDMI_1_PLL_CFG_0, RG_HDMITXPLL_IBAND_FIX_EN); 66 mtk_phy_clear_bits(regs + HDMI_1_PLL_CFG_1, RG_HDMITXPLL_RESERVE_BIT14); 67 mtk_phy_clear_bits(regs + HDMI_1_PLL_CFG_2, RG_HDMITXPLL_HIKVCO); 68 mtk_phy_update_field(regs + HDMI_1_PLL_CFG_0, RG_HDMITXPLL_HREN, 0x1); 69 mtk_phy_update_field(regs + HDMI_1_PLL_CFG_0, RG_HDMITXPLL_LVR_SEL, 0x1); 70 mtk_phy_set_bits(regs + HDMI_1_PLL_CFG_1, RG_HDMITXPLL_RESERVE_BIT12_11); 71 mtk_phy_set_bits(regs + HDMI_1_PLL_CFG_0, RG_HDMITXPLL_TCL_EN); 72} 73 74static int mtk_hdmi_pll_set_hw(struct clk_hw *hw, u8 prediv, 75 u8 fbkdiv_high, 76 u32 fbkdiv_low, 77 u8 fbkdiv_hs3, u8 posdiv1, 78 u8 posdiv2, u8 txprediv, 79 u8 txposdiv, 80 u8 digital_div) 81{ 82 u8 txposdiv_value; 83 u8 div3_ctrl_value; 84 u8 posdiv_vallue; 85 u8 div_ctrl_value; 86 u8 reserve_3_2_value; 87 u8 prediv_value; 88 u8 reserve13_value; 89 struct mtk_hdmi_phy *hdmi_phy = to_mtk_hdmi_phy(hw); 90 void __iomem *regs = hdmi_phy->regs; 91 92 mtk_hdmi_pll_sel_src(hw); 93 94 mtk_hdmi_pll_perf(hw); 95 96 mtk_phy_update_field(regs + HDMI_1_CFG_10, RG_HDMITX21_BIAS_PE_BG_VREF_SEL, 0x2); 97 mtk_phy_clear_bits(regs + HDMI_1_CFG_10, RG_HDMITX21_VREF_SEL); 98 mtk_phy_update_field(regs + HDMI_1_CFG_9, RG_HDMITX21_SLDO_VREF_SEL, 0x2); 99 mtk_phy_clear_bits(regs + HDMI_1_CFG_10, RG_HDMITX21_BIAS_PE_VREF_SELB); 100 mtk_phy_set_bits(regs + HDMI_1_CFG_3, RG_HDMITX21_SLDOLPF_EN); 101 mtk_phy_update_field(regs + HDMI_1_CFG_6, RG_HDMITX21_INTR_CAL, 0x11); 102 mtk_phy_set_bits(regs + HDMI_1_PLL_CFG_2, RG_HDMITXPLL_PWD); 103 104 /* TXPOSDIV */ 105 txposdiv_value = ilog2(txposdiv); 106 107 mtk_phy_update_field(regs + HDMI_1_CFG_6, RG_HDMITX21_TX_POSDIV, txposdiv_value); 108 mtk_phy_set_bits(regs + HDMI_1_CFG_6, RG_HDMITX21_TX_POSDIV_EN); 109 mtk_phy_clear_bits(regs + HDMI_1_CFG_6, RG_HDMITX21_FRL_EN); 110 111 /* TXPREDIV */ 112 switch (txprediv) { 113 case 2: 114 div3_ctrl_value = 0x0; 115 posdiv_vallue = 0x0; 116 break; 117 case 4: 118 div3_ctrl_value = 0x0; 119 posdiv_vallue = 0x1; 120 break; 121 case 6: 122 div3_ctrl_value = 0x1; 123 posdiv_vallue = 0x0; 124 break; 125 case 12: 126 div3_ctrl_value = 0x1; 127 posdiv_vallue = 0x1; 128 break; 129 default: 130 return -EINVAL; 131 } 132 133 mtk_phy_update_field(regs + HDMI_1_PLL_CFG_4, RG_HDMITXPLL_POSDIV_DIV3_CTRL, div3_ctrl_value); 134 mtk_phy_update_field(regs + HDMI_1_PLL_CFG_4, RG_HDMITXPLL_POSDIV, posdiv_vallue); 135 136 /* POSDIV1 */ 137 switch (posdiv1) { 138 case 5: 139 div_ctrl_value = 0x0; 140 break; 141 case 10: 142 div_ctrl_value = 0x1; 143 break; 144 case 12: 145 div_ctrl_value = 0x2; 146 break; 147 case 15: 148 div_ctrl_value = 0x3; 149 break; 150 default: 151 return -EINVAL; 152 } 153 154 mtk_phy_update_field(regs + HDMI_1_PLL_CFG_4, RG_HDMITXPLL_DIV_CTRL, div_ctrl_value); 155 156 /* DE add new setting */ 157 mtk_phy_clear_bits(regs + HDMI_1_PLL_CFG_1, RG_HDMITXPLL_RESERVE_BIT14); 158 159 /* POSDIV2 */ 160 switch (posdiv2) { 161 case 1: 162 reserve_3_2_value = 0x0; 163 break; 164 case 2: 165 reserve_3_2_value = 0x1; 166 break; 167 case 4: 168 reserve_3_2_value = 0x2; 169 break; 170 case 6: 171 reserve_3_2_value = 0x3; 172 break; 173 default: 174 return -EINVAL; 175 } 176 177 mtk_phy_update_field(regs + HDMI_1_PLL_CFG_1, RG_HDMITXPLL_RESERVE_BIT3_2, reserve_3_2_value); 178 179 /* DE add new setting */ 180 mtk_phy_update_field(regs + HDMI_1_PLL_CFG_1, RG_HDMITXPLL_RESERVE_BIT1_0, 0x2); 181 182 /* PREDIV */ 183 prediv_value = ilog2(prediv); 184 185 mtk_phy_update_field(regs + HDMI_1_PLL_CFG_4, RG_HDMITXPLL_PREDIV, prediv_value); 186 187 /* FBKDIV_HS3 */ 188 reserve13_value = ilog2(fbkdiv_hs3); 189 190 mtk_phy_update_field(regs + HDMI_1_PLL_CFG_1, RG_HDMITXPLL_RESERVE_BIT13, reserve13_value); 191 192 /* FBDIV */ 193 mtk_phy_update_field(regs + HDMI_1_PLL_CFG_4, RG_HDMITXPLL_FBKDIV_HIGH, fbkdiv_high); 194 mtk_phy_update_field(regs + HDMI_1_PLL_CFG_3, RG_HDMITXPLL_FBKDIV_LOW, fbkdiv_low); 195 196 /* Digital DIVIDER */ 197 mtk_phy_clear_bits(regs + HDMI_CTL_3, REG_PIXEL_CLOCK_SEL); 198 199 if (digital_div == 1) { 200 mtk_phy_clear_bits(regs + HDMI_CTL_3, REG_HDMITX_PIXEL_CLOCK); 201 } else { 202 mtk_phy_set_bits(regs + HDMI_CTL_3, REG_HDMITX_PIXEL_CLOCK); 203 mtk_phy_update_field(regs + HDMI_CTL_3, REG_HDMITXPLL_DIV, digital_div - 1); 204 } 205 206 return 0; 207} 208 209static int mtk_hdmi_pll_calc(struct mtk_hdmi_phy *hdmi_phy, struct clk_hw *hw, 210 unsigned long rate, unsigned long parent_rate) 211{ 212 u8 digital_div, txprediv, txposdiv, fbkdiv_high, posdiv1, posdiv2; 213 u64 tmds_clk, pixel_clk, da_hdmitx21_ref_ck, ns_hdmipll_ck, pcw; 214 u8 txpredivs[4] = { 2, 4, 6, 12 }; 215 u32 fbkdiv_low; 216 int i; 217 218 pixel_clk = rate; 219 tmds_clk = pixel_clk; 220 221 if (tmds_clk < 25 * MEGA || tmds_clk > 594 * MEGA) 222 return -EINVAL; 223 224 if (tmds_clk >= 340 * MEGA) 225 hdmi_phy->tmds_over_340M = true; 226 else 227 hdmi_phy->tmds_over_340M = false; 228 229 /* in Hz */ 230 da_hdmitx21_ref_ck = 26 * MEGA; 231 232 /* TXPOSDIV stage treatment: 233 * 0M < TMDS clk < 54M /8 234 * 54M <= TMDS clk < 148.35M /4 235 * 148.35M <=TMDS clk < 296.7M /2 236 * 296.7 <=TMDS clk <= 594M /1 237 */ 238 if (tmds_clk < 54 * MEGA) 239 txposdiv = 8; 240 else if (tmds_clk >= 54 * MEGA && (tmds_clk * 100) < 14835 * MEGA) 241 txposdiv = 4; 242 else if ((tmds_clk * 100) >= 14835 * MEGA && (tmds_clk * 10) < 2967 * MEGA) 243 txposdiv = 2; 244 else if ((tmds_clk * 10) >= 2967 * MEGA && tmds_clk <= 594 * MEGA) 245 txposdiv = 1; 246 else 247 return -EINVAL; 248 249 /* calculate txprediv: can be 2, 4, 6, 12 250 * ICO clk = 5*TMDS_CLK*TXPOSDIV*TXPREDIV 251 * ICO clk constraint: 5G =< ICO clk <= 12G 252 */ 253 for (i = 0; i < ARRAY_SIZE(txpredivs); i++) { 254 ns_hdmipll_ck = 5 * tmds_clk * txposdiv * txpredivs[i]; 255 if (ns_hdmipll_ck >= 5 * GIGA && 256 ns_hdmipll_ck <= 12 * GIGA) 257 break; 258 } 259 if (i == (ARRAY_SIZE(txpredivs) - 1) && 260 (ns_hdmipll_ck < 5 * GIGA || ns_hdmipll_ck > 12 * GIGA)) { 261 return -EINVAL; 262 } 263 if (i == ARRAY_SIZE(txpredivs)) 264 return -EINVAL; 265 266 txprediv = txpredivs[i]; 267 268 /* PCW calculation: FBKDIV 269 * formula: pcw=(frequency_out*2^pcw_bit) / frequency_in / FBKDIV_HS3; 270 * RG_HDMITXPLL_FBKDIV[32:0]: 271 * [32,24] 9bit integer, [23,0]:24bit fraction 272 */ 273 pcw = div_u64(((u64)ns_hdmipll_ck) << PCW_DECIMAL_WIDTH, 274 da_hdmitx21_ref_ck * PLL_FBKDIV_HS3); 275 276 if (pcw > GENMASK_ULL(32, 0)) 277 return -EINVAL; 278 279 fbkdiv_high = FIELD_GET(GENMASK_ULL(63, 32), pcw); 280 fbkdiv_low = FIELD_GET(GENMASK(31, 0), pcw); 281 282 /* posdiv1: 283 * posdiv1 stage treatment according to color_depth: 284 * 24bit -> posdiv1 /10, 30bit -> posdiv1 /12.5, 285 * 36bit -> posdiv1 /15, 48bit -> posdiv1 /10 286 */ 287 posdiv1 = 10; 288 posdiv2 = 1; 289 290 /* Digital clk divider, max /32 */ 291 digital_div = div_u64(ns_hdmipll_ck, posdiv1 * posdiv2 * pixel_clk); 292 if (!(digital_div <= 32 && digital_div >= 1)) 293 return -EINVAL; 294 295 return mtk_hdmi_pll_set_hw(hw, PLL_PREDIV, fbkdiv_high, fbkdiv_low, 296 PLL_FBKDIV_HS3, posdiv1, posdiv2, txprediv, 297 txposdiv, digital_div); 298} 299 300static int mtk_hdmi_pll_drv_setting(struct clk_hw *hw) 301{ 302 struct mtk_hdmi_phy *hdmi_phy = to_mtk_hdmi_phy(hw); 303 void __iomem *regs = hdmi_phy->regs; 304 u8 data_channel_bias, clk_channel_bias; 305 u8 impedance, impedance_en; 306 u32 tmds_clk; 307 u32 pixel_clk = hdmi_phy->pll_rate; 308 309 tmds_clk = pixel_clk; 310 311 /* bias & impedance setting: 312 * 3G < data rate <= 6G: enable impedance 100ohm, 313 * data channel bias 24mA, clock channel bias 20mA 314 * pixel clk >= HD, 74.175MHZ <= pixel clk <= 300MHZ: 315 * enalbe impedance 100ohm 316 * data channel 20mA, clock channel 16mA 317 * 27M =< pixel clk < 74.175: disable impedance 318 * data channel & clock channel bias 10mA 319 */ 320 321 /* 3G < data rate <= 6G, 300M < tmds rate <= 594M */ 322 if (tmds_clk > 300 * MEGA && tmds_clk <= 594 * MEGA) { 323 data_channel_bias = 0x3c; /* 24mA */ 324 clk_channel_bias = 0x34; /* 20mA */ 325 impedance_en = 0xf; 326 impedance = 0x36; /* 100ohm */ 327 } else if (((u64)pixel_clk * 1000) >= 74175 * MEGA && pixel_clk <= 300 * MEGA) { 328 data_channel_bias = 0x34; /* 20mA */ 329 clk_channel_bias = 0x2c; /* 16mA */ 330 impedance_en = 0xf; 331 impedance = 0x36; /* 100ohm */ 332 } else if (pixel_clk >= 27 * MEGA && ((u64)pixel_clk * 1000) < 74175 * MEGA) { 333 data_channel_bias = 0x14; /* 10mA */ 334 clk_channel_bias = 0x14; /* 10mA */ 335 impedance_en = 0x0; 336 impedance = 0x0; 337 } else { 338 return -EINVAL; 339 } 340 341 /* bias */ 342 mtk_phy_update_field(regs + HDMI_1_CFG_1, RG_HDMITX21_DRV_IBIAS_D0, data_channel_bias); 343 mtk_phy_update_field(regs + HDMI_1_CFG_1, RG_HDMITX21_DRV_IBIAS_D1, data_channel_bias); 344 mtk_phy_update_field(regs + HDMI_1_CFG_1, RG_HDMITX21_DRV_IBIAS_D2, data_channel_bias); 345 mtk_phy_update_field(regs + HDMI_1_CFG_0, RG_HDMITX21_DRV_IBIAS_CLK, clk_channel_bias); 346 347 /* impedance */ 348 mtk_phy_update_field(regs + HDMI_1_CFG_0, RG_HDMITX21_DRV_IMP_EN, impedance_en); 349 mtk_phy_update_field(regs + HDMI_1_CFG_2, RG_HDMITX21_DRV_IMP_D0_EN1, impedance); 350 mtk_phy_update_field(regs + HDMI_1_CFG_2, RG_HDMITX21_DRV_IMP_D1_EN1, impedance); 351 mtk_phy_update_field(regs + HDMI_1_CFG_2, RG_HDMITX21_DRV_IMP_D2_EN1, impedance); 352 mtk_phy_update_field(regs + HDMI_1_CFG_2, RG_HDMITX21_DRV_IMP_CLK_EN1, impedance); 353 354 return 0; 355} 356 357static int mtk_hdmi_pll_prepare(struct clk_hw *hw) 358{ 359 struct mtk_hdmi_phy *hdmi_phy = to_mtk_hdmi_phy(hw); 360 void __iomem *regs = hdmi_phy->regs; 361 362 mtk_phy_set_bits(regs + HDMI_1_CFG_6, RG_HDMITX21_TX_POSDIV_EN); 363 364 mtk_phy_set_bits(regs + HDMI_1_CFG_0, RG_HDMITX21_SER_EN); 365 mtk_phy_set_bits(regs + HDMI_1_CFG_6, RG_HDMITX21_D0_DRV_OP_EN); 366 mtk_phy_set_bits(regs + HDMI_1_CFG_6, RG_HDMITX21_D1_DRV_OP_EN); 367 mtk_phy_set_bits(regs + HDMI_1_CFG_6, RG_HDMITX21_D2_DRV_OP_EN); 368 mtk_phy_set_bits(regs + HDMI_1_CFG_6, RG_HDMITX21_CK_DRV_OP_EN); 369 370 mtk_phy_clear_bits(regs + HDMI_1_CFG_6, RG_HDMITX21_FRL_D0_EN); 371 mtk_phy_clear_bits(regs + HDMI_1_CFG_6, RG_HDMITX21_FRL_D1_EN); 372 mtk_phy_clear_bits(regs + HDMI_1_CFG_6, RG_HDMITX21_FRL_D2_EN); 373 mtk_phy_clear_bits(regs + HDMI_1_CFG_6, RG_HDMITX21_FRL_CK_EN); 374 375 mtk_hdmi_pll_drv_setting(hw); 376 377 mtk_phy_clear_bits(regs + HDMI_1_CFG_10, RG_HDMITX21_BG_PWD); 378 mtk_phy_set_bits(regs + HDMI_1_CFG_6, RG_HDMITX21_BIAS_EN); 379 mtk_phy_set_bits(regs + HDMI_1_CFG_3, RG_HDMITX21_CKLDO_EN); 380 mtk_phy_set_bits(regs + HDMI_1_CFG_3, RG_HDMITX21_SLDO_EN); 381 382 mtk_phy_set_bits(regs + HDMI_1_PLL_CFG_4, DA_HDMITXPLL_PWR_ON); 383 usleep_range(5, 10); 384 mtk_phy_clear_bits(regs + HDMI_1_PLL_CFG_4, DA_HDMITXPLL_ISO_EN); 385 usleep_range(5, 10); 386 mtk_phy_clear_bits(regs + HDMI_1_PLL_CFG_2, RG_HDMITXPLL_PWD); 387 usleep_range(30, 50); 388 return 0; 389} 390 391static void mtk_hdmi_pll_unprepare(struct clk_hw *hw) 392{ 393 struct mtk_hdmi_phy *hdmi_phy = to_mtk_hdmi_phy(hw); 394 void __iomem *regs = hdmi_phy->regs; 395 396 mtk_phy_set_bits(regs + HDMI_1_CFG_10, RG_HDMITX21_BG_PWD); 397 mtk_phy_clear_bits(regs + HDMI_1_CFG_6, RG_HDMITX21_BIAS_EN); 398 mtk_phy_clear_bits(regs + HDMI_1_CFG_3, RG_HDMITX21_CKLDO_EN); 399 mtk_phy_clear_bits(regs + HDMI_1_CFG_3, RG_HDMITX21_SLDO_EN); 400 401 mtk_phy_set_bits(regs + HDMI_1_PLL_CFG_2, RG_HDMITXPLL_PWD); 402 usleep_range(10, 20); 403 mtk_phy_set_bits(regs + HDMI_1_PLL_CFG_4, DA_HDMITXPLL_ISO_EN); 404 usleep_range(10, 20); 405 mtk_phy_clear_bits(regs + HDMI_1_PLL_CFG_4, DA_HDMITXPLL_PWR_ON); 406} 407 408static int mtk_hdmi_pll_set_rate(struct clk_hw *hw, unsigned long rate, 409 unsigned long parent_rate) 410{ 411 struct mtk_hdmi_phy *hdmi_phy = to_mtk_hdmi_phy(hw); 412 413 dev_dbg(hdmi_phy->dev, "%s: %lu Hz, parent: %lu Hz\n", __func__, rate, 414 parent_rate); 415 416 return mtk_hdmi_pll_calc(hdmi_phy, hw, rate, parent_rate); 417} 418 419static long mtk_hdmi_pll_round_rate(struct clk_hw *hw, unsigned long rate, 420 unsigned long *parent_rate) 421{ 422 struct mtk_hdmi_phy *hdmi_phy = to_mtk_hdmi_phy(hw); 423 424 hdmi_phy->pll_rate = rate; 425 return rate; 426} 427 428static unsigned long mtk_hdmi_pll_recalc_rate(struct clk_hw *hw, 429 unsigned long parent_rate) 430{ 431 struct mtk_hdmi_phy *hdmi_phy = to_mtk_hdmi_phy(hw); 432 433 return hdmi_phy->pll_rate; 434} 435 436static const struct clk_ops mtk_hdmi_pll_ops = { 437 .prepare = mtk_hdmi_pll_prepare, 438 .unprepare = mtk_hdmi_pll_unprepare, 439 .set_rate = mtk_hdmi_pll_set_rate, 440 .round_rate = mtk_hdmi_pll_round_rate, 441 .recalc_rate = mtk_hdmi_pll_recalc_rate, 442}; 443 444static void vtx_signal_en(struct mtk_hdmi_phy *hdmi_phy, bool on) 445{ 446 void __iomem *regs = hdmi_phy->regs; 447 448 if (on) 449 mtk_phy_set_bits(regs + HDMI_1_CFG_0, RG_HDMITX21_DRV_EN); 450 else 451 mtk_phy_clear_bits(regs + HDMI_1_CFG_0, RG_HDMITX21_DRV_EN); 452} 453 454static void mtk_hdmi_phy_enable_tmds(struct mtk_hdmi_phy *hdmi_phy) 455{ 456 vtx_signal_en(hdmi_phy, true); 457 usleep_range(100, 150); 458} 459 460static void mtk_hdmi_phy_disable_tmds(struct mtk_hdmi_phy *hdmi_phy) 461{ 462 vtx_signal_en(hdmi_phy, false); 463} 464 465static int mtk_hdmi_phy_configure(struct phy *phy, union phy_configure_opts *opts) 466{ 467 struct phy_configure_opts_dp *dp_opts = &opts->dp; 468 struct mtk_hdmi_phy *hdmi_phy = phy_get_drvdata(phy); 469 int ret; 470 471 ret = clk_set_rate(hdmi_phy->pll, dp_opts->link_rate); 472 473 if (ret) 474 return ret; 475 476 mtk_phy_tmds_clk_ratio(hdmi_phy, hdmi_phy->tmds_over_340M); 477 478 return ret; 479} 480 481struct mtk_hdmi_phy_conf mtk_hdmi_phy_8195_conf = { 482 .flags = CLK_SET_RATE_PARENT | CLK_SET_RATE_GATE, 483 .hdmi_phy_clk_ops = &mtk_hdmi_pll_ops, 484 .hdmi_phy_enable_tmds = mtk_hdmi_phy_enable_tmds, 485 .hdmi_phy_disable_tmds = mtk_hdmi_phy_disable_tmds, 486 .hdmi_phy_configure = mtk_hdmi_phy_configure, 487}; 488 489MODULE_AUTHOR("Can Zeng <can.zeng@mediatek.com>"); 490MODULE_DESCRIPTION("MediaTek MT8195 HDMI PHY Driver"); 491MODULE_LICENSE("GPL v2"); 492