Searched refs:postdiv (Results 1 - 25 of 26) sorted by relevance

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/linux-master/arch/mips/ath79/
H A Dclock.c238 u32 pll, out_div, ref_div, nint, nfrac, frac, clk_ctrl, postdiv; local
309 postdiv = (clk_ctrl >> AR934X_PLL_CPU_DDR_CLK_CTRL_CPU_POST_DIV_SHIFT) &
315 cpu_rate = cpu_pll / (postdiv + 1);
317 cpu_rate = ddr_pll / (postdiv + 1);
319 postdiv = (clk_ctrl >> AR934X_PLL_CPU_DDR_CLK_CTRL_DDR_POST_DIV_SHIFT) &
325 ddr_rate = ddr_pll / (postdiv + 1);
327 ddr_rate = cpu_pll / (postdiv + 1);
329 postdiv = (clk_ctrl >> AR934X_PLL_CPU_DDR_CLK_CTRL_AHB_POST_DIV_SHIFT) &
335 ahb_rate = ddr_pll / (postdiv + 1);
337 ahb_rate = cpu_pll / (postdiv
356 u32 pll, out_div, ref_div, nint, frac, clk_ctrl, postdiv; local
439 u32 pll, out_div, ref_div, nint, frac, clk_ctrl, postdiv; local
522 u32 pll, out_div, ref_div, nint, hfrac, lfrac, clk_ctrl, postdiv; local
[all...]
/linux-master/drivers/clk/mediatek/
H A Dclk-pll.c41 u32 pcw, int postdiv)
64 return ((unsigned long)vco + postdiv - 1) / postdiv;
94 int postdiv)
101 /* set postdiv */
104 val |= (ffs(postdiv) - 1) << pll->data->pd_shift;
106 /* postdiv and pcw need to set at the same time if on same register */
133 * @postdiv: The post divider (output)
138 void mtk_pll_calc_values(struct mtk_clk_pll *pll, u32 *pcw, u32 *postdiv, argument
158 *postdiv
40 __mtk_pll_recalc_rate(struct mtk_clk_pll *pll, u32 fin, u32 pcw, int postdiv) argument
93 mtk_pll_set_rate_regs(struct mtk_clk_pll *pll, u32 pcw, int postdiv) argument
180 u32 postdiv; local
191 u32 postdiv; local
208 int postdiv; local
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H A Dclk-fhctl.c171 static void __set_postdiv(struct mtk_clk_pll *pll, unsigned int postdiv) argument
177 regval |= (ffs(postdiv) - 1) << pll->data->pd_shift;
182 unsigned int postdiv)
193 if (postdiv) {
196 if (postdiv > pll_postdiv)
197 __set_postdiv(pll, postdiv);
206 if (postdiv && postdiv < pll_postdiv)
207 __set_postdiv(pll, postdiv);
181 fhctl_hopping(struct mtk_fh *fh, unsigned int new_dds, unsigned int postdiv) argument
H A Dclk-pllfh.h67 unsigned int postdiv);
H A Dclk-pll.h95 void mtk_pll_calc_values(struct mtk_clk_pll *pll, u32 *pcw, u32 *postdiv,
H A Dclk-pllfh.c33 u32 postdiv; local
35 mtk_pll_calc_values(pll, &pcw, &postdiv, rate, parent_rate);
37 return fh->ops->hopping(fh, pcw, postdiv);
/linux-master/drivers/clk/mmp/
H A Dclk-audio.c121 unsigned int postdiv; local
140 for (postdiv = 0; postdiv < ARRAY_SIZE(postdivs); postdiv++) {
146 val |= SSPA_AUD_PLL_CTRL0_DIV_OCLK_MODULO(postdivs[postdiv].modulo);
154 val |= SSPA_AUD_PLL_CTRL1_DIV_OCLK_PATTERN(postdivs[postdiv].pattern);
159 freq /= postdivs[postdiv].divisor;
171 unsigned int postdiv; local
177 for (postdiv = 0; postdiv < ARRAY_SIZ
199 unsigned int postdiv; local
[all...]
H A Dclk-pll.c49 u32 fbdiv, refdiv, postdiv; local
71 postdiv = (val >> pll->postdiv_shift) & 0x7;
76 do_div(rate, postdivs[postdiv]);
/linux-master/drivers/clk/keystone/
H A Dpll.c45 * @postdiv: Fixed post divider
60 u32 postdiv; member in struct:clk_pll_data
81 u32 mult = 0, prediv, postdiv, val; local
100 postdiv = ((val & pll_data->clkod_mask) >>
103 postdiv = readl(pll_data->pllod);
104 postdiv = ((postdiv & pll_data->clkod_mask) >>
107 postdiv = pll_data->postdiv;
111 rate /= postdiv;
[all...]
/linux-master/drivers/gpu/drm/msm/dsi/phy/
H A Ddsi_phy_14nm.c605 struct dsi_pll_14nm_postdiv *postdiv = to_pll_14nm_postdiv(hw); local
606 struct dsi_pll_14nm *pll_14nm = postdiv->pll;
608 u8 shift = postdiv->shift;
609 u8 width = postdiv->width;
618 postdiv->flags, width);
625 struct dsi_pll_14nm_postdiv *postdiv = to_pll_14nm_postdiv(hw); local
626 struct dsi_pll_14nm *pll_14nm = postdiv->pll;
631 postdiv->width,
632 postdiv->flags);
638 struct dsi_pll_14nm_postdiv *postdiv local
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/linux-master/drivers/media/i2c/
H A Dtc358746.c822 u8 postdiv; local
830 postdiv = 1;
832 postdiv = 2;
834 postdiv = 4;
836 postdiv = 8;
846 tmp = fout * postdiv;
853 do_div(tmp, postdiv);
872 tc358746->pll_post_div = postdiv;
880 dev_dbg(dev, "Found PLL settings: freq:%lu prediv:%u multi:%u postdiv:%u\n",
881 best_freq, p_best, m_best, postdiv);
1103 unsigned int postdiv, mclkdiv; local
1191 unsigned int prediv, postdiv; local
[all...]
H A Dov2659.c897 u32 prediv, postdiv, mult; local
903 postdiv = ctrl1[i].div;
910 actual /= postdiv;
/linux-master/drivers/clk/visconti/
H A Dpll.c59 u32 postdiv, val; local
70 postdiv = readl(pll->pll_base + PLL_POSTDIV_REG);
71 rate_table->postdiv1 = postdiv & PLL_POSTDIV_MASK;
72 rate_table->postdiv2 = (postdiv >> 4) & PLL_POSTDIV_MASK;
/linux-master/drivers/clk/
H A Dclk-tps68470.c35 unsigned int postdiv; member in struct:tps68470_clkout_freqs
46 * hclk_# = osc_in * (((plldiv*2)+320) / (xtaldiv+30)) * (1 / 2^postdiv)
59 * osc_in xtaldiv plldiv postdiv hclk_#
171 regmap_write(clkdata->regmap, TPS68470_REG_POSTDIV, clk_freqs[idx].postdiv);
172 regmap_write(clkdata->regmap, TPS68470_REG_POSTDIV2, clk_freqs[idx].postdiv);
H A Dclk-axm5516.c52 unsigned long rate, fbdiv, refdiv, postdiv; local
56 postdiv = ((control >> 0) & 0xf) + 1;
59 rate = (parent_rate / (refdiv * postdiv)) * fbdiv;
/linux-master/drivers/clk/imx/
H A Dclk-composite-8m.c52 int *prediv, int *postdiv)
59 *postdiv = 1;
67 *postdiv = div2;
50 imx8m_clk_composite_compute_dividers(unsigned long rate, unsigned long parent_rate, int *prediv, int *postdiv) argument
/linux-master/drivers/gpu/drm/bridge/
H A Dlontium-lt9611.c173 static void lt9611_pcr_setup(struct lt9611 *lt9611, const struct drm_display_mode *mode, unsigned int postdiv) argument
175 unsigned int pcr_m = mode->clock * 5 * postdiv / 27000;
223 static int lt9611_pll_setup(struct lt9611 *lt9611, const struct drm_display_mode *mode, unsigned int *postdiv) argument
244 *postdiv = 1;
247 *postdiv = 2;
250 *postdiv = 4;
695 unsigned int postdiv; local
712 lt9611_pll_setup(lt9611, mode, &postdiv);
714 lt9611_pcr_setup(lt9611, mode, postdiv);
/linux-master/drivers/video/fbdev/
H A Dgxt4500.c239 int m, n, pdiv1, pdiv2, postdiv; local
249 postdiv = pdiv1 * pdiv2;
250 pll_period = DIV_ROUND_UP(period_ps, postdiv);
258 n = intf * postdiv / period_ps;
261 t = par->refclk_ps * m * postdiv / n;
/linux-master/drivers/gpu/drm/amd/pm/powerplay/smumgr/
H A Dvegam_smumgr.c683 table->SclkFcwRangeTable[i].postdiv =
702 (ref_clk * Range_Table[i].fcw_trans_lower) >> Range_Table[i].postdiv;
704 (ref_clk * Range_Table[i].fcw_trans_upper) >> Range_Table[i].postdiv;
707 table->SclkFcwRangeTable[i].postdiv = Range_Table[i].postdiv;
760 ((clock << table->SclkFcwRangeTable[sclk_setting->PllRange].postdiv) /
762 temp = clock << table->SclkFcwRangeTable[sclk_setting->PllRange].postdiv;
770 ((pcc_target_freq << table->SclkFcwRangeTable[sclk_setting->PllRange].postdiv) /
779 ((ss_target_freq << table->SclkFcwRangeTable[sclk_setting->PllRange].postdiv) /
781 temp = ss_target_freq << table->SclkFcwRangeTable[sclk_setting->PllRange].postdiv;
[all...]
H A Dpolaris10_smumgr.c860 table->SclkFcwRangeTable[i].postdiv = range_table_from_vbios.entry[i].ucPostdiv;
874 smu_data->range_table[i].trans_lower_frequency = (ref_clk * Range_Table[i].fcw_trans_lower) >> Range_Table[i].postdiv;
875 smu_data->range_table[i].trans_upper_frequency = (ref_clk * Range_Table[i].fcw_trans_upper) >> Range_Table[i].postdiv;
878 table->SclkFcwRangeTable[i].postdiv = Range_Table[i].postdiv;
930 sclk_setting->Fcw_int = (uint16_t)((clock << table->SclkFcwRangeTable[sclk_setting->PllRange].postdiv) / ref_clock);
931 temp = clock << table->SclkFcwRangeTable[sclk_setting->PllRange].postdiv;
938 sclk_setting->Pcc_fcw_int = (uint16_t)((pcc_target_freq << table->SclkFcwRangeTable[sclk_setting->PllRange].postdiv) / ref_clock);
945 sclk_setting->Fcw1_int = (uint16_t)((ss_target_freq << table->SclkFcwRangeTable[sclk_setting->PllRange].postdiv) / ref_clock);
946 temp = ss_target_freq << table->SclkFcwRangeTable[sclk_setting->PllRange].postdiv;
[all...]
/linux-master/drivers/phy/rockchip/
H A Dphy-rockchip-inno-hdmi.c270 u8 postdiv; member in struct:post_pll_config
1076 if (cfg->postdiv == 1) {
1080 int div = cfg->postdiv / 2 - 1;
1182 if (cfg->postdiv == 1) {
1188 v = (cfg->postdiv / 2) - 1;
/linux-master/drivers/clk/rockchip/
H A Dclk-pll.c900 u64 rate64 = prate, postdiv; local
911 postdiv = cur.p * 65535;
912 do_div(frac_rate64, postdiv);
/linux-master/drivers/net/can/rcar/
H A Drcar_canfd.c521 u8 postdiv; member in struct:rcar_canfd_hw_info
597 .postdiv = 2,
603 .postdiv = 2,
609 .postdiv = 1,
1953 fcan_freq /= info->postdiv;
/linux-master/drivers/gpu/drm/amd/pm/powerplay/inc/
H A Dsmu74_discrete.h45 uint8_t postdiv; member in struct:sclkFcwRange_t
H A Dsmu75_discrete.h44 uint8_t postdiv; /* divide by 2^n */ member in struct:sclkFcwRange_t

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