10SN/A/* SPDX-License-Identifier: GPL-2.0-only */ 28625SN/A/* 30SN/A * Copyright (c) 2014 MediaTek Inc. 40SN/A * Author: James Liao <jamesjj.liao@mediatek.com> 50SN/A */ 60SN/A 72362SN/A#ifndef __DRV_CLK_MTK_PLL_H 80SN/A#define __DRV_CLK_MTK_PLL_H 92362SN/A 100SN/A#include <linux/clk-provider.h> 110SN/A#include <linux/types.h> 120SN/A 130SN/Astruct clk_ops; 140SN/Astruct clk_hw_onecell_data; 150SN/Astruct device_node; 160SN/A 170SN/Astruct mtk_pll_div_table { 180SN/A u32 div; 190SN/A unsigned long freq; 200SN/A}; 212362SN/A 222362SN/A#define HAVE_RST_BAR BIT(0) 232362SN/A#define PLL_AO BIT(1) 240SN/A#define POSTDIV_MASK GENMASK(2, 0) 250SN/A 260SN/Astruct mtk_pll_data { 270SN/A int id; 280SN/A const char *name; 290SN/A u32 reg; 300SN/A u32 pwr_reg; 310SN/A u32 en_mask; 3210071SN/A u32 pd_reg; 338625SN/A u32 tuner_reg; 348625SN/A u32 tuner_en_reg; 358625SN/A u8 tuner_en_bit; 360SN/A int pd_shift; 370SN/A unsigned int flags; 380SN/A const struct clk_ops *ops; 390SN/A u32 rst_bar_mask; 400SN/A unsigned long fmin; 410SN/A unsigned long fmax; 420SN/A int pcwbits; 430SN/A int pcwibits; 440SN/A u32 pcw_reg; 450SN/A int pcw_shift; 4610071SN/A u32 pcw_chg_reg; 470SN/A const struct mtk_pll_div_table *div_table; 480SN/A const char *parent_name; 490SN/A u32 en_reg; 500SN/A u8 pll_en_bit; /* Assume 0, indicates BIT(0) by default */ 510SN/A u8 pcw_chg_bit; 520SN/A}; 530SN/A 540SN/A/* 550SN/A * MediaTek PLLs are configured through their pcw value. The pcw value describes 560SN/A * a divider in the PLL feedback loop which consists of 7 bits for the integer 570SN/A * part and the remaining bits (if present) for the fractional part. Also they 5810071SN/A * have a 3 bit power-of-two post divider. 590SN/A */ 600SN/A 610SN/Astruct mtk_clk_pll { 620SN/A struct clk_hw hw; 630SN/A void __iomem *base_addr; 640SN/A void __iomem *pd_addr; 65 void __iomem *pwr_addr; 66 void __iomem *tuner_addr; 67 void __iomem *tuner_en_addr; 68 void __iomem *pcw_addr; 69 void __iomem *pcw_chg_addr; 70 void __iomem *en_addr; 71 const struct mtk_pll_data *data; 72}; 73 74int mtk_clk_register_plls(struct device_node *node, 75 const struct mtk_pll_data *plls, int num_plls, 76 struct clk_hw_onecell_data *clk_data); 77void mtk_clk_unregister_plls(const struct mtk_pll_data *plls, int num_plls, 78 struct clk_hw_onecell_data *clk_data); 79 80extern const struct clk_ops mtk_pll_ops; 81 82static inline struct mtk_clk_pll *to_mtk_clk_pll(struct clk_hw *hw) 83{ 84 return container_of(hw, struct mtk_clk_pll, hw); 85} 86 87int mtk_pll_is_prepared(struct clk_hw *hw); 88 89int mtk_pll_prepare(struct clk_hw *hw); 90 91void mtk_pll_unprepare(struct clk_hw *hw); 92 93unsigned long mtk_pll_recalc_rate(struct clk_hw *hw, unsigned long parent_rate); 94 95void mtk_pll_calc_values(struct mtk_clk_pll *pll, u32 *pcw, u32 *postdiv, 96 u32 freq, u32 fin); 97int mtk_pll_set_rate(struct clk_hw *hw, unsigned long rate, 98 unsigned long parent_rate); 99long mtk_pll_round_rate(struct clk_hw *hw, unsigned long rate, 100 unsigned long *prate); 101 102struct clk_hw *mtk_clk_register_pll_ops(struct mtk_clk_pll *pll, 103 const struct mtk_pll_data *data, 104 void __iomem *base, 105 const struct clk_ops *pll_ops); 106struct clk_hw *mtk_clk_register_pll(const struct mtk_pll_data *data, 107 void __iomem *base); 108void mtk_clk_unregister_pll(struct clk_hw *hw); 109 110__iomem void *mtk_clk_pll_get_base(struct clk_hw *hw, 111 const struct mtk_pll_data *data); 112 113#endif /* __DRV_CLK_MTK_PLL_H */ 114