1// SPDX-License-Identifier: GPL-2.0-only 2/* 3 * Frame buffer device for IBM GXT4500P/6500P and GXT4000P/6000P 4 * display adaptors 5 * 6 * Copyright (C) 2006 Paul Mackerras, IBM Corp. <paulus@samba.org> 7 */ 8 9#include <linux/aperture.h> 10#include <linux/kernel.h> 11#include <linux/module.h> 12#include <linux/fb.h> 13#include <linux/console.h> 14#include <linux/pci.h> 15#include <linux/pci_ids.h> 16#include <linux/delay.h> 17#include <linux/string.h> 18 19#define PCI_DEVICE_ID_IBM_GXT4500P 0x21c 20#define PCI_DEVICE_ID_IBM_GXT6500P 0x21b 21#define PCI_DEVICE_ID_IBM_GXT4000P 0x16e 22#define PCI_DEVICE_ID_IBM_GXT6000P 0x170 23 24/* GXT4500P registers */ 25 26/* Registers in PCI config space */ 27#define CFG_ENDIAN0 0x40 28 29/* Misc control/status registers */ 30#define STATUS 0x1000 31#define CTRL_REG0 0x1004 32#define CR0_HALT_DMA 0x4 33#define CR0_RASTER_RESET 0x8 34#define CR0_GEOM_RESET 0x10 35#define CR0_MEM_CTRLER_RESET 0x20 36 37/* Framebuffer control registers */ 38#define FB_AB_CTRL 0x1100 39#define FB_CD_CTRL 0x1104 40#define FB_WID_CTRL 0x1108 41#define FB_Z_CTRL 0x110c 42#define FB_VGA_CTRL 0x1110 43#define REFRESH_AB_CTRL 0x1114 44#define REFRESH_CD_CTRL 0x1118 45#define FB_OVL_CTRL 0x111c 46#define FB_CTRL_TYPE 0x80000000 47#define FB_CTRL_WIDTH_MASK 0x007f0000 48#define FB_CTRL_WIDTH_SHIFT 16 49#define FB_CTRL_START_SEG_MASK 0x00003fff 50 51#define REFRESH_START 0x1098 52#define REFRESH_SIZE 0x109c 53 54/* "Direct" framebuffer access registers */ 55#define DFA_FB_A 0x11e0 56#define DFA_FB_B 0x11e4 57#define DFA_FB_C 0x11e8 58#define DFA_FB_D 0x11ec 59#define DFA_FB_ENABLE 0x80000000 60#define DFA_FB_BASE_MASK 0x03f00000 61#define DFA_FB_STRIDE_1k 0x00000000 62#define DFA_FB_STRIDE_2k 0x00000010 63#define DFA_FB_STRIDE_4k 0x00000020 64#define DFA_PIX_8BIT 0x00000000 65#define DFA_PIX_16BIT_565 0x00000001 66#define DFA_PIX_16BIT_1555 0x00000002 67#define DFA_PIX_24BIT 0x00000004 68#define DFA_PIX_32BIT 0x00000005 69 70/* maps DFA_PIX_* to pixel size in bytes */ 71static const unsigned char pixsize[] = { 72 1, 2, 2, 2, 4, 4 73}; 74 75/* Display timing generator registers */ 76#define DTG_CONTROL 0x1900 77#define DTG_CTL_SCREEN_REFRESH 2 78#define DTG_CTL_ENABLE 1 79#define DTG_HORIZ_EXTENT 0x1904 80#define DTG_HORIZ_DISPLAY 0x1908 81#define DTG_HSYNC_START 0x190c 82#define DTG_HSYNC_END 0x1910 83#define DTG_HSYNC_END_COMP 0x1914 84#define DTG_VERT_EXTENT 0x1918 85#define DTG_VERT_DISPLAY 0x191c 86#define DTG_VSYNC_START 0x1920 87#define DTG_VSYNC_END 0x1924 88#define DTG_VERT_SHORT 0x1928 89 90/* PLL/RAMDAC registers */ 91#define DISP_CTL 0x402c 92#define DISP_CTL_OFF 2 93#define SYNC_CTL 0x4034 94#define SYNC_CTL_SYNC_ON_RGB 1 95#define SYNC_CTL_SYNC_OFF 2 96#define SYNC_CTL_HSYNC_INV 8 97#define SYNC_CTL_VSYNC_INV 0x10 98#define SYNC_CTL_HSYNC_OFF 0x20 99#define SYNC_CTL_VSYNC_OFF 0x40 100 101#define PLL_M 0x4040 102#define PLL_N 0x4044 103#define PLL_POSTDIV 0x4048 104#define PLL_C 0x404c 105 106/* Hardware cursor */ 107#define CURSOR_X 0x4078 108#define CURSOR_Y 0x407c 109#define CURSOR_HOTSPOT 0x4080 110#define CURSOR_MODE 0x4084 111#define CURSOR_MODE_OFF 0 112#define CURSOR_MODE_4BPP 1 113#define CURSOR_PIXMAP 0x5000 114#define CURSOR_CMAP 0x7400 115 116/* Window attribute table */ 117#define WAT_FMT 0x4100 118#define WAT_FMT_24BIT 0 119#define WAT_FMT_16BIT_565 1 120#define WAT_FMT_16BIT_1555 2 121#define WAT_FMT_32BIT 3 /* 0 vs. 3 is a guess */ 122#define WAT_FMT_8BIT_332 9 123#define WAT_FMT_8BIT 0xa 124#define WAT_FMT_NO_CMAP 4 /* ORd in to other values */ 125#define WAT_CMAP_OFFSET 0x4104 /* 4-bit value gets << 6 */ 126#define WAT_CTRL 0x4108 127#define WAT_CTRL_SEL_B 1 /* select B buffer if 1 */ 128#define WAT_CTRL_NO_INC 2 129#define WAT_GAMMA_CTRL 0x410c 130#define WAT_GAMMA_DISABLE 1 /* disables gamma cmap */ 131#define WAT_OVL_CTRL 0x430c /* controls overlay */ 132 133/* Indexed by DFA_PIX_* values */ 134static const unsigned char watfmt[] = { 135 WAT_FMT_8BIT, WAT_FMT_16BIT_565, WAT_FMT_16BIT_1555, 0, 136 WAT_FMT_24BIT, WAT_FMT_32BIT 137}; 138 139/* Colormap array; 1k entries of 4 bytes each */ 140#define CMAP 0x6000 141 142#define readreg(par, reg) readl((par)->regs + (reg)) 143#define writereg(par, reg, val) writel((val), (par)->regs + (reg)) 144 145struct gxt4500_par { 146 void __iomem *regs; 147 int wc_cookie; 148 int pixfmt; /* pixel format, see DFA_PIX_* values */ 149 150 /* PLL parameters */ 151 int refclk_ps; /* ref clock period in picoseconds */ 152 int pll_m; /* ref clock divisor */ 153 int pll_n; /* VCO divisor */ 154 int pll_pd1; /* first post-divisor */ 155 int pll_pd2; /* second post-divisor */ 156 157 u32 pseudo_palette[16]; /* used in color blits */ 158}; 159 160/* mode requested by user */ 161static char *mode_option; 162 163/* default mode: 1280x1024 @ 60 Hz, 8 bpp */ 164static const struct fb_videomode defaultmode = { 165 .refresh = 60, 166 .xres = 1280, 167 .yres = 1024, 168 .pixclock = 9295, 169 .left_margin = 248, 170 .right_margin = 48, 171 .upper_margin = 38, 172 .lower_margin = 1, 173 .hsync_len = 112, 174 .vsync_len = 3, 175 .vmode = FB_VMODE_NONINTERLACED 176}; 177 178/* List of supported cards */ 179enum gxt_cards { 180 GXT4500P, 181 GXT6500P, 182 GXT4000P, 183 GXT6000P 184}; 185 186/* Card-specific information */ 187static const struct cardinfo { 188 int refclk_ps; /* period of PLL reference clock in ps */ 189 const char *cardname; 190} cardinfo[] = { 191 [GXT4500P] = { .refclk_ps = 9259, .cardname = "IBM GXT4500P" }, 192 [GXT6500P] = { .refclk_ps = 9259, .cardname = "IBM GXT6500P" }, 193 [GXT4000P] = { .refclk_ps = 40000, .cardname = "IBM GXT4000P" }, 194 [GXT6000P] = { .refclk_ps = 40000, .cardname = "IBM GXT6000P" }, 195}; 196 197/* 198 * The refclk and VCO dividers appear to use a linear feedback shift 199 * register, which gets reloaded when it reaches a terminal value, at 200 * which point the divider output is toggled. Thus one can obtain 201 * whatever divisor is required by putting the appropriate value into 202 * the reload register. For a divisor of N, one puts the value from 203 * the LFSR sequence that comes N-1 places before the terminal value 204 * into the reload register. 205 */ 206 207static const unsigned char mdivtab[] = { 208/* 1 */ 0x3f, 0x00, 0x20, 0x10, 0x28, 0x14, 0x2a, 0x15, 0x0a, 209/* 10 */ 0x25, 0x32, 0x19, 0x0c, 0x26, 0x13, 0x09, 0x04, 0x22, 0x11, 210/* 20 */ 0x08, 0x24, 0x12, 0x29, 0x34, 0x1a, 0x2d, 0x36, 0x1b, 0x0d, 211/* 30 */ 0x06, 0x23, 0x31, 0x38, 0x1c, 0x2e, 0x17, 0x0b, 0x05, 0x02, 212/* 40 */ 0x21, 0x30, 0x18, 0x2c, 0x16, 0x2b, 0x35, 0x3a, 0x1d, 0x0e, 213/* 50 */ 0x27, 0x33, 0x39, 0x3c, 0x1e, 0x2f, 0x37, 0x3b, 0x3d, 0x3e, 214/* 60 */ 0x1f, 0x0f, 0x07, 0x03, 0x01, 215}; 216 217static const unsigned char ndivtab[] = { 218/* 2 */ 0x00, 0x80, 0xc0, 0xe0, 0xf0, 0x78, 0xbc, 0x5e, 219/* 10 */ 0x2f, 0x17, 0x0b, 0x85, 0xc2, 0xe1, 0x70, 0x38, 0x9c, 0x4e, 220/* 20 */ 0xa7, 0xd3, 0xe9, 0xf4, 0xfa, 0xfd, 0xfe, 0x7f, 0xbf, 0xdf, 221/* 30 */ 0xef, 0x77, 0x3b, 0x1d, 0x8e, 0xc7, 0xe3, 0x71, 0xb8, 0xdc, 222/* 40 */ 0x6e, 0xb7, 0x5b, 0x2d, 0x16, 0x8b, 0xc5, 0xe2, 0xf1, 0xf8, 223/* 50 */ 0xfc, 0x7e, 0x3f, 0x9f, 0xcf, 0x67, 0xb3, 0xd9, 0x6c, 0xb6, 224/* 60 */ 0xdb, 0x6d, 0x36, 0x9b, 0x4d, 0x26, 0x13, 0x89, 0xc4, 0x62, 225/* 70 */ 0xb1, 0xd8, 0xec, 0xf6, 0xfb, 0x7d, 0xbe, 0x5f, 0xaf, 0x57, 226/* 80 */ 0x2b, 0x95, 0x4a, 0x25, 0x92, 0x49, 0xa4, 0x52, 0x29, 0x94, 227/* 90 */ 0xca, 0x65, 0xb2, 0x59, 0x2c, 0x96, 0xcb, 0xe5, 0xf2, 0x79, 228/* 100 */ 0x3c, 0x1e, 0x0f, 0x07, 0x83, 0x41, 0x20, 0x90, 0x48, 0x24, 229/* 110 */ 0x12, 0x09, 0x84, 0x42, 0xa1, 0x50, 0x28, 0x14, 0x8a, 0x45, 230/* 120 */ 0xa2, 0xd1, 0xe8, 0x74, 0xba, 0xdd, 0xee, 0xf7, 0x7b, 0x3d, 231/* 130 */ 0x9e, 0x4f, 0x27, 0x93, 0xc9, 0xe4, 0x72, 0x39, 0x1c, 0x0e, 232/* 140 */ 0x87, 0xc3, 0x61, 0x30, 0x18, 0x8c, 0xc6, 0x63, 0x31, 0x98, 233/* 150 */ 0xcc, 0xe6, 0x73, 0xb9, 0x5c, 0x2e, 0x97, 0x4b, 0xa5, 0xd2, 234/* 160 */ 0x69, 235}; 236 237static int calc_pll(int period_ps, struct gxt4500_par *par) 238{ 239 int m, n, pdiv1, pdiv2, postdiv; 240 int pll_period, best_error, t, intf; 241 242 /* only deal with range 5MHz - 300MHz */ 243 if (period_ps < 3333 || period_ps > 200000) 244 return -1; 245 246 best_error = 1000000; 247 for (pdiv1 = 1; pdiv1 <= 8; ++pdiv1) { 248 for (pdiv2 = 1; pdiv2 <= pdiv1; ++pdiv2) { 249 postdiv = pdiv1 * pdiv2; 250 pll_period = DIV_ROUND_UP(period_ps, postdiv); 251 /* keep pll in range 350..600 MHz */ 252 if (pll_period < 1666 || pll_period > 2857) 253 continue; 254 for (m = 1; m <= 64; ++m) { 255 intf = m * par->refclk_ps; 256 if (intf > 500000) 257 break; 258 n = intf * postdiv / period_ps; 259 if (n < 3 || n > 160) 260 continue; 261 t = par->refclk_ps * m * postdiv / n; 262 t -= period_ps; 263 if (t >= 0 && t < best_error) { 264 par->pll_m = m; 265 par->pll_n = n; 266 par->pll_pd1 = pdiv1; 267 par->pll_pd2 = pdiv2; 268 best_error = t; 269 } 270 } 271 } 272 } 273 if (best_error == 1000000) 274 return -1; 275 return 0; 276} 277 278static int calc_pixclock(struct gxt4500_par *par) 279{ 280 return par->refclk_ps * par->pll_m * par->pll_pd1 * par->pll_pd2 281 / par->pll_n; 282} 283 284static int gxt4500_var_to_par(struct fb_var_screeninfo *var, 285 struct gxt4500_par *par) 286{ 287 if (var->xres + var->xoffset > var->xres_virtual || 288 var->yres + var->yoffset > var->yres_virtual || 289 var->xres_virtual > 4096) 290 return -EINVAL; 291 if ((var->vmode & FB_VMODE_MASK) != FB_VMODE_NONINTERLACED) 292 return -EINVAL; 293 294 if (calc_pll(var->pixclock, par) < 0) 295 return -EINVAL; 296 297 switch (var->bits_per_pixel) { 298 case 32: 299 if (var->transp.length) 300 par->pixfmt = DFA_PIX_32BIT; 301 else 302 par->pixfmt = DFA_PIX_24BIT; 303 break; 304 case 24: 305 par->pixfmt = DFA_PIX_24BIT; 306 break; 307 case 16: 308 if (var->green.length == 5) 309 par->pixfmt = DFA_PIX_16BIT_1555; 310 else 311 par->pixfmt = DFA_PIX_16BIT_565; 312 break; 313 case 8: 314 par->pixfmt = DFA_PIX_8BIT; 315 break; 316 default: 317 return -EINVAL; 318 } 319 320 return 0; 321} 322 323static const struct fb_bitfield eightbits = {0, 8}; 324static const struct fb_bitfield nobits = {0, 0}; 325 326static void gxt4500_unpack_pixfmt(struct fb_var_screeninfo *var, 327 int pixfmt) 328{ 329 var->bits_per_pixel = pixsize[pixfmt] * 8; 330 var->red = eightbits; 331 var->green = eightbits; 332 var->blue = eightbits; 333 var->transp = nobits; 334 335 switch (pixfmt) { 336 case DFA_PIX_16BIT_565: 337 var->red.length = 5; 338 var->green.length = 6; 339 var->blue.length = 5; 340 break; 341 case DFA_PIX_16BIT_1555: 342 var->red.length = 5; 343 var->green.length = 5; 344 var->blue.length = 5; 345 var->transp.length = 1; 346 break; 347 case DFA_PIX_32BIT: 348 var->transp.length = 8; 349 break; 350 } 351 if (pixfmt != DFA_PIX_8BIT) { 352 var->blue.offset = 0; 353 var->green.offset = var->blue.length; 354 var->red.offset = var->green.offset + var->green.length; 355 if (var->transp.length) 356 var->transp.offset = 357 var->red.offset + var->red.length; 358 } 359} 360 361static int gxt4500_check_var(struct fb_var_screeninfo *var, 362 struct fb_info *info) 363{ 364 struct gxt4500_par par; 365 int err; 366 367 par = *(struct gxt4500_par *)info->par; 368 err = gxt4500_var_to_par(var, &par); 369 if (!err) { 370 var->pixclock = calc_pixclock(&par); 371 gxt4500_unpack_pixfmt(var, par.pixfmt); 372 } 373 return err; 374} 375 376static int gxt4500_set_par(struct fb_info *info) 377{ 378 struct gxt4500_par *par = info->par; 379 struct fb_var_screeninfo *var = &info->var; 380 int err; 381 u32 ctrlreg, tmp; 382 unsigned int dfa_ctl, pixfmt, stride; 383 unsigned int wid_tiles, i; 384 unsigned int prefetch_pix, htot; 385 struct gxt4500_par save_par; 386 387 save_par = *par; 388 err = gxt4500_var_to_par(var, par); 389 if (err) { 390 *par = save_par; 391 return err; 392 } 393 394 /* turn off DTG for now */ 395 ctrlreg = readreg(par, DTG_CONTROL); 396 ctrlreg &= ~(DTG_CTL_ENABLE | DTG_CTL_SCREEN_REFRESH); 397 writereg(par, DTG_CONTROL, ctrlreg); 398 399 /* set PLL registers */ 400 tmp = readreg(par, PLL_C) & ~0x7f; 401 if (par->pll_n < 38) 402 tmp |= 0x29; 403 if (par->pll_n < 69) 404 tmp |= 0x35; 405 else if (par->pll_n < 100) 406 tmp |= 0x76; 407 else 408 tmp |= 0x7e; 409 writereg(par, PLL_C, tmp); 410 writereg(par, PLL_M, mdivtab[par->pll_m - 1]); 411 writereg(par, PLL_N, ndivtab[par->pll_n - 2]); 412 tmp = ((8 - par->pll_pd2) << 3) | (8 - par->pll_pd1); 413 if (par->pll_pd1 == 8 || par->pll_pd2 == 8) { 414 /* work around erratum */ 415 writereg(par, PLL_POSTDIV, tmp | 0x9); 416 udelay(1); 417 } 418 writereg(par, PLL_POSTDIV, tmp); 419 msleep(20); 420 421 /* turn off hardware cursor */ 422 writereg(par, CURSOR_MODE, CURSOR_MODE_OFF); 423 424 /* reset raster engine */ 425 writereg(par, CTRL_REG0, CR0_RASTER_RESET | (CR0_RASTER_RESET << 16)); 426 udelay(10); 427 writereg(par, CTRL_REG0, CR0_RASTER_RESET << 16); 428 429 /* set display timing generator registers */ 430 htot = var->xres + var->left_margin + var->right_margin + 431 var->hsync_len; 432 writereg(par, DTG_HORIZ_EXTENT, htot - 1); 433 writereg(par, DTG_HORIZ_DISPLAY, var->xres - 1); 434 writereg(par, DTG_HSYNC_START, var->xres + var->right_margin - 1); 435 writereg(par, DTG_HSYNC_END, 436 var->xres + var->right_margin + var->hsync_len - 1); 437 writereg(par, DTG_HSYNC_END_COMP, 438 var->xres + var->right_margin + var->hsync_len - 1); 439 writereg(par, DTG_VERT_EXTENT, 440 var->yres + var->upper_margin + var->lower_margin + 441 var->vsync_len - 1); 442 writereg(par, DTG_VERT_DISPLAY, var->yres - 1); 443 writereg(par, DTG_VSYNC_START, var->yres + var->lower_margin - 1); 444 writereg(par, DTG_VSYNC_END, 445 var->yres + var->lower_margin + var->vsync_len - 1); 446 prefetch_pix = 3300000 / var->pixclock; 447 if (prefetch_pix >= htot) 448 prefetch_pix = htot - 1; 449 writereg(par, DTG_VERT_SHORT, htot - prefetch_pix - 1); 450 ctrlreg |= DTG_CTL_ENABLE | DTG_CTL_SCREEN_REFRESH; 451 writereg(par, DTG_CONTROL, ctrlreg); 452 453 /* calculate stride in DFA aperture */ 454 if (var->xres_virtual > 2048) { 455 stride = 4096; 456 dfa_ctl = DFA_FB_STRIDE_4k; 457 } else if (var->xres_virtual > 1024) { 458 stride = 2048; 459 dfa_ctl = DFA_FB_STRIDE_2k; 460 } else { 461 stride = 1024; 462 dfa_ctl = DFA_FB_STRIDE_1k; 463 } 464 465 /* Set up framebuffer definition */ 466 wid_tiles = (var->xres_virtual + 63) >> 6; 467 468 /* XXX add proper FB allocation here someday */ 469 writereg(par, FB_AB_CTRL, FB_CTRL_TYPE | (wid_tiles << 16) | 0); 470 writereg(par, REFRESH_AB_CTRL, FB_CTRL_TYPE | (wid_tiles << 16) | 0); 471 writereg(par, FB_CD_CTRL, FB_CTRL_TYPE | (wid_tiles << 16) | 0); 472 writereg(par, REFRESH_CD_CTRL, FB_CTRL_TYPE | (wid_tiles << 16) | 0); 473 writereg(par, REFRESH_START, (var->xoffset << 16) | var->yoffset); 474 writereg(par, REFRESH_SIZE, (var->xres << 16) | var->yres); 475 476 /* Set up framebuffer access by CPU */ 477 478 pixfmt = par->pixfmt; 479 dfa_ctl |= DFA_FB_ENABLE | pixfmt; 480 writereg(par, DFA_FB_A, dfa_ctl); 481 482 /* 483 * Set up window attribute table. 484 * We set all WAT entries the same so it doesn't matter what the 485 * window ID (WID) plane contains. 486 */ 487 for (i = 0; i < 32; ++i) { 488 writereg(par, WAT_FMT + (i << 4), watfmt[pixfmt]); 489 writereg(par, WAT_CMAP_OFFSET + (i << 4), 0); 490 writereg(par, WAT_CTRL + (i << 4), 0); 491 writereg(par, WAT_GAMMA_CTRL + (i << 4), WAT_GAMMA_DISABLE); 492 } 493 494 /* Set sync polarity etc. */ 495 ctrlreg = readreg(par, SYNC_CTL) & 496 ~(SYNC_CTL_SYNC_ON_RGB | SYNC_CTL_HSYNC_INV | 497 SYNC_CTL_VSYNC_INV); 498 if (var->sync & FB_SYNC_ON_GREEN) 499 ctrlreg |= SYNC_CTL_SYNC_ON_RGB; 500 if (!(var->sync & FB_SYNC_HOR_HIGH_ACT)) 501 ctrlreg |= SYNC_CTL_HSYNC_INV; 502 if (!(var->sync & FB_SYNC_VERT_HIGH_ACT)) 503 ctrlreg |= SYNC_CTL_VSYNC_INV; 504 writereg(par, SYNC_CTL, ctrlreg); 505 506 info->fix.line_length = stride * pixsize[pixfmt]; 507 info->fix.visual = (pixfmt == DFA_PIX_8BIT)? FB_VISUAL_PSEUDOCOLOR: 508 FB_VISUAL_DIRECTCOLOR; 509 510 return 0; 511} 512 513static int gxt4500_setcolreg(unsigned int reg, unsigned int red, 514 unsigned int green, unsigned int blue, 515 unsigned int transp, struct fb_info *info) 516{ 517 u32 cmap_entry; 518 struct gxt4500_par *par = info->par; 519 520 if (reg > 1023) 521 return 1; 522 cmap_entry = ((transp & 0xff00) << 16) | ((red & 0xff00) << 8) | 523 (green & 0xff00) | (blue >> 8); 524 writereg(par, CMAP + reg * 4, cmap_entry); 525 526 if (reg < 16 && par->pixfmt != DFA_PIX_8BIT) { 527 u32 *pal = info->pseudo_palette; 528 u32 val = reg; 529 switch (par->pixfmt) { 530 case DFA_PIX_16BIT_565: 531 val |= (reg << 11) | (reg << 5); 532 break; 533 case DFA_PIX_16BIT_1555: 534 val |= (reg << 10) | (reg << 5); 535 break; 536 case DFA_PIX_32BIT: 537 val |= (reg << 24); 538 fallthrough; 539 case DFA_PIX_24BIT: 540 val |= (reg << 16) | (reg << 8); 541 break; 542 } 543 pal[reg] = val; 544 } 545 546 return 0; 547} 548 549static int gxt4500_pan_display(struct fb_var_screeninfo *var, 550 struct fb_info *info) 551{ 552 struct gxt4500_par *par = info->par; 553 554 if (var->xoffset & 7) 555 return -EINVAL; 556 if (var->xoffset + info->var.xres > info->var.xres_virtual || 557 var->yoffset + info->var.yres > info->var.yres_virtual) 558 return -EINVAL; 559 560 writereg(par, REFRESH_START, (var->xoffset << 16) | var->yoffset); 561 return 0; 562} 563 564static int gxt4500_blank(int blank, struct fb_info *info) 565{ 566 struct gxt4500_par *par = info->par; 567 int ctrl, dctl; 568 569 ctrl = readreg(par, SYNC_CTL); 570 ctrl &= ~(SYNC_CTL_SYNC_OFF | SYNC_CTL_HSYNC_OFF | SYNC_CTL_VSYNC_OFF); 571 dctl = readreg(par, DISP_CTL); 572 dctl |= DISP_CTL_OFF; 573 switch (blank) { 574 case FB_BLANK_UNBLANK: 575 dctl &= ~DISP_CTL_OFF; 576 break; 577 case FB_BLANK_POWERDOWN: 578 ctrl |= SYNC_CTL_SYNC_OFF; 579 break; 580 case FB_BLANK_HSYNC_SUSPEND: 581 ctrl |= SYNC_CTL_HSYNC_OFF; 582 break; 583 case FB_BLANK_VSYNC_SUSPEND: 584 ctrl |= SYNC_CTL_VSYNC_OFF; 585 break; 586 default: ; 587 } 588 writereg(par, SYNC_CTL, ctrl); 589 writereg(par, DISP_CTL, dctl); 590 591 return 0; 592} 593 594static const struct fb_fix_screeninfo gxt4500_fix = { 595 .id = "IBM GXT4500P", 596 .type = FB_TYPE_PACKED_PIXELS, 597 .visual = FB_VISUAL_PSEUDOCOLOR, 598 .xpanstep = 8, 599 .ypanstep = 1, 600 .mmio_len = 0x20000, 601}; 602 603static const struct fb_ops gxt4500_ops = { 604 .owner = THIS_MODULE, 605 FB_DEFAULT_IOMEM_OPS, 606 .fb_check_var = gxt4500_check_var, 607 .fb_set_par = gxt4500_set_par, 608 .fb_setcolreg = gxt4500_setcolreg, 609 .fb_pan_display = gxt4500_pan_display, 610 .fb_blank = gxt4500_blank, 611}; 612 613/* PCI functions */ 614static int gxt4500_probe(struct pci_dev *pdev, const struct pci_device_id *ent) 615{ 616 int err; 617 unsigned long reg_phys, fb_phys; 618 struct gxt4500_par *par; 619 struct fb_info *info; 620 struct fb_var_screeninfo var; 621 enum gxt_cards cardtype; 622 623 err = aperture_remove_conflicting_pci_devices(pdev, "gxt4500fb"); 624 if (err) 625 return err; 626 627 err = pci_enable_device(pdev); 628 if (err) { 629 dev_err(&pdev->dev, "gxt4500: cannot enable PCI device: %d\n", 630 err); 631 return err; 632 } 633 634 reg_phys = pci_resource_start(pdev, 0); 635 if (!request_mem_region(reg_phys, pci_resource_len(pdev, 0), 636 "gxt4500 regs")) { 637 dev_err(&pdev->dev, "gxt4500: cannot get registers\n"); 638 goto err_nodev; 639 } 640 641 fb_phys = pci_resource_start(pdev, 1); 642 if (!request_mem_region(fb_phys, pci_resource_len(pdev, 1), 643 "gxt4500 FB")) { 644 dev_err(&pdev->dev, "gxt4500: cannot get framebuffer\n"); 645 goto err_free_regs; 646 } 647 648 info = framebuffer_alloc(sizeof(struct gxt4500_par), &pdev->dev); 649 if (!info) 650 goto err_free_fb; 651 652 par = info->par; 653 cardtype = ent->driver_data; 654 par->refclk_ps = cardinfo[cardtype].refclk_ps; 655 info->fix = gxt4500_fix; 656 strscpy(info->fix.id, cardinfo[cardtype].cardname, 657 sizeof(info->fix.id)); 658 info->pseudo_palette = par->pseudo_palette; 659 660 info->fix.mmio_start = reg_phys; 661 par->regs = pci_ioremap_bar(pdev, 0); 662 if (!par->regs) { 663 dev_err(&pdev->dev, "gxt4500: cannot map registers\n"); 664 goto err_free_all; 665 } 666 667 info->fix.smem_start = fb_phys; 668 info->fix.smem_len = pci_resource_len(pdev, 1); 669 info->screen_base = pci_ioremap_wc_bar(pdev, 1); 670 if (!info->screen_base) { 671 dev_err(&pdev->dev, "gxt4500: cannot map framebuffer\n"); 672 goto err_unmap_regs; 673 } 674 675 pci_set_drvdata(pdev, info); 676 677 par->wc_cookie = arch_phys_wc_add(info->fix.smem_start, 678 info->fix.smem_len); 679 680#ifdef __BIG_ENDIAN 681 /* Set byte-swapping for DFA aperture for all pixel sizes */ 682 pci_write_config_dword(pdev, CFG_ENDIAN0, 0x333300); 683#else /* __LITTLE_ENDIAN */ 684 /* not sure what this means but fgl23 driver does that */ 685 pci_write_config_dword(pdev, CFG_ENDIAN0, 0x2300); 686/* pci_write_config_dword(pdev, CFG_ENDIAN0 + 4, 0x400000);*/ 687 pci_write_config_dword(pdev, CFG_ENDIAN0 + 8, 0x98530000); 688#endif 689 690 info->fbops = &gxt4500_ops; 691 info->flags = FBINFO_HWACCEL_XPAN | FBINFO_HWACCEL_YPAN; 692 693 err = fb_alloc_cmap(&info->cmap, 256, 0); 694 if (err) { 695 dev_err(&pdev->dev, "gxt4500: cannot allocate cmap\n"); 696 goto err_unmap_all; 697 } 698 699 gxt4500_blank(FB_BLANK_UNBLANK, info); 700 701 if (!fb_find_mode(&var, info, mode_option, NULL, 0, &defaultmode, 8)) { 702 dev_err(&pdev->dev, "gxt4500: cannot find valid video mode\n"); 703 goto err_free_cmap; 704 } 705 info->var = var; 706 if (gxt4500_set_par(info)) { 707 printk(KERN_ERR "gxt4500: cannot set video mode\n"); 708 goto err_free_cmap; 709 } 710 711 if (register_framebuffer(info) < 0) { 712 dev_err(&pdev->dev, "gxt4500: cannot register framebuffer\n"); 713 goto err_free_cmap; 714 } 715 fb_info(info, "%s frame buffer device\n", info->fix.id); 716 717 return 0; 718 719 err_free_cmap: 720 fb_dealloc_cmap(&info->cmap); 721 err_unmap_all: 722 iounmap(info->screen_base); 723 err_unmap_regs: 724 iounmap(par->regs); 725 err_free_all: 726 framebuffer_release(info); 727 err_free_fb: 728 release_mem_region(fb_phys, pci_resource_len(pdev, 1)); 729 err_free_regs: 730 release_mem_region(reg_phys, pci_resource_len(pdev, 0)); 731 err_nodev: 732 return -ENODEV; 733} 734 735static void gxt4500_remove(struct pci_dev *pdev) 736{ 737 struct fb_info *info = pci_get_drvdata(pdev); 738 struct gxt4500_par *par; 739 740 if (!info) 741 return; 742 par = info->par; 743 unregister_framebuffer(info); 744 arch_phys_wc_del(par->wc_cookie); 745 fb_dealloc_cmap(&info->cmap); 746 iounmap(par->regs); 747 iounmap(info->screen_base); 748 release_mem_region(pci_resource_start(pdev, 0), 749 pci_resource_len(pdev, 0)); 750 release_mem_region(pci_resource_start(pdev, 1), 751 pci_resource_len(pdev, 1)); 752 framebuffer_release(info); 753} 754 755/* supported chipsets */ 756static const struct pci_device_id gxt4500_pci_tbl[] = { 757 { PCI_DEVICE(PCI_VENDOR_ID_IBM, PCI_DEVICE_ID_IBM_GXT4500P), 758 .driver_data = GXT4500P }, 759 { PCI_DEVICE(PCI_VENDOR_ID_IBM, PCI_DEVICE_ID_IBM_GXT6500P), 760 .driver_data = GXT6500P }, 761 { PCI_DEVICE(PCI_VENDOR_ID_IBM, PCI_DEVICE_ID_IBM_GXT4000P), 762 .driver_data = GXT4000P }, 763 { PCI_DEVICE(PCI_VENDOR_ID_IBM, PCI_DEVICE_ID_IBM_GXT6000P), 764 .driver_data = GXT6000P }, 765 { 0 } 766}; 767 768MODULE_DEVICE_TABLE(pci, gxt4500_pci_tbl); 769 770static struct pci_driver gxt4500_driver = { 771 .name = "gxt4500", 772 .id_table = gxt4500_pci_tbl, 773 .probe = gxt4500_probe, 774 .remove = gxt4500_remove, 775}; 776 777static int gxt4500_init(void) 778{ 779 if (fb_modesetting_disabled("gxt4500")) 780 return -ENODEV; 781 782#ifndef MODULE 783 if (fb_get_options("gxt4500", &mode_option)) 784 return -ENODEV; 785#endif 786 787 return pci_register_driver(&gxt4500_driver); 788} 789module_init(gxt4500_init); 790 791static void __exit gxt4500_exit(void) 792{ 793 pci_unregister_driver(&gxt4500_driver); 794} 795module_exit(gxt4500_exit); 796 797MODULE_AUTHOR("Paul Mackerras <paulus@samba.org>"); 798MODULE_DESCRIPTION("FBDev driver for IBM GXT4500P/6500P and GXT4000P/6000P"); 799MODULE_LICENSE("GPL"); 800module_param(mode_option, charp, 0); 801MODULE_PARM_DESC(mode_option, "Specify resolution as \"<xres>x<yres>[-<bpp>][@<refresh>]\""); 802