Searched refs:pipe_config (Results 1 - 25 of 55) sorted by relevance

123

/linux-master/drivers/gpu/drm/i915/display/
H A Dintel_crtc_state_dump.c31 intel_dump_m_n_config(const struct intel_crtc_state *pipe_config, argument
35 struct drm_i915_private *i915 = to_i915(pipe_config->uapi.crtc->dev);
200 void intel_crtc_state_dump(const struct intel_crtc_state *pipe_config, argument
204 struct intel_crtc *crtc = to_intel_crtc(pipe_config->uapi.crtc);
213 str_yes_no(pipe_config->hw.enable), context);
215 if (!pipe_config->hw.enable)
218 snprintf_output_types(buf, sizeof(buf), pipe_config->output_types);
221 str_yes_no(pipe_config->hw.active),
222 buf, pipe_config->output_types,
223 intel_output_format_name(pipe_config
[all...]
H A Dg4x_hdmi.c153 struct intel_crtc_state *pipe_config)
161 pipe_config->output_types |= BIT(INTEL_OUTPUT_HDMI);
176 pipe_config->has_hdmi_sink = true;
178 pipe_config->infoframes.enable |=
179 intel_hdmi_infoframes_enabled(encoder, pipe_config);
181 if (pipe_config->infoframes.enable)
182 pipe_config->has_infoframe = true;
185 pipe_config->has_audio = true;
189 pipe_config->limited_color_range = true;
191 pipe_config
152 intel_hdmi_get_config(struct intel_encoder *encoder, struct intel_crtc_state *pipe_config) argument
220 g4x_hdmi_enable_port(struct intel_encoder *encoder, const struct intel_crtc_state *pipe_config) argument
270 g4x_enable_hdmi(struct intel_atomic_state *state, struct intel_encoder *encoder, const struct intel_crtc_state *pipe_config, const struct drm_connector_state *conn_state) argument
278 ibx_enable_hdmi(struct intel_atomic_state *state, struct intel_encoder *encoder, const struct intel_crtc_state *pipe_config, const struct drm_connector_state *conn_state) argument
325 cpt_enable_hdmi(struct intel_atomic_state *state, struct intel_encoder *encoder, const struct intel_crtc_state *pipe_config, const struct drm_connector_state *conn_state) argument
374 vlv_enable_hdmi(struct intel_atomic_state *state, struct intel_encoder *encoder, const struct intel_crtc_state *pipe_config, const struct drm_connector_state *conn_state) argument
463 intel_hdmi_pre_enable(struct intel_atomic_state *state, struct intel_encoder *encoder, const struct intel_crtc_state *pipe_config, const struct drm_connector_state *conn_state) argument
478 vlv_hdmi_pre_enable(struct intel_atomic_state *state, struct intel_encoder *encoder, const struct intel_crtc_state *pipe_config, const struct drm_connector_state *conn_state) argument
502 vlv_hdmi_pre_pll_enable(struct intel_atomic_state *state, struct intel_encoder *encoder, const struct intel_crtc_state *pipe_config, const struct drm_connector_state *conn_state) argument
512 chv_hdmi_pre_pll_enable(struct intel_atomic_state *state, struct intel_encoder *encoder, const struct intel_crtc_state *pipe_config, const struct drm_connector_state *conn_state) argument
555 chv_hdmi_pre_enable(struct intel_atomic_state *state, struct intel_encoder *encoder, const struct intel_crtc_state *pipe_config, const struct drm_connector_state *conn_state) argument
[all...]
H A Dintel_lspcon.h35 const struct intel_crtc_state *pipe_config);
37 const struct intel_crtc_state *pipe_config);
H A Dg4x_dp.h24 struct intel_crtc_state *pipe_config);
40 struct intel_crtc_state *pipe_config)
39 g4x_dp_set_clock(struct intel_encoder *encoder, struct intel_crtc_state *pipe_config) argument
H A Dg4x_dp.c57 struct intel_crtc_state *pipe_config)
79 if (pipe_config->port_clock == divisor[i].dot) {
80 pipe_config->dpll = divisor[i];
81 pipe_config->clock_set = true;
89 const struct intel_crtc_state *pipe_config)
94 struct intel_crtc *crtc = to_intel_crtc(pipe_config->uapi.crtc);
95 const struct drm_display_mode *adjusted_mode = &pipe_config->hw.adjusted_mode;
98 pipe_config->port_clock,
99 pipe_config->lane_count);
124 intel_dp->DP |= DP_PORT_WIDTH(pipe_config
56 g4x_dp_set_clock(struct intel_encoder *encoder, struct intel_crtc_state *pipe_config) argument
88 intel_dp_prepare(struct intel_encoder *encoder, const struct intel_crtc_state *pipe_config) argument
190 ilk_edp_pll_on(struct intel_dp *intel_dp, const struct intel_crtc_state *pipe_config) argument
332 intel_dp_get_config(struct intel_encoder *encoder, struct intel_crtc_state *pipe_config) argument
671 intel_enable_dp(struct intel_atomic_state *state, struct intel_encoder *encoder, const struct intel_crtc_state *pipe_config, const struct drm_connector_state *conn_state) argument
713 g4x_enable_dp(struct intel_atomic_state *state, struct intel_encoder *encoder, const struct intel_crtc_state *pipe_config, const struct drm_connector_state *conn_state) argument
722 vlv_enable_dp(struct intel_atomic_state *state, struct intel_encoder *encoder, const struct intel_crtc_state *pipe_config, const struct drm_connector_state *conn_state) argument
730 g4x_pre_enable_dp(struct intel_atomic_state *state, struct intel_encoder *encoder, const struct intel_crtc_state *pipe_config, const struct drm_connector_state *conn_state) argument
745 vlv_pre_enable_dp(struct intel_atomic_state *state, struct intel_encoder *encoder, const struct intel_crtc_state *pipe_config, const struct drm_connector_state *conn_state) argument
755 vlv_dp_pre_pll_enable(struct intel_atomic_state *state, struct intel_encoder *encoder, const struct intel_crtc_state *pipe_config, const struct drm_connector_state *conn_state) argument
765 chv_pre_enable_dp(struct intel_atomic_state *state, struct intel_encoder *encoder, const struct intel_crtc_state *pipe_config, const struct drm_connector_state *conn_state) argument
778 chv_dp_pre_pll_enable(struct intel_atomic_state *state, struct intel_encoder *encoder, const struct intel_crtc_state *pipe_config, const struct drm_connector_state *conn_state) argument
[all...]
H A Dintel_dpll.h43 struct intel_crtc_state *pipe_config);
45 struct intel_crtc_state *pipe_config);
47 struct intel_crtc_state *pipe_config);
H A Dintel_vdsc.h20 int intel_dsc_compute_params(struct intel_crtc_state *pipe_config);
H A Dintel_dvo.c160 struct intel_crtc_state *pipe_config)
166 pipe_config->output_types |= BIT(INTEL_OUTPUT_DVO);
178 pipe_config->hw.adjusted_mode.flags |= flags;
180 pipe_config->hw.adjusted_mode.crtc_clock = pipe_config->port_clock;
200 const struct intel_crtc_state *pipe_config,
208 &pipe_config->hw.mode,
209 &pipe_config->hw.adjusted_mode);
256 struct intel_crtc_state *pipe_config,
261 struct drm_display_mode *adjusted_mode = &pipe_config
159 intel_dvo_get_config(struct intel_encoder *encoder, struct intel_crtc_state *pipe_config) argument
198 intel_enable_dvo(struct intel_atomic_state *state, struct intel_encoder *encoder, const struct intel_crtc_state *pipe_config, const struct drm_connector_state *conn_state) argument
255 intel_dvo_compute_config(struct intel_encoder *encoder, struct intel_crtc_state *pipe_config, struct drm_connector_state *conn_state) argument
288 intel_dvo_pre_enable(struct intel_atomic_state *state, struct intel_encoder *encoder, const struct intel_crtc_state *pipe_config, const struct drm_connector_state *conn_state) argument
[all...]
H A Dintel_fdi.h21 const struct intel_crtc_state *pipe_config);
24 struct intel_crtc_state *pipe_config);
H A Dintel_dp.h41 struct intel_crtc_state *pipe_config,
78 struct intel_crtc_state *pipe_config,
81 struct intel_crtc_state *pipe_config,
87 struct intel_crtc_state *pipe_config,
144 int intel_dp_dsc_sink_min_compressed_bpp(struct intel_crtc_state *pipe_config);
146 struct intel_crtc_state *pipe_config,
161 const struct intel_crtc_state *pipe_config);
167 const struct intel_crtc_state *pipe_config);
H A Dintel_crt.c142 struct intel_crtc_state *pipe_config)
144 pipe_config->output_types |= BIT(INTEL_OUTPUT_ANALOG);
146 pipe_config->hw.adjusted_mode.flags |= intel_crt_get_flags(encoder);
148 pipe_config->hw.adjusted_mode.crtc_clock = pipe_config->port_clock;
152 struct intel_crtc_state *pipe_config)
154 lpt_pch_get_config(pipe_config);
156 hsw_ddi_get_config(encoder, pipe_config);
158 pipe_config->hw.adjusted_mode.flags &= ~(DRM_MODE_FLAG_PHSYNC |
162 pipe_config
141 intel_crt_get_config(struct intel_encoder *encoder, struct intel_crtc_state *pipe_config) argument
151 hsw_crt_get_config(struct intel_encoder *encoder, struct intel_crtc_state *pipe_config) argument
395 intel_crt_compute_config(struct intel_encoder *encoder, struct intel_crtc_state *pipe_config, struct drm_connector_state *conn_state) argument
411 pch_crt_compute_config(struct intel_encoder *encoder, struct intel_crtc_state *pipe_config, struct drm_connector_state *conn_state) argument
430 hsw_crt_compute_config(struct intel_encoder *encoder, struct intel_crtc_state *pipe_config, struct drm_connector_state *conn_state) argument
[all...]
H A Dintel_dp.c1417 const struct intel_crtc_state *pipe_config)
1426 !intel_crtc_has_type(pipe_config, INTEL_OUTPUT_DP_MST))
1434 const struct intel_crtc_state *pipe_config)
1436 return intel_dp_source_supports_fec(intel_dp, pipe_config) &&
1526 struct intel_crtc_state *pipe_config,
1536 pipe_config->dither_force_disable = bpp == 6 * 3;
1590 struct intel_crtc_state *pipe_config,
1594 int bpp, i, lane_count, clock = intel_dp_mode_clock(pipe_config, conn_state);
1600 int link_bpp = intel_dp_output_bpp(pipe_config->output_format, bpp);
1619 pipe_config
1416 intel_dp_source_supports_fec(struct intel_dp *intel_dp, const struct intel_crtc_state *pipe_config) argument
1432 intel_dp_supports_fec(struct intel_dp *intel_dp, const struct intel_connector *connector, const struct intel_crtc_state *pipe_config) argument
1525 intel_dp_adjust_compliance_config(struct intel_dp *intel_dp, struct intel_crtc_state *pipe_config, struct link_config_limits *limits) argument
1589 intel_dp_compute_link_config_wide(struct intel_dp *intel_dp, struct intel_crtc_state *pipe_config, const struct drm_connector_state *conn_state, const struct link_config_limits *limits) argument
1796 dsc_compute_link_config(struct intel_dp *intel_dp, struct intel_crtc_state *pipe_config, struct link_config_limits *limits, u16 compressed_bppx16, int timeslots) argument
1831 intel_dp_dsc_max_sink_compressed_bppx16(const struct intel_connector *connector, struct intel_crtc_state *pipe_config, int bpc) argument
1857 intel_dp_dsc_sink_min_compressed_bpp(struct intel_crtc_state *pipe_config) argument
1874 intel_dp_dsc_sink_max_compressed_bpp(const struct intel_connector *connector, struct intel_crtc_state *pipe_config, int bpc) argument
1907 icl_dsc_compute_link_config(struct intel_dp *intel_dp, struct intel_crtc_state *pipe_config, struct link_config_limits *limits, int dsc_max_bpp, int dsc_min_bpp, int pipe_bpp, int timeslots) argument
1948 xelpd_dsc_compute_link_config(struct intel_dp *intel_dp, const struct intel_connector *connector, struct intel_crtc_state *pipe_config, struct link_config_limits *limits, int dsc_max_bpp, int dsc_min_bpp, int pipe_bpp, int timeslots) argument
1995 dsc_compute_compressed_bpp(struct intel_dp *intel_dp, const struct intel_connector *connector, struct intel_crtc_state *pipe_config, struct link_config_limits *limits, int pipe_bpp, int timeslots) argument
2081 intel_dp_dsc_compute_pipe_bpp(struct intel_dp *intel_dp, struct intel_crtc_state *pipe_config, struct drm_connector_state *conn_state, struct link_config_limits *limits, int timeslots) argument
2140 intel_edp_dsc_compute_pipe_bpp(struct intel_dp *intel_dp, struct intel_crtc_state *pipe_config, struct drm_connector_state *conn_state, struct link_config_limits *limits) argument
2193 intel_dp_dsc_compute_config(struct intel_dp *intel_dp, struct intel_crtc_state *pipe_config, struct drm_connector_state *conn_state, struct link_config_limits *limits, int timeslots, bool compute_pipe_bpp) argument
2405 intel_dp_compute_link_config(struct intel_encoder *encoder, struct intel_crtc_state *pipe_config, struct drm_connector_state *conn_state, bool respect_downstream_limits) argument
2689 can_enable_drrs(struct intel_connector *connector, const struct intel_crtc_state *pipe_config, const struct drm_display_mode *downclock_mode) argument
2719 intel_dp_drrs_compute_config(struct intel_connector *connector, struct intel_crtc_state *pipe_config, int link_bpp_x16) argument
2825 intel_dp_audio_compute_config(struct intel_encoder *encoder, struct intel_crtc_state *pipe_config, struct drm_connector_state *conn_state) argument
2872 intel_dp_compute_config(struct intel_encoder *encoder, struct intel_crtc_state *pipe_config, struct drm_connector_state *conn_state) argument
[all...]
H A Dintel_dp_mst.c523 struct intel_crtc_state *pipe_config,
533 &pipe_config->hw.adjusted_mode;
538 if (pipe_config->fec_enable &&
539 !intel_dp_supports_fec(intel_dp, connector, pipe_config))
545 pipe_config->sink_format = INTEL_OUTPUT_FORMAT_RGB;
546 pipe_config->output_format = INTEL_OUTPUT_FORMAT_RGB;
547 pipe_config->has_pch_encoder = false;
552 pipe_config,
557 ret = intel_dp_mst_compute_link_config(encoder, pipe_config,
573 if (!intel_dp_mst_dsc_source_support(pipe_config))
522 intel_dp_mst_compute_config(struct intel_encoder *encoder, struct intel_crtc_state *pipe_config, struct drm_connector_state *conn_state) argument
1037 intel_mst_pre_pll_enable_dp(struct intel_atomic_state *state, struct intel_encoder *encoder, const struct intel_crtc_state *pipe_config, const struct drm_connector_state *conn_state) argument
1058 intel_mst_pre_enable_dp(struct intel_atomic_state *state, struct intel_encoder *encoder, const struct intel_crtc_state *pipe_config, const struct drm_connector_state *conn_state) argument
1120 intel_mst_enable_dp(struct intel_atomic_state *state, struct intel_encoder *encoder, const struct intel_crtc_state *pipe_config, const struct drm_connector_state *conn_state) argument
1190 intel_dp_mst_enc_get_config(struct intel_encoder *encoder, struct intel_crtc_state *pipe_config) argument
[all...]
H A Dicl_dsi.c277 const struct intel_crtc_state *pipe_config)
286 struct intel_crtc *crtc = to_intel_crtc(pipe_config->uapi.crtc);
302 &pipe_config->hw.adjusted_mode;
679 const struct intel_crtc_state *pipe_config)
683 struct intel_crtc *crtc = to_intel_crtc(pipe_config->uapi.crtc);
699 if (afe_clk(encoder, pipe_config) >= 1500 * 1000) {
725 if (pipe_config->dsc.compression_enable) {
792 configure_dual_link_mode(encoder, pipe_config);
1185 const struct intel_crtc_state *pipe_config,
1189 gen11_dsi_map_pll(encoder, pipe_config);
276 configure_dual_link_mode(struct intel_encoder *encoder, const struct intel_crtc_state *pipe_config) argument
678 gen11_dsi_configure_transcoder(struct intel_encoder *encoder, const struct intel_crtc_state *pipe_config) argument
1183 gen11_dsi_pre_enable(struct intel_atomic_state *state, struct intel_encoder *encoder, const struct intel_crtc_state *pipe_config, const struct drm_connector_state *conn_state) argument
1454 gen11_dsi_get_timings(struct intel_encoder *encoder, struct intel_crtc_state *pipe_config) argument
1509 gen11_dsi_get_cmd_mode_config(struct intel_dsi *intel_dsi, struct intel_crtc_state *pipe_config) argument
1521 gen11_dsi_get_config(struct intel_encoder *encoder, struct intel_crtc_state *pipe_config) argument
1614 gen11_dsi_compute_config(struct intel_encoder *encoder, struct intel_crtc_state *pipe_config, struct drm_connector_state *conn_state) argument
[all...]
H A Dintel_hdcp.h33 const struct intel_crtc_state *pipe_config,
H A Dintel_pipe_crc.c282 struct intel_crtc_state *pipe_config; local
299 pipe_config = intel_atomic_get_crtc_state(state, crtc);
300 if (IS_ERR(pipe_config)) {
301 ret = PTR_ERR(pipe_config);
305 pipe_config->uapi.mode_changed = pipe_config->has_psr;
306 pipe_config->crc_enabled = enable;
309 pipe_config->hw.active && crtc->pipe == PIPE_A &&
310 pipe_config->cpu_transcoder == TRANSCODER_EDP)
311 pipe_config
[all...]
H A Dintel_fdi.c181 struct intel_crtc_state *pipe_config,
185 struct drm_atomic_state *state = pipe_config->uapi.state;
193 pipe_name(pipe), pipe_config->fdi_lanes);
194 if (pipe_config->fdi_lanes > 4) {
197 pipe_name(pipe), pipe_config->fdi_lanes);
202 if (pipe_config->fdi_lanes > 2) {
205 pipe_config->fdi_lanes);
220 if (pipe_config->fdi_lanes <= 2)
232 pipe_name(pipe), pipe_config->fdi_lanes);
237 if (pipe_config
180 ilk_check_fdi_lanes(struct drm_device *dev, enum pipe pipe, struct intel_crtc_state *pipe_config, enum pipe *pipe_to_reduce) argument
281 intel_fdi_link_freq(struct drm_i915_private *i915, const struct intel_crtc_state *pipe_config) argument
318 ilk_fdi_compute_config(struct intel_crtc *crtc, struct intel_crtc_state *pipe_config) argument
351 intel_fdi_atomic_check_bw(struct intel_atomic_state *state, struct intel_crtc *crtc, struct intel_crtc_state *pipe_config, struct intel_link_bw_limits *limits) argument
[all...]
H A Dvlv_dsi.c272 struct intel_crtc_state *pipe_config,
279 struct drm_display_mode *adjusted_mode = &pipe_config->hw.adjusted_mode;
283 pipe_config->sink_format = INTEL_OUTPUT_FORMAT_RGB;
284 pipe_config->output_format = INTEL_OUTPUT_FORMAT_RGB;
290 ret = intel_panel_fitting(pipe_config, conn_state);
301 pipe_config->pipe_bpp = 24;
303 pipe_config->pipe_bpp = 18;
307 pipe_config->mode_flags |=
312 pipe_config->cpu_transcoder = TRANSCODER_DSI_C;
314 pipe_config
271 intel_dsi_compute_config(struct intel_encoder *encoder, struct intel_crtc_state *pipe_config, struct drm_connector_state *conn_state) argument
724 intel_dsi_pre_enable(struct intel_atomic_state *state, struct intel_encoder *encoder, const struct intel_crtc_state *pipe_config, const struct drm_connector_state *conn_state) argument
1010 bxt_dsi_get_pipe_config(struct intel_encoder *encoder, struct intel_crtc_state *pipe_config) argument
1173 intel_dsi_get_config(struct intel_encoder *encoder, struct intel_crtc_state *pipe_config) argument
1302 intel_dsi_prepare(struct intel_encoder *intel_encoder, const struct intel_crtc_state *pipe_config) argument
[all...]
H A Dintel_display.c2730 struct intel_crtc_state *pipe_config)
2734 enum transcoder cpu_transcoder = pipe_config->cpu_transcoder;
2735 struct drm_display_mode *adjusted_mode = &pipe_config->hw.adjusted_mode;
2766 if (intel_pipe_is_interlaced(pipe_config)) {
2796 struct intel_crtc_state *pipe_config)
2804 drm_rect_init(&pipe_config->pipe_src, 0, 0,
2808 intel_bigjoiner_adjust_pipe_src(pipe_config);
2938 struct intel_crtc_state *pipe_config)
2951 pipe_config->output_format = INTEL_OUTPUT_FORMAT_RGB;
2952 pipe_config
2729 intel_get_transcoder_timings(struct intel_crtc *crtc, struct intel_crtc_state *pipe_config) argument
2795 intel_get_pipe_src_size(struct intel_crtc *crtc, struct intel_crtc_state *pipe_config) argument
2937 i9xx_get_pipe_config(struct intel_crtc *crtc, struct intel_crtc_state *pipe_config) argument
3328 ilk_get_pipe_config(struct intel_crtc *crtc, struct intel_crtc_state *pipe_config) argument
3627 hsw_get_transcoder_state(struct intel_crtc *crtc, struct intel_crtc_state *pipe_config, struct intel_display_power_domain_set *power_domain_set) argument
3665 bxt_get_dsi_transcoder_state(struct intel_crtc *crtc, struct intel_crtc_state *pipe_config, struct intel_display_power_domain_set *power_domain_set) argument
3728 hsw_get_pipe_config(struct intel_crtc *crtc, struct intel_crtc_state *pipe_config) argument
3859 intel_crtc_dotclock(const struct intel_crtc_state *pipe_config) argument
4942 intel_pipe_config_compare(const struct intel_crtc_state *current_config, const struct intel_crtc_state *pipe_config, bool fastset) argument
[all...]
H A Dintel_ddi.c377 static void ddi_dotclock_get(struct intel_crtc_state *pipe_config) argument
380 if (pipe_config->has_pch_encoder)
383 pipe_config->hw.adjusted_mode.crtc_clock =
384 intel_crtc_dotclock(pipe_config);
2352 struct intel_crtc_state *pipe_config)
2354 struct intel_crtc *crtc = to_intel_crtc(pipe_config->uapi.crtc);
2364 pipe_config->splitter.enable = dss1 & SPLITTER_ENABLE;
2365 if (!pipe_config->splitter.enable)
2369 pipe_config->splitter.enable = false;
2379 pipe_config
2351 intel_ddi_mso_get_config(struct intel_encoder *encoder, struct intel_crtc_state *pipe_config) argument
3800 intel_ddi_read_func_ctl(struct intel_encoder *encoder, struct intel_crtc_state *pipe_config) argument
3925 intel_ddi_get_config(struct intel_encoder *encoder, struct intel_crtc_state *pipe_config) argument
4197 intel_ddi_compute_config(struct intel_encoder *encoder, struct intel_crtc_state *pipe_config, struct drm_connector_state *conn_state) argument
[all...]
H A Dintel_hdmi.h31 struct intel_crtc_state *pipe_config,
H A Dintel_vdsc.c239 static int intel_dsc_slice_dimensions_valid(struct intel_crtc_state *pipe_config, argument
242 if (pipe_config->output_format == INTEL_OUTPUT_FORMAT_RGB ||
243 pipe_config->output_format == INTEL_OUTPUT_FORMAT_YCBCR444) {
248 } else if (pipe_config->output_format == INTEL_OUTPUT_FORMAT_YCBCR420) {
262 int intel_dsc_compute_params(struct intel_crtc_state *pipe_config) argument
264 struct intel_crtc *crtc = to_intel_crtc(pipe_config->uapi.crtc);
266 struct drm_dsc_config *vdsc_cfg = &pipe_config->dsc.config;
267 u16 compressed_bpp = to_bpp_int(pipe_config->dsc.compressed_bpp_x16);
271 vdsc_cfg->pic_width = pipe_config->hw.adjusted_mode.crtc_hdisplay;
273 pipe_config
[all...]
H A Dintel_psr.h44 struct intel_crtc_state *pipe_config);
H A Dintel_hdmi.c254 const struct intel_crtc_state *pipe_config)
326 const struct intel_crtc_state *pipe_config)
329 enum pipe pipe = to_intel_crtc(pipe_config->uapi.crtc)->pipe;
404 const struct intel_crtc_state *pipe_config)
407 enum pipe pipe = to_intel_crtc(pipe_config->uapi.crtc)->pipe;
477 const struct intel_crtc_state *pipe_config)
480 enum pipe pipe = to_intel_crtc(pipe_config->uapi.crtc)->pipe;
552 const struct intel_crtc_state *pipe_config)
556 HSW_TVIDEO_DIP_CTL(pipe_config->cpu_transcoder));
2285 struct intel_crtc_state *pipe_config,
253 g4x_infoframes_enabled(struct intel_encoder *encoder, const struct intel_crtc_state *pipe_config) argument
325 ibx_infoframes_enabled(struct intel_encoder *encoder, const struct intel_crtc_state *pipe_config) argument
403 cpt_infoframes_enabled(struct intel_encoder *encoder, const struct intel_crtc_state *pipe_config) argument
476 vlv_infoframes_enabled(struct intel_encoder *encoder, const struct intel_crtc_state *pipe_config) argument
551 hsw_infoframes_enabled(struct intel_encoder *encoder, const struct intel_crtc_state *pipe_config) argument
2284 intel_hdmi_compute_config(struct intel_encoder *encoder, struct intel_crtc_state *pipe_config, struct drm_connector_state *conn_state) argument
[all...]
/linux-master/drivers/gpu/drm/amd/display/dc/
H A Ddc_dmub_srv.c566 pipe_data->pipe_config.vblank_data.drr_info.drr_in_use = true;
567 pipe_data->pipe_config.vblank_data.drr_info.use_ramping = false; // for now don't use ramping
568 pipe_data->pipe_config.vblank_data.drr_info.drr_window_size_ms = 4; // hardcode 4ms DRR window for now
599 pipe_data->pipe_config.vblank_data.drr_info.min_vtotal_supported = min_vtotal_supported;
600 pipe_data->pipe_config.vblank_data.drr_info.max_vtotal_supported = max_vtotal_supported;
601 pipe_data->pipe_config.vblank_data.drr_info.drr_vblank_start_margin = dc->caps.subvp_drr_vblank_start_margin_us;
645 pipe_data->pipe_config.vblank_data.pix_clk_100hz = vblank_pipe->stream->timing.pix_clk_100hz;
646 pipe_data->pipe_config.vblank_data.vblank_start = vblank_pipe->stream->timing.v_total -
648 pipe_data->pipe_config.vblank_data.vtotal = vblank_pipe->stream->timing.v_total;
649 pipe_data->pipe_config
[all...]

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