Searched refs:pipe_cnt (Results 1 - 25 of 34) sorted by relevance

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/linux-master/drivers/gpu/drm/amd/display/dc/dml/dcn32/
H A Ddcn32_fpu.h37 int pipe_cnt);
44 unsigned int pipe_cnt,
56 int pipe_cnt,
64 int pipe_cnt,
70 int pipe_cnt);
H A Ddcn32_fpu.c275 int pipe_cnt,
290 dcn32_internal_validate_bw(dc, context, pipes, &pipe_cnt, &vlevel, false);
324 * @pipe_cnt: [in] DML pipe count
333 int pipe_cnt)
347 get_vstartup(&context->bw_ctx.dml, pipes, pipe_cnt, pipe_idx);
349 get_vupdate_offset(&context->bw_ctx.dml, pipes, pipe_cnt, pipe_idx);
351 get_vupdate_width(&context->bw_ctx.dml, pipes, pipe_cnt, pipe_idx);
353 get_vready_offset(&context->bw_ctx.dml, pipes, pipe_cnt, pipe_idx);
448 * @pipe_cnt: number of DML pipes
468 unsigned int pipe_cnt,
272 dcn32_find_dummy_latency_index_for_fw_based_mclk_switch(struct dc *dc, struct dc_state *context, display_e2e_pipe_params_st *pipes, int pipe_cnt, int vlevel) argument
330 dcn32_helper_populate_phantom_dlg_params(struct dc *dc, struct dc_state *context, display_e2e_pipe_params_st *pipes, int pipe_cnt) argument
463 dcn32_set_phantom_stream_timing(struct dc *dc, struct dc_state *context, struct pipe_ctx *ref_pipe, struct dc_stream_state *phantom_stream, display_e2e_pipe_params_st *pipes, unsigned int pipe_cnt, unsigned int dc_pipe_idx) argument
1384 try_odm_power_optimization_and_revalidate( struct dc *dc, struct dc_state *context, display_e2e_pipe_params_st *pipes, int *split, bool *merge, unsigned int *vlevel, int pipe_cnt) argument
1428 dcn32_full_validate_bw_helper(struct dc *dc, struct dc_state *context, display_e2e_pipe_params_st *pipes, int *vlevel, int *split, bool *merge, int *pipe_cnt) argument
1640 dcn32_calculate_dlg_params(struct dc *dc, struct dc_state *context, display_e2e_pipe_params_st *pipes, int pipe_cnt, int vlevel) argument
1944 int pipe_cnt, i, pipe_idx; local
2267 dcn32_calculate_wm_and_dlg_fpu(struct dc *dc, struct dc_state *context, display_e2e_pipe_params_st *pipes, int pipe_cnt, int vlevel) argument
3326 dcn32_zero_pipe_dcc_fraction(display_e2e_pipe_params_st *pipes, int pipe_cnt) argument
[all...]
/linux-master/drivers/gpu/drm/amd/display/dc/dml/dcn20/
H A Ddcn20_fpu.c994 int pipe_cnt, i; local
998 for (i = 0, pipe_cnt = 0; i < dc->res_pool->pipe_count; i++) {
1005 pipes[pipe_cnt].dout.wb_enable = (wb_info->wb_enabled == true) ? 1 : 0;
1006 pipes[pipe_cnt].dout.num_active_wb++;
1007 pipes[pipe_cnt].dout.wb.wb_src_height = wb_info->dwb_params.cnv_params.crop_height;
1008 pipes[pipe_cnt].dout.wb.wb_src_width = wb_info->dwb_params.cnv_params.crop_width;
1009 pipes[pipe_cnt].dout.wb.wb_dst_width = wb_info->dwb_params.dest_width;
1010 pipes[pipe_cnt].dout.wb.wb_dst_height = wb_info->dwb_params.dest_height;
1011 pipes[pipe_cnt].dout.wb.wb_htaps_luma = 1;
1012 pipes[pipe_cnt]
1030 dcn20_fpu_set_wb_arb_params(struct mcif_arb_params *wb_arb_params, struct dc_state *context, display_e2e_pipe_params_st *pipes, int pipe_cnt, int i) argument
1137 dcn20_calculate_dlg_params(struct dc *dc, struct dc_state *context, display_e2e_pipe_params_st *pipes, int pipe_cnt, int vlevel) argument
1316 int pipe_cnt, i; local
1732 int pipe_cnt, i, pipe_idx; local
2032 int pipe_cnt = 0; local
2155 uint32_t pipe_cnt; local
2201 calculate_wm_set_for_vlevel(int vlevel, struct wm_range_table_entry *table_entry, struct dcn_watermarks *wm_set, struct display_mode_lib *dml, display_e2e_pipe_params_st *pipes, int pipe_cnt) argument
2238 int pipe_cnt, i, pipe_idx; local
2324 int pipe_cnt = 0; local
2474 int pipe_cnt, i, j; local
[all...]
H A Ddcn20_fpu.h38 int pipe_cnt, int i);
42 int pipe_cnt,
/linux-master/drivers/gpu/drm/amd/display/dc/dml/dcn30/
H A Ddcn30_fpu.h41 int pipe_cnt,
49 int pipe_cnt,
69 int pipe_cnt,
H A Ddcn30_fpu.c260 int pipe_cnt, i, j; local
267 for (i = 0, pipe_cnt = 0; i < dc->res_pool->pipe_count; i++) {
275 pipes[pipe_cnt].dout.wb_enable = 0;
276 pipes[pipe_cnt].dout.num_active_wb = 0;
282 pipes[pipe_cnt].dout.wb_enable = 1;
283 pipes[pipe_cnt].dout.num_active_wb++;
326 pipes[pipe_cnt].pipe.dest.pixel_rate_mhz,
333 pipes[pipe_cnt].pipe.dest.htotal,
338 pipes[pipe_cnt].dout.wb = dout_wb;
343 pipe_cnt
347 dcn30_fpu_set_mcif_arb_params(struct mcif_arb_params *wb_arb_params, struct display_mode_lib *dml, display_e2e_pipe_params_st *pipes, int pipe_cnt, int cur_pipe) argument
379 dcn30_fpu_calculate_wm_and_dlg( struct dc *dc, struct dc_state *context, display_e2e_pipe_params_st *pipes, int pipe_cnt, int vlevel) argument
691 dcn30_find_dummy_latency_index_for_fw_based_mclk_switch(struct dc *dc, struct dc_state *context, display_e2e_pipe_params_st *pipes, int pipe_cnt, int vlevel) argument
[all...]
/linux-master/drivers/gpu/drm/amd/display/dc/dml/dcn301/
H A Ddcn301_fpu.h40 int pipe_cnt,
H A Ddcn301_fpu.c297 int pipe_cnt)
311 wm_set->urgent_ns = get_wm_urgent(dml, pipes, pipe_cnt) * 1000;
312 wm_set->cstate_pstate.cstate_enter_plus_exit_ns = get_wm_stutter_enter_exit(dml, pipes, pipe_cnt) * 1000;
313 wm_set->cstate_pstate.cstate_exit_ns = get_wm_stutter_exit(dml, pipes, pipe_cnt) * 1000;
314 wm_set->cstate_pstate.pstate_change_ns = get_wm_dram_clock_change(dml, pipes, pipe_cnt) * 1000;
315 wm_set->pte_meta_urgent_ns = get_wm_memory_trip(dml, pipes, pipe_cnt) * 1000;
316 wm_set->frac_urg_bw_nom = get_fraction_of_urgent_bandwidth(dml, pipes, pipe_cnt) * 1000;
317 wm_set->frac_urg_bw_flip = get_fraction_of_urgent_bandwidth_imm_flip(dml, pipes, pipe_cnt) * 1000;
318 wm_set->urgent_latency_ns = get_urgent_latency(dml, pipes, pipe_cnt) * 1000;
415 int pipe_cnt,
292 calculate_wm_set_for_vlevel(int vlevel, struct wm_range_table_entry *table_entry, struct dcn_watermarks *wm_set, struct display_mode_lib *dml, display_e2e_pipe_params_st *pipes, int pipe_cnt) argument
412 dcn301_calculate_wm_and_dlg_fp(struct dc *dc, struct dc_state *context, display_e2e_pipe_params_st *pipes, int pipe_cnt, int vlevel_req) argument
[all...]
/linux-master/drivers/gpu/drm/amd/display/dc/dml/dcn314/
H A Ddcn314_fpu.c311 int i, pipe_cnt; local
321 for (i = 0, pipe_cnt = 0; i < dc->res_pool->pipe_count; i++) {
334 pipes[pipe_cnt].pipe.dest.vtotal = pipe->stream->adjust.v_total_min;
336 pipes[pipe_cnt].pipe.dest.vtotal = timing->v_total;
340 pipes[pipe_cnt].pipe.dest.vblank_nom = timing->v_total - pipes[pipe_cnt].pipe.dest.vactive;
341 pipes[pipe_cnt].pipe.dest.vblank_nom = min(pipes[pipe_cnt].pipe.dest.vblank_nom, num_lines);
346 pipes[pipe_cnt].pipe.dest.vblank_nom =
347 max(pipes[pipe_cnt]
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/linux-master/drivers/gpu/drm/amd/display/dc/dml/dcn31/
H A Ddcn31_fpu.h35 int pipe_cnt);
43 int pipe_cnt,
H A Ddcn31_fpu.c446 int pipe_cnt)
450 pipes[pipe_cnt].pipe.src.dcc_fraction_of_zs_req_luma = 0;
451 pipes[pipe_cnt].pipe.src.dcc_fraction_of_zs_req_chroma = 0;
485 int pipe_cnt,
500 if (pipe_cnt == 0) {
515 context->bw_ctx.bw.dcn.watermarks.a.urgent_ns = get_wm_urgent(&context->bw_ctx.dml, pipes, pipe_cnt) * 1000;
516 context->bw_ctx.bw.dcn.watermarks.a.cstate_pstate.cstate_enter_plus_exit_ns = get_wm_stutter_enter_exit(&context->bw_ctx.dml, pipes, pipe_cnt) * 1000;
517 context->bw_ctx.bw.dcn.watermarks.a.cstate_pstate.cstate_exit_ns = get_wm_stutter_exit(&context->bw_ctx.dml, pipes, pipe_cnt) * 1000;
518 context->bw_ctx.bw.dcn.watermarks.a.cstate_pstate.pstate_change_ns = get_wm_dram_clock_change(&context->bw_ctx.dml, pipes, pipe_cnt) * 1000;
519 context->bw_ctx.bw.dcn.watermarks.a.cstate_pstate.cstate_enter_plus_exit_z8_ns = get_wm_z8_stutter_enter_exit(&context->bw_ctx.dml, pipes, pipe_cnt) * 100
445 dcn31_zero_pipe_dcc_fraction(display_e2e_pipe_params_st *pipes, int pipe_cnt) argument
482 dcn31_calculate_wm_and_dlg_fp( struct dc *dc, struct dc_state *context, display_e2e_pipe_params_st *pipes, int pipe_cnt, int vlevel) argument
[all...]
/linux-master/drivers/gpu/drm/amd/display/dc/dml/dcn35/
H A Ddcn35_fpu.c440 int i, pipe_cnt; local
449 for (i = 0, pipe_cnt = 0; i < dc->res_pool->pipe_count; i++) {
466 pipes[pipe_cnt].pipe.dest.vtotal =
468 pipes[pipe_cnt].pipe.dest.vblank_nom = timing->v_total -
469 pipes[pipe_cnt].pipe.dest.vactive;
472 pipes[pipe_cnt].pipe.dest.vblank_nom = timing->v_total - pipes[pipe_cnt].pipe.dest.vactive;
473 pipes[pipe_cnt].pipe.dest.vblank_nom = min(pipes[pipe_cnt].pipe.dest.vblank_nom, num_lines);
478 pipes[pipe_cnt]
[all...]
/linux-master/drivers/gpu/drm/amd/display/dc/dml/dcn351/
H A Ddcn351_fpu.c475 int i, pipe_cnt; local
484 for (i = 0, pipe_cnt = 0; i < dc->res_pool->pipe_count; i++) {
501 pipes[pipe_cnt].pipe.dest.vtotal =
503 pipes[pipe_cnt].pipe.dest.vblank_nom = timing->v_total -
504 pipes[pipe_cnt].pipe.dest.vactive;
507 pipes[pipe_cnt].pipe.dest.vblank_nom = timing->v_total - pipes[pipe_cnt].pipe.dest.vactive;
508 pipes[pipe_cnt].pipe.dest.vblank_nom = min(pipes[pipe_cnt].pipe.dest.vblank_nom, num_lines);
513 pipes[pipe_cnt]
[all...]
/linux-master/drivers/gpu/drm/amd/display/dc/resource/dcn30/
H A Ddcn30_resource.h52 int pipe_cnt);
72 int pipe_cnt,
106 display_e2e_pipe_params_st *pipes, int pipe_cnt, int vlevel);
H A Ddcn30_resource.c1325 int i, pipe_cnt; local
1332 for (i = 0, pipe_cnt = 0; i < dc->res_pool->pipe_count; i++) {
1336 pipes[pipe_cnt++].pipe.scale_ratio_depth.lb_depth =
1340 return pipe_cnt;
1378 int pipe_cnt)
1408 dcn30_fpu_set_mcif_arb_params(wb_arb_params, dml, pipes, pipe_cnt, j);
1642 int pipe_cnt, i, pipe_idx, vlevel; local
1653 pipe_cnt = dc->res_pool->funcs->populate_dml_pipes(dc, context, pipes, fast_validate);
1655 if (!pipe_cnt) {
1660 dml_log_pipe_params(&context->bw_ctx.dml, pipes, pipe_cnt);
1374 dcn30_set_mcif_arb_params( struct dc *dc, struct dc_state *context, display_e2e_pipe_params_st *pipes, int pipe_cnt) argument
2027 dcn30_calculate_wm_and_dlg( struct dc *dc, struct dc_state *context, display_e2e_pipe_params_st *pipes, int pipe_cnt, int vlevel) argument
2047 int pipe_cnt = 0; local
[all...]
/linux-master/drivers/gpu/drm/amd/display/dc/resource/dcn31/
H A Ddcn31_resource.h46 int pipe_cnt,
60 int pipe_cnt);
H A Ddcn31_resource.c1621 uint32_t pipe_cnt; local
1626 pipe_cnt = dcn20_populate_dml_pipes_from_context(dc, context, pipes, fast_validate);
1628 for (i = 0; i < pipe_cnt; i++) {
1631 //pipes[pipe_cnt].pipe.src.hostvm = dc->res_pool->hubbub->riommu_active;
1638 return pipe_cnt;
1646 int i, pipe_cnt; local
1655 for (i = 0, pipe_cnt = 0; i < dc->res_pool->pipe_count; i++) {
1672 pipes[pipe_cnt].pipe.src.immediate_flip = true;
1673 pipes[pipe_cnt].pipe.src.unbounded_req_mode = false;
1674 pipes[pipe_cnt]
1723 dcn31_calculate_wm_and_dlg( struct dc *dc, struct dc_state *context, display_e2e_pipe_params_st *pipes, int pipe_cnt, int vlevel) argument
1745 dcn31_set_mcif_arb_params(struct dc *dc, struct dc_state *context, display_e2e_pipe_params_st *pipes, int pipe_cnt) argument
1764 int pipe_cnt = 0; local
[all...]
/linux-master/drivers/gpu/drm/amd/display/dc/resource/dcn315/
H A Ddcn315_resource.c1664 int i, pipe_cnt, crb_idx, crb_pipes; local
1675 for (i = 0, pipe_cnt = 0, crb_pipes = 0; i < dc->res_pool->pipe_count; i++) {
1688 pipes[pipe_cnt].pipe.src.immediate_flip = true;
1690 pipes[pipe_cnt].pipe.src.unbounded_req_mode = false;
1691 pipes[pipe_cnt].pipe.dest.vfront_porch = timing->v_front_porch;
1692 pipes[pipe_cnt].pipe.src.dcc_rate = 3;
1693 pipes[pipe_cnt].dout.dsc_input_bpc = 0;
1695 dcn31_zero_pipe_dcc_fraction(pipes, pipe_cnt);
1697 int bpp = source_format_to_bpp(pipes[pipe_cnt].pipe.src.source_format);
1712 pipes[pipe_cnt]
[all...]
/linux-master/drivers/gpu/drm/amd/display/dc/dml/
H A Ddisplay_mode_lib.h106 int pipe_cnt);
/linux-master/drivers/gpu/drm/amd/display/dc/dml2/
H A Ddml2_utils.h111 * @pipe_cnt : DML functions to obtain RQ, TTu and DLG params need a pipe_index.
112 * This helps provide pipe_index in the pipe_cnt loop.
117 void dml2_calculate_rq_and_dlg_params(const struct dc *dc, struct dc_state *context, struct resource_context *out_new_hw_state, struct dml2_context *in_ctx, unsigned int pipe_cnt);
/linux-master/drivers/gpu/drm/amd/display/dc/dcn32/
H A Ddcn32_resource_helpers.c334 uint8_t pipe_cnt = 0; local
385 for (i = 0, pipe_cnt = 0; i < dc->res_pool->pipe_count; i++) {
388 pipes[pipe_cnt].pipe.src.det_size_override = pipe_segments[i] * DCN3_2_DET_SEG_SIZE;
389 pipe_cnt++;
400 int i, pipe_cnt; local
405 for (i = 0, pipe_cnt = 0; i < dc->res_pool->pipe_count; i++) {
411 pipe_cnt++;
418 if (pipe_cnt == 1) {
763 int i, pipe_cnt; local
767 for (i = 0, pipe_cnt
[all...]
/linux-master/drivers/gpu/drm/amd/display/dc/resource/dcn32/
H A Ddcn32_resource.c1680 unsigned int pipe_cnt,
1693 dcn32_set_phantom_stream_timing(dc, context, ref_pipe, phantom_stream, pipes, pipe_cnt, dc_pipe_idx);
1705 unsigned int pipe_cnt,
1714 phantom_stream = dcn32_enable_phantom_stream(dc, context, pipes, pipe_cnt, index);
1741 int pipe_cnt = 0; local
1755 out = dcn32_internal_validate_bw(dc, context, pipes, &pipe_cnt, &vlevel, fast_validate);
1758 if (pipe_cnt == 0)
1771 dc->res_pool->funcs->calculate_wm_and_dlg(dc, context, pipes, pipe_cnt, vlevel);
1813 int i, pipe_cnt; local
1821 for (i = 0, pipe_cnt
1677 dcn32_enable_phantom_stream(struct dc *dc, struct dc_state *context, display_e2e_pipe_params_st *pipes, unsigned int pipe_cnt, unsigned int dc_pipe_idx) argument
1703 dcn32_add_phantom_pipes(struct dc *dc, struct dc_state *context, display_e2e_pipe_params_st *pipes, unsigned int pipe_cnt, unsigned int index) argument
1920 dcn32_calculate_wm_and_dlg(struct dc *dc, struct dc_state *context, display_e2e_pipe_params_st *pipes, int pipe_cnt, int vlevel) argument
[all...]
/linux-master/drivers/gpu/drm/amd/display/dc/resource/dcn316/
H A Ddcn316_resource.c1615 int i, pipe_cnt; local
1624 for (i = 0, pipe_cnt = 0; i < dc->res_pool->pipe_count; i++) {
1637 pipes[pipe_cnt].pipe.src.immediate_flip = true;
1639 pipes[pipe_cnt].pipe.src.unbounded_req_mode = false;
1640 pipes[pipe_cnt].pipe.dest.vfront_porch = timing->v_front_porch;
1641 pipes[pipe_cnt].pipe.src.dcc_rate = 3;
1642 pipes[pipe_cnt].dout.dsc_input_bpc = 0;
1644 dcn31_zero_pipe_dcc_fraction(pipes, pipe_cnt);
1647 if (pipes[pipe_cnt].dout.dsc_enable) {
1650 pipes[pipe_cnt]
[all...]
/linux-master/drivers/gpu/drm/amd/display/dc/inc/
H A Dcore_types.h88 int pipe_cnt,
175 int pipe_cnt);
200 unsigned int pipe_cnt,
/linux-master/drivers/gpu/drm/amd/display/dc/resource/dcn20/
H A Ddcn20_resource.h121 int pipe_cnt);

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