Searched refs:opcode (Results 1 - 25 of 83) sorted by relevance

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/u-boot/arch/mips/dts/include/dt-bindings/sound/
H A Dazalia.h25 #define AZALIA_SET_BYTE(codec, nid, opcode, val, byte) \
28 ((opcode) + (byte)) << AZALIA_VERB_SHIFT | \
32 #define AZALIA_WORD(codec, nid, opcode, val) \
33 (AZALIA_SET_BYTE(codec, nid, opcode, val, 0) | \
34 AZALIA_SET_BYTE(codec, nid, opcode, val, 1) | \
35 AZALIA_SET_BYTE(codec, nid, opcode, val, 2) | \
36 AZALIA_SET_BYTE(codec, nid, opcode, val, 3))
/u-boot/arch/nios2/dts/include/dt-bindings/sound/
H A Dazalia.h25 #define AZALIA_SET_BYTE(codec, nid, opcode, val, byte) \
28 ((opcode) + (byte)) << AZALIA_VERB_SHIFT | \
32 #define AZALIA_WORD(codec, nid, opcode, val) \
33 (AZALIA_SET_BYTE(codec, nid, opcode, val, 0) | \
34 AZALIA_SET_BYTE(codec, nid, opcode, val, 1) | \
35 AZALIA_SET_BYTE(codec, nid, opcode, val, 2) | \
36 AZALIA_SET_BYTE(codec, nid, opcode, val, 3))
/u-boot/arch/arm/dts/include/dt-bindings/sound/
H A Dazalia.h25 #define AZALIA_SET_BYTE(codec, nid, opcode, val, byte) \
28 ((opcode) + (byte)) << AZALIA_VERB_SHIFT | \
32 #define AZALIA_WORD(codec, nid, opcode, val) \
33 (AZALIA_SET_BYTE(codec, nid, opcode, val, 0) | \
34 AZALIA_SET_BYTE(codec, nid, opcode, val, 1) | \
35 AZALIA_SET_BYTE(codec, nid, opcode, val, 2) | \
36 AZALIA_SET_BYTE(codec, nid, opcode, val, 3))
/u-boot/arch/microblaze/dts/include/dt-bindings/sound/
H A Dazalia.h25 #define AZALIA_SET_BYTE(codec, nid, opcode, val, byte) \
28 ((opcode) + (byte)) << AZALIA_VERB_SHIFT | \
32 #define AZALIA_WORD(codec, nid, opcode, val) \
33 (AZALIA_SET_BYTE(codec, nid, opcode, val, 0) | \
34 AZALIA_SET_BYTE(codec, nid, opcode, val, 1) | \
35 AZALIA_SET_BYTE(codec, nid, opcode, val, 2) | \
36 AZALIA_SET_BYTE(codec, nid, opcode, val, 3))
/u-boot/arch/sandbox/dts/include/dt-bindings/sound/
H A Dazalia.h25 #define AZALIA_SET_BYTE(codec, nid, opcode, val, byte) \
28 ((opcode) + (byte)) << AZALIA_VERB_SHIFT | \
32 #define AZALIA_WORD(codec, nid, opcode, val) \
33 (AZALIA_SET_BYTE(codec, nid, opcode, val, 0) | \
34 AZALIA_SET_BYTE(codec, nid, opcode, val, 1) | \
35 AZALIA_SET_BYTE(codec, nid, opcode, val, 2) | \
36 AZALIA_SET_BYTE(codec, nid, opcode, val, 3))
/u-boot/arch/x86/dts/include/dt-bindings/sound/
H A Dazalia.h25 #define AZALIA_SET_BYTE(codec, nid, opcode, val, byte) \
28 ((opcode) + (byte)) << AZALIA_VERB_SHIFT | \
32 #define AZALIA_WORD(codec, nid, opcode, val) \
33 (AZALIA_SET_BYTE(codec, nid, opcode, val, 0) | \
34 AZALIA_SET_BYTE(codec, nid, opcode, val, 1) | \
35 AZALIA_SET_BYTE(codec, nid, opcode, val, 2) | \
36 AZALIA_SET_BYTE(codec, nid, opcode, val, 3))
/u-boot/arch/xtensa/dts/include/dt-bindings/sound/
H A Dazalia.h25 #define AZALIA_SET_BYTE(codec, nid, opcode, val, byte) \
28 ((opcode) + (byte)) << AZALIA_VERB_SHIFT | \
32 #define AZALIA_WORD(codec, nid, opcode, val) \
33 (AZALIA_SET_BYTE(codec, nid, opcode, val, 0) | \
34 AZALIA_SET_BYTE(codec, nid, opcode, val, 1) | \
35 AZALIA_SET_BYTE(codec, nid, opcode, val, 2) | \
36 AZALIA_SET_BYTE(codec, nid, opcode, val, 3))
/u-boot/include/dt-bindings/sound/
H A Dazalia.h25 #define AZALIA_SET_BYTE(codec, nid, opcode, val, byte) \
28 ((opcode) + (byte)) << AZALIA_VERB_SHIFT | \
32 #define AZALIA_WORD(codec, nid, opcode, val) \
33 (AZALIA_SET_BYTE(codec, nid, opcode, val, 0) | \
34 AZALIA_SET_BYTE(codec, nid, opcode, val, 1) | \
35 AZALIA_SET_BYTE(codec, nid, opcode, val, 2) | \
36 AZALIA_SET_BYTE(codec, nid, opcode, val, 3))
/u-boot/post/lib_powerpc/
H A Dcpu_asm.h112 #define ASM_0(opcode) (opcode)
113 #define ASM_1(opcode, rd) ((opcode) + \
115 #define ASM_1C(opcode, cr) ((opcode) + \
117 #define ASM_11(opcode, rd, rs) ((opcode) + \
120 #define ASM_11C(opcode, cd, cs) ((opcode)
[all...]
/u-boot/arch/arm/mach-zynq/
H A Dps7_spl_init.c88 unsigned long opcode; local
97 opcode = ptr[0];
98 if (opcode == OPCODE_EXIT)
100 addr = (opcode & OPCODE_ADDRESS_MASK);
102 switch (opcode & ~OPCODE_ADDRESS_MASK) {
/u-boot/drivers/led/
H A Dled_lp5562.c341 u8 opcode = 0; local
375 program[opcode++] =
380 program[opcode++] =
386 program[opcode++] =
390 program[opcode++] =
396 program[opcode++] = 0x00;
403 program[opcode++] =
409 program[opcode++] =
415 program[opcode++] =
422 program[opcode
[all...]
/u-boot/drivers/spi/
H A Dca_sflash.c420 struct spi_mem_op *op, u8 opcode)
430 GENMASK(31, 0), CA_SF_AR_ACCODE(opcode));
432 if (opcode == CA_SF_AC_OP_EXTEND) { /* read_data, write_data */
446 GENMASK(31, 0), CA_SF_EAR_OP(op->cmd.opcode)
458 CA_SF_AR_OP(op->cmd.opcode));
462 if (opcode == CA_SF_AC_OP_4_ADDR) { /* erase_op */
491 u8 opcode; local
494 __func__, op->cmd.opcode, op->addr.val,
498 opcode = CA_SF_AC_OP;
500 opcode
419 _ca_sflash_issue_cmd(struct ca_sflash_priv *priv, struct spi_mem_op *op, u8 opcode) argument
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H A Dbcmbca_hsspi.c220 u16 opcode = 0; local
231 opcode = HSSPI_FIFO_OP_READ_WRITE;
233 opcode = HSSPI_FIFO_OP_CODE_R;
235 opcode = HSSPI_FIFO_OP_CODE_W;
237 if (opcode != HSSPI_FIFO_OP_CODE_R)
241 if ((opcode == HSSPI_FIFO_OP_CODE_R && (plat->mode & SPI_RX_DUAL)) ||
242 (opcode == HSSPI_FIFO_OP_CODE_W && (plat->mode & SPI_TX_DUAL))) {
243 opcode |= HSSPI_FIFO_OP_MBIT_MASK;
269 writew(cpu_to_be16(opcode | (curr_step & HSSPI_FIFO_OP_BYTES_MASK)),
H A Dcadence_qspi_apb.c395 ext = op->cmd.opcode & 0xff;
419 /* Set up command opcode extension. */
465 u8 opcode; local
468 opcode = op->cmd.opcode >> 8;
470 opcode = op->cmd.opcode;
472 if (opcode == CMD_4BYTE_OCTAL_READ && !priv->dtr)
473 opcode = CMD_4BYTE_FAST_READ;
475 reg = opcode << CQSPI_REG_CMDCTRL_OPCODE_LS
556 u8 opcode; local
619 u8 opcode; local
788 u8 opcode; local
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H A Dbcm63xx_hsspi.c261 uint16_t opcode = 0; local
271 opcode = HSSPI_FIFO_OP_READ_WRITE;
273 opcode = HSSPI_FIFO_OP_CODE_R;
275 opcode = HSSPI_FIFO_OP_CODE_W;
277 if (opcode != HSSPI_FIFO_OP_CODE_R)
281 if ((opcode == HSSPI_FIFO_OP_CODE_R && (plat->mode & SPI_RX_DUAL)) ||
282 (opcode == HSSPI_FIFO_OP_CODE_W && (plat->mode & SPI_TX_DUAL))) {
283 opcode |= HSSPI_FIFO_OP_MBIT_MASK;
309 writew(cpu_to_be16(opcode | (curr_step & HSSPI_FIFO_OP_BYTES_MASK)),
402 uint16_t opcode local
[all...]
H A Dcadence_ospi_versal.c25 u8 opcode, addr_bytes, *rxbuf, dummy_cycles; local
83 opcode = CMD_4BYTE_FAST_READ;
85 writel((dummy_cycles << CQSPI_REG_RD_INSTR_DUMMY_LSB) | opcode,
88 reg = opcode << CQSPI_REG_CMDCTRL_OPCODE_LSB;
H A Dich.c169 ich_writeb(ctlr, trans->opcode, ctlr->opmenu);
180 if (trans->opcode == SPI_OPCODE_WREN)
186 if (opmenu[opcode_index] == trans->opcode)
191 debug("ICH SPI: Opcode %x not found\n", trans->opcode);
280 if (trans->opcode != op->cmd.opcode)
281 trans->opcode = op->cmd.opcode;
283 if (lock && trans->opcode == SPI_OPCODE_WRDIS)
286 if (trans->opcode
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/u-boot/cmd/
H A Ditest.c31 int opcode; /* internal representation of opcode */ member in struct:op_tbl_s
166 return (stringcomp(arg1, arg2, optp->opcode));
168 return (arithcomp (arg1, arg2, optp->opcode, w));
/u-boot/drivers/mmc/
H A Dcv1800b_sdhci.c34 static int cv1800b_execute_tuning(struct mmc *mmc, u8 opcode) argument
47 if (mmc_send_tuning(host->mmc, opcode)) {
H A Diproc_sdhci.c180 static int sdhci_iproc_execute_tuning(struct mmc *mmc, u8 opcode) argument
191 cmd.cmdidx = opcode;
195 if (opcode == MMC_CMD_SEND_TUNING_BLOCK_HS200 && mmc->bus_width == 8)
204 if (opcode == MMC_CMD_SEND_TUNING_BLOCK)
222 printf("%s:Tuning failed, opcode = 0x%02x\n", __func__, opcode);
H A Dmtk-sd.c467 u32 opcode = cmd->cmdidx; local
473 switch (opcode) {
502 rawcmd |= ((opcode << SDC_CMD_CMD_S) & SDC_CMD_CMD_M) |
507 if (opcode == MMC_CMD_STOP_TRANSMISSION)
1104 static int hs400_tune_response(struct udevice *dev, u32 opcode) argument
1134 cmd_err = mmc_send_tuning(mmc, opcode);
1154 static int msdc_tune_response(struct udevice *dev, u32 opcode) argument
1184 cmd_err = mmc_send_tuning(mmc, opcode);
1206 cmd_err = mmc_send_tuning(mmc, opcode);
1241 cmd_err = mmc_send_tuning(mmc, opcode);
1258 msdc_tune_data(struct udevice *dev, u32 opcode) argument
1348 msdc_tune_together(struct udevice *dev, u32 opcode) argument
1406 msdc_execute_tuning(struct udevice *dev, uint opcode) argument
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/u-boot/drivers/nvme/
H A Dnvme.h227 __u8 opcode; member in struct:nvme_common_command
239 __u8 opcode; member in struct:nvme_rw_command
281 __u8 opcode; member in struct:nvme_dsm_cmd
358 __u8 opcode; member in struct:nvme_identify
370 __u8 opcode; member in struct:nvme_features
383 __u8 opcode; member in struct:nvme_create_cq
397 __u8 opcode; member in struct:nvme_create_sq
411 __u8 opcode; member in struct:nvme_delete_queue
421 __u8 opcode; member in struct:nvme_abort_cmd
431 __u8 opcode; member in struct:nvme_download_firmware
443 __u8 opcode; member in struct:nvme_format_cmd
[all...]
/u-boot/drivers/mtd/spi/
H A Dspi-nor-tiny.c76 static int spi_nor_write_reg(struct spi_nor *nor, u8 opcode, u8 *buf, int len) argument
78 struct spi_mem_op op = SPI_MEM_OP(SPI_MEM_OP_CMD(opcode, 1),
177 static u8 spi_nor_convert_opcode(u8 opcode, const u8 table[][2], size_t size) argument
182 if (table[i][0] == opcode)
186 return opcode;
189 static inline u8 spi_nor_convert_3to4_read(u8 opcode) argument
200 return spi_nor_convert_opcode(opcode, spi_nor_3to4_read,
563 u8 opcode,
568 read->opcode = opcode;
560 spi_nor_set_read_settings(struct spi_nor_read_command *read, u8 num_mode_clocks, u8 num_wait_states, u8 opcode, enum spi_nor_protocol proto) argument
[all...]
/u-boot/test/image/
H A Dspl_load_net.c100 u16 opcode; member in struct:tftp_hdr
138 if (htons(tftp->opcode) != TFTP_RRQ)
144 if (htons(tftp->opcode) != TFTP_ACK)
185 tftpr->opcode = htons(TFTP_DATA);
/u-boot/board/gdsys/a38x/
H A Dhre.c370 * @brief executes the next opcode on the hash register engine.
372 * @param[in,out] ip pointer to the opcode (instruction pointer)
381 uint8_t opcode; local
396 opcode = **ip;
403 opcode, src_spec, dst_spec, data_size);
405 if ((opcode & 0x80) && (data_size + 4) > *code_size)
412 (opcode & 0x40) ? HREG_RDWR : HREG_WR);
416 switch (opcode) {
486 if (opcode & 0x80) {

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