1// SPDX-License-Identifier: GPL-2.0+ 2/* 3 * Copyright (C) 2017 ��lvaro Fern��ndez Rojas <noltari@gmail.com> 4 * 5 * Derived from linux/drivers/spi/spi-bcm63xx-hsspi.c: 6 * Copyright (C) 2000-2010 Broadcom Corporation 7 * Copyright (C) 2012-2013 Jonas Gorski <jogo@openwrt.org> 8 * Copyright (C) 2021 Broadcom Ltd 9 */ 10 11#include <asm/io.h> 12#include <clk.h> 13#include <spi.h> 14#include <reset.h> 15#include <wait_bit.h> 16#include <dm.h> 17#include <dm/device_compat.h> 18 19#define HSSPI_PP 0 20 21#define SPI_MAX_SYNC_CLOCK 30000000 22 23/* SPI Control register */ 24#define SPI_CTL_REG 0x000 25#define SPI_CTL_CS_POL_SHIFT 0 26#define SPI_CTL_CS_POL_MASK (0xff << SPI_CTL_CS_POL_SHIFT) 27#define SPI_CTL_CLK_GATE_SHIFT 16 28#define SPI_CTL_CLK_GATE_MASK BIT(SPI_CTL_CLK_GATE_SHIFT) 29#define SPI_CTL_CLK_POL_SHIFT 17 30#define SPI_CTL_CLK_POL_MASK BIT(SPI_CTL_CLK_POL_SHIFT) 31 32/* SPI Interrupts registers */ 33#define SPI_IR_STAT_REG 0x008 34#define SPI_IR_ST_MASK_REG 0x00c 35#define SPI_IR_MASK_REG 0x010 36 37#define SPI_IR_CLEAR_ALL 0xff001f1f 38 39/* SPI Ping-Pong Command registers */ 40#define SPI_CMD_REG (0x080 + (0x40 * (HSSPI_PP)) + 0x00) 41#define SPI_CMD_OP_SHIFT 0 42#define SPI_CMD_OP_START BIT(SPI_CMD_OP_SHIFT) 43#define SPI_CMD_PFL_SHIFT 8 44#define SPI_CMD_PFL_MASK (0x7 << SPI_CMD_PFL_SHIFT) 45#define SPI_CMD_SLAVE_SHIFT 12 46#define SPI_CMD_SLAVE_MASK (0x7 << SPI_CMD_SLAVE_SHIFT) 47 48/* SPI Ping-Pong Status registers */ 49#define SPI_STAT_REG (0x080 + (0x40 * (HSSPI_PP)) + 0x04) 50#define SPI_STAT_SRCBUSY_SHIFT 1 51#define SPI_STAT_SRCBUSY_MASK BIT(SPI_STAT_SRCBUSY_SHIFT) 52 53/* SPI Profile Clock registers */ 54#define SPI_PFL_CLK_REG(x) (0x100 + (0x20 * (x)) + 0x00) 55#define SPI_PFL_CLK_FREQ_SHIFT 0 56#define SPI_PFL_CLK_FREQ_MASK (0x3fff << SPI_PFL_CLK_FREQ_SHIFT) 57#define SPI_PFL_CLK_RSTLOOP_SHIFT 15 58#define SPI_PFL_CLK_RSTLOOP_MASK BIT(SPI_PFL_CLK_RSTLOOP_SHIFT) 59 60/* SPI Profile Signal registers */ 61#define SPI_PFL_SIG_REG(x) (0x100 + (0x20 * (x)) + 0x04) 62#define SPI_PFL_SIG_LATCHRIS_SHIFT 12 63#define SPI_PFL_SIG_LATCHRIS_MASK BIT(SPI_PFL_SIG_LATCHRIS_SHIFT) 64#define SPI_PFL_SIG_LAUNCHRIS_SHIFT 13 65#define SPI_PFL_SIG_LAUNCHRIS_MASK BIT(SPI_PFL_SIG_LAUNCHRIS_SHIFT) 66#define SPI_PFL_SIG_ASYNCIN_SHIFT 16 67#define SPI_PFL_SIG_ASYNCIN_MASK BIT(SPI_PFL_SIG_ASYNCIN_SHIFT) 68 69/* SPI Profile Mode registers */ 70#define SPI_PFL_MODE_REG(x) (0x100 + (0x20 * (x)) + 0x08) 71#define SPI_PFL_MODE_FILL_SHIFT 0 72#define SPI_PFL_MODE_FILL_MASK (0xff << SPI_PFL_MODE_FILL_SHIFT) 73#define SPI_PFL_MODE_MDRDSZ_SHIFT 16 74#define SPI_PFL_MODE_MDRDSZ_MASK BIT(SPI_PFL_MODE_MDRDSZ_SHIFT) 75#define SPI_PFL_MODE_MDWRSZ_SHIFT 18 76#define SPI_PFL_MODE_MDWRSZ_MASK BIT(SPI_PFL_MODE_MDWRSZ_SHIFT) 77#define SPI_PFL_MODE_3WIRE_SHIFT 20 78#define SPI_PFL_MODE_3WIRE_MASK BIT(SPI_PFL_MODE_3WIRE_SHIFT) 79 80/* SPI Ping-Pong FIFO registers */ 81#define HSSPI_FIFO_SIZE 0x200 82#define HSSPI_FIFO_BASE (0x200 + \ 83 (HSSPI_FIFO_SIZE * HSSPI_PP)) 84 85/* SPI Ping-Pong FIFO OP register */ 86#define HSSPI_FIFO_OP_SIZE 0x2 87#define HSSPI_FIFO_OP_REG (HSSPI_FIFO_BASE + 0x00) 88#define HSSPI_FIFO_OP_BYTES_SHIFT 0 89#define HSSPI_FIFO_OP_BYTES_MASK (0x3ff << HSSPI_FIFO_OP_BYTES_SHIFT) 90#define HSSPI_FIFO_OP_MBIT_SHIFT 11 91#define HSSPI_FIFO_OP_MBIT_MASK BIT(HSSPI_FIFO_OP_MBIT_SHIFT) 92#define HSSPI_FIFO_OP_CODE_SHIFT 13 93#define HSSPI_FIFO_OP_READ_WRITE (1 << HSSPI_FIFO_OP_CODE_SHIFT) 94#define HSSPI_FIFO_OP_CODE_W (2 << HSSPI_FIFO_OP_CODE_SHIFT) 95#define HSSPI_FIFO_OP_CODE_R (3 << HSSPI_FIFO_OP_CODE_SHIFT) 96 97#define HSSPI_MAX_DATA_SIZE (HSSPI_FIFO_SIZE - HSSPI_FIFO_OP_SIZE) 98 99#define SPIM_CTRL_CS_OVERRIDE_SEL_SHIFT 0 100#define SPIM_CTRL_CS_OVERRIDE_SEL_MASK 0xff 101#define SPIM_CTRL_CS_OVERRIDE_VAL_SHIFT 8 102#define SPIM_CTRL_CS_OVERRIDE_VAL_MASK 0xff 103 104struct bcmbca_hsspi_priv { 105 void __iomem *regs; 106 void __iomem *spim_ctrl; 107 u32 clk_rate; 108 u8 num_cs; 109 u8 cs_pols; 110 u32 speed; 111}; 112 113static int bcmbca_hsspi_cs_info(struct udevice *bus, uint cs, 114 struct spi_cs_info *info) 115{ 116 struct bcmbca_hsspi_priv *priv = dev_get_priv(bus); 117 118 if (cs >= priv->num_cs) { 119 dev_err(bus, "no cs %u\n", cs); 120 return -EINVAL; 121 } 122 123 return 0; 124} 125 126static int bcmbca_hsspi_set_mode(struct udevice *bus, uint mode) 127{ 128 struct bcmbca_hsspi_priv *priv = dev_get_priv(bus); 129 130 /* clock polarity */ 131 if (mode & SPI_CPOL) 132 setbits_32(priv->regs + SPI_CTL_REG, SPI_CTL_CLK_POL_MASK); 133 else 134 clrbits_32(priv->regs + SPI_CTL_REG, SPI_CTL_CLK_POL_MASK); 135 136 return 0; 137} 138 139static int bcmbca_hsspi_set_speed(struct udevice *bus, uint speed) 140{ 141 struct bcmbca_hsspi_priv *priv = dev_get_priv(bus); 142 143 priv->speed = speed; 144 145 return 0; 146} 147 148static void bcmbca_hsspi_setup_clock(struct bcmbca_hsspi_priv *priv, 149 struct dm_spi_slave_plat *plat) 150{ 151 u32 clr, set; 152 153 /* profile clock */ 154 set = DIV_ROUND_UP(priv->clk_rate, priv->speed); 155 set = DIV_ROUND_UP(2048, set); 156 set &= SPI_PFL_CLK_FREQ_MASK; 157 set |= SPI_PFL_CLK_RSTLOOP_MASK; 158 writel(set, priv->regs + SPI_PFL_CLK_REG(plat->cs)); 159 160 /* profile signal */ 161 set = 0; 162 clr = SPI_PFL_SIG_LAUNCHRIS_MASK | 163 SPI_PFL_SIG_LATCHRIS_MASK | 164 SPI_PFL_SIG_ASYNCIN_MASK; 165 166 /* latch/launch config */ 167 if (plat->mode & SPI_CPHA) 168 set |= SPI_PFL_SIG_LAUNCHRIS_MASK; 169 else 170 set |= SPI_PFL_SIG_LATCHRIS_MASK; 171 172 /* async clk */ 173 if (priv->speed > SPI_MAX_SYNC_CLOCK) 174 set |= SPI_PFL_SIG_ASYNCIN_MASK; 175 176 clrsetbits_32(priv->regs + SPI_PFL_SIG_REG(plat->cs), clr, set); 177 178 /* global control */ 179 set = 0; 180 clr = 0; 181 182 if (priv->cs_pols & BIT(plat->cs)) 183 set |= BIT(plat->cs); 184 else 185 clr |= BIT(plat->cs); 186 187 clrsetbits_32(priv->regs + SPI_CTL_REG, clr, set); 188} 189 190static void bcmbca_hsspi_activate_cs(struct bcmbca_hsspi_priv *priv, 191 struct dm_spi_slave_plat *plat) 192{ 193 u32 val; 194 195 /* set the override bit */ 196 val = readl(priv->spim_ctrl); 197 val |= BIT(plat->cs + SPIM_CTRL_CS_OVERRIDE_SEL_SHIFT); 198 writel(val, priv->spim_ctrl); 199} 200 201static void bcmbca_hsspi_deactivate_cs(struct bcmbca_hsspi_priv *priv, 202 struct dm_spi_slave_plat *plat) 203{ 204 u32 val; 205 206 /* clear the cs override bit */ 207 val = readl(priv->spim_ctrl); 208 val &= ~BIT(plat->cs + SPIM_CTRL_CS_OVERRIDE_SEL_SHIFT); 209 writel(val, priv->spim_ctrl); 210} 211 212static int bcmbca_hsspi_xfer(struct udevice *dev, unsigned int bitlen, 213 const void *dout, void *din, unsigned long flags) 214{ 215 struct bcmbca_hsspi_priv *priv = dev_get_priv(dev->parent); 216 struct dm_spi_slave_plat *plat = dev_get_parent_plat(dev); 217 size_t data_bytes = bitlen / 8; 218 size_t step_size = HSSPI_FIFO_SIZE; 219 u16 opcode = 0; 220 u32 val = SPI_PFL_MODE_FILL_MASK; 221 const u8 *tx = dout; 222 u8 *rx = din; 223 u32 cs_act = 0; 224 225 if (flags & SPI_XFER_BEGIN) 226 bcmbca_hsspi_setup_clock(priv, plat); 227 228 /* fifo operation */ 229 if (tx && rx) 230 opcode = HSSPI_FIFO_OP_READ_WRITE; 231 else if (rx) 232 opcode = HSSPI_FIFO_OP_CODE_R; 233 else if (tx) 234 opcode = HSSPI_FIFO_OP_CODE_W; 235 236 if (opcode != HSSPI_FIFO_OP_CODE_R) 237 step_size -= HSSPI_FIFO_OP_SIZE; 238 239 /* dual mode */ 240 if ((opcode == HSSPI_FIFO_OP_CODE_R && (plat->mode & SPI_RX_DUAL)) || 241 (opcode == HSSPI_FIFO_OP_CODE_W && (plat->mode & SPI_TX_DUAL))) { 242 opcode |= HSSPI_FIFO_OP_MBIT_MASK; 243 244 /* profile mode */ 245 if (plat->mode & SPI_RX_DUAL) 246 val |= SPI_PFL_MODE_MDRDSZ_MASK; 247 if (plat->mode & SPI_TX_DUAL) 248 val |= SPI_PFL_MODE_MDWRSZ_MASK; 249 } 250 251 if (plat->mode & SPI_3WIRE) 252 val |= SPI_PFL_MODE_3WIRE_MASK; 253 writel(val, priv->regs + SPI_PFL_MODE_REG(plat->cs)); 254 255 /* transfer loop */ 256 while (data_bytes > 0) { 257 size_t curr_step = min(step_size, data_bytes); 258 int ret; 259 260 /* copy tx data */ 261 if (tx) { 262 memcpy_toio(priv->regs + HSSPI_FIFO_BASE + 263 HSSPI_FIFO_OP_SIZE, tx, curr_step); 264 tx += curr_step; 265 } 266 267 /* set fifo operation */ 268 writew(cpu_to_be16(opcode | (curr_step & HSSPI_FIFO_OP_BYTES_MASK)), 269 priv->regs + HSSPI_FIFO_OP_REG); 270 271 /* make sure we keep cs active until spi transfer is done */ 272 if (!cs_act) { 273 bcmbca_hsspi_activate_cs(priv, plat); 274 cs_act = 1; 275 } 276 277 /* issue the transfer */ 278 val = SPI_CMD_OP_START; 279 val |= (plat->cs << SPI_CMD_PFL_SHIFT) & 280 SPI_CMD_PFL_MASK; 281 val |= (plat->cs << SPI_CMD_SLAVE_SHIFT) & 282 SPI_CMD_SLAVE_MASK; 283 writel(val, priv->regs + SPI_CMD_REG); 284 285 /* wait for completion */ 286 ret = wait_for_bit_32(priv->regs + SPI_STAT_REG, 287 SPI_STAT_SRCBUSY_MASK, false, 288 1000, false); 289 if (ret) { 290 bcmbca_hsspi_deactivate_cs(priv, plat); 291 dev_err(dev, "interrupt timeout\n"); 292 return ret; 293 } 294 295 data_bytes -= curr_step; 296 if ((flags & SPI_XFER_END) && !data_bytes) 297 bcmbca_hsspi_deactivate_cs(priv, plat); 298 299 /* copy rx data */ 300 if (rx) { 301 memcpy_fromio(rx, priv->regs + HSSPI_FIFO_BASE, 302 curr_step); 303 rx += curr_step; 304 } 305 } 306 307 return 0; 308} 309 310static const struct dm_spi_ops bcmbca_hsspi_ops = { 311 .cs_info = bcmbca_hsspi_cs_info, 312 .set_mode = bcmbca_hsspi_set_mode, 313 .set_speed = bcmbca_hsspi_set_speed, 314 .xfer = bcmbca_hsspi_xfer, 315}; 316 317static const struct udevice_id bcmbca_hsspi_ids[] = { 318 { .compatible = "brcm,bcmbca-hsspi-v1.1", }, 319 { /* sentinel */ } 320}; 321 322static int bcmbca_hsspi_child_pre_probe(struct udevice *dev) 323{ 324 struct bcmbca_hsspi_priv *priv = dev_get_priv(dev->parent); 325 struct dm_spi_slave_plat *plat = dev_get_parent_plat(dev); 326 u32 val; 327 328 /* check cs */ 329 if (plat->cs >= priv->num_cs) { 330 dev_err(dev, "no cs %u\n", plat->cs); 331 return -EINVAL; 332 } 333 334 /* cs polarity */ 335 if (plat->mode & SPI_CS_HIGH) 336 priv->cs_pols |= BIT(plat->cs); 337 else 338 priv->cs_pols &= ~BIT(plat->cs); 339 340 /* set the polarity to spim cs register */ 341 val = readl(priv->spim_ctrl); 342 val &= ~BIT(plat->cs + SPIM_CTRL_CS_OVERRIDE_VAL_SHIFT); 343 if (priv->cs_pols & BIT(plat->cs)) 344 val |= BIT(plat->cs + SPIM_CTRL_CS_OVERRIDE_VAL_SHIFT); 345 writel(val, priv->spim_ctrl); 346 347 return 0; 348} 349 350static int bcmbca_hsspi_probe(struct udevice *dev) 351{ 352 struct bcmbca_hsspi_priv *priv = dev_get_priv(dev); 353 struct clk clk; 354 int ret; 355 356 priv->regs = dev_remap_addr_name(dev, "hsspi"); 357 if (!priv->regs) 358 return -EINVAL; 359 360 priv->spim_ctrl = dev_remap_addr_name(dev, "spim-ctrl"); 361 if (!priv->spim_ctrl) { 362 dev_err(dev, "misc spim ctrl register not defined in dts!\n"); 363 return -EINVAL; 364 } 365 366 priv->num_cs = dev_read_u32_default(dev, "num-cs", 8); 367 368 /* enable clock */ 369 ret = clk_get_by_name(dev, "hsspi", &clk); 370 if (ret < 0) 371 return ret; 372 373 ret = clk_enable(&clk); 374 if (ret < 0 && ret != -ENOSYS) 375 return ret; 376 377 /* get clock rate */ 378 ret = clk_get_by_name(dev, "pll", &clk); 379 if (ret < 0 && ret != -ENOSYS) 380 return ret; 381 382 priv->clk_rate = clk_get_rate(&clk); 383 384 /* initialize hardware */ 385 writel(0, priv->regs + SPI_IR_MASK_REG); 386 387 /* clear pending interrupts */ 388 writel(SPI_IR_CLEAR_ALL, priv->regs + SPI_IR_STAT_REG); 389 390 /* enable clk gate */ 391 setbits_32(priv->regs + SPI_CTL_REG, SPI_CTL_CLK_GATE_MASK); 392 393 /* read default cs polarities */ 394 priv->cs_pols = readl(priv->regs + SPI_CTL_REG) & 395 SPI_CTL_CS_POL_MASK; 396 397 dev_info(dev, "Broadcom BCMBCA HS SPI bus driver\n"); 398 return 0; 399} 400 401U_BOOT_DRIVER(bcmbca_hsspi) = { 402 .name = "bcmbca_hsspi", 403 .id = UCLASS_SPI, 404 .of_match = bcmbca_hsspi_ids, 405 .ops = &bcmbca_hsspi_ops, 406 .priv_auto = sizeof(struct bcmbca_hsspi_priv), 407 .child_pre_probe = bcmbca_hsspi_child_pre_probe, 408 .probe = bcmbca_hsspi_probe, 409}; 410