Searched refs:num_banks (Results 1 - 25 of 80) sorted by relevance

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/linux-master/drivers/nvmem/
H A Dnintendo-otp.c35 unsigned int num_banks; member in struct:nintendo_otp_devtype_data
40 .num_banks = 1,
45 .num_banks = 8,
101 config.size = data->num_banks * BANK_SIZE;
/linux-master/drivers/hwspinlock/
H A Dsun6i_hwspinlock.c96 u32 num_banks; local
146 num_banks = readl(io_base + SPINLOCK_SYSSTATUS_REG) >> 28;
147 switch (num_banks) {
149 priv->nlocks = 1 << (4 + num_banks);
153 dev_err(&pdev->dev, "unsupported hwspinlock setup (%d)\n", num_banks);
/linux-master/drivers/crypto/intel/qat/qat_common/
H A Dadf_isr.c25 u32 msix_num_entries = hw_data->num_banks + 1;
183 int clust_irq = hw_data->num_banks;
187 for (i = 0; i < hw_data->num_banks; i++) {
208 int clust_irq = hw_data->num_banks;
214 for (i = 0; i < hw_data->num_banks; i++) {
238 cpu = ((accel_dev->accel_id * hw_data->num_banks) +
278 msix_num_entries += hw_data->num_banks;
302 for (i = 0; i < hw_data->num_banks; i++)
315 for (i = 0; i < hw_data->num_banks; i++) {
H A Dadf_transport.c480 u32 num_banks = 0; local
488 num_banks = GET_MAX_BANKS(accel_dev);
489 size = num_banks * sizeof(struct adf_etr_bank_data);
505 for (i = 0; i < num_banks; i++) {
548 u32 i, num_banks = GET_MAX_BANKS(accel_dev); local
550 for (i = 0; i < num_banks; i++)
/linux-master/drivers/gpu/drm/amd/amdgpu/
H A Damdgpu_socbb.h68 uint32_t num_banks; member in struct:gpu_info_soc_bounding_box_v1_0
/linux-master/drivers/mtd/nand/raw/ingenic/
H A Dingenic_nand_drv.c47 unsigned int num_banks; member in struct:ingenic_nfc
49 struct ingenic_nand_cs cs[] __counted_by(num_banks);
446 if (num_chips > nfc->num_banks) {
448 num_chips, nfc->num_banks);
469 unsigned int num_banks; local
473 num_banks = jz4780_nemc_num_banks(dev);
474 if (num_banks == 0) {
479 nfc = devm_kzalloc(dev, struct_size(nfc, cs, num_banks), GFP_KERNEL);
496 nfc->num_banks = num_banks;
[all...]
/linux-master/drivers/gpio/
H A Dgpio-brcmstb.c362 int num_banks = local
365 if (res_num_banks != num_banks) {
367 res_num_banks, num_banks);
598 int num_banks = 0; local
652 num_banks);
653 num_banks++;
665 bank->id = num_banks;
724 num_banks++;
H A Dgpio-stmpe.c183 int num_banks = DIV_ROUND_UP(stmpe->num_gpios, 8); local
214 for (j = 0; j < num_banks; j++) {
384 int num_banks = DIV_ROUND_UP(stmpe->num_gpios, 8); local
402 ret = stmpe_block_read(stmpe, statmsbreg, num_banks, status);
406 for (i = 0; i < num_banks; i++) {
408 num_banks - i - 1;
H A Dgpio-tegra186.c104 unsigned int num_banks; member in struct:tegra_gpio
798 if (gpio->num_irq > gpio->num_banks) {
799 if (gpio->num_irq % gpio->num_banks != 0)
803 if (gpio->num_irq < gpio->num_banks)
806 gpio->num_irqs_per_bank = gpio->num_irq / gpio->num_banks;
815 gpio->num_irq, gpio->num_banks);
838 if (gpio->soc->ports[i].bank > gpio->num_banks)
839 gpio->num_banks = gpio->soc->ports[i].bank;
841 gpio->num_banks++;
950 irq->parents = devm_kcalloc(&pdev->dev, gpio->num_banks,
[all...]
/linux-master/drivers/gpu/drm/amd/display/dc/dml/dcn10/
H A Ddcn10_fpu.c119 .num_banks = 8,
/linux-master/drivers/crypto/intel/qat/qat_c3xxxvf/
H A Dadf_c3xxxvf_hw_data.c65 hw_data->num_banks = ADF_C3XXXIOV_ETR_MAX_BANKS;
/linux-master/drivers/crypto/intel/qat/qat_c62xvf/
H A Dadf_c62xvf_hw_data.c65 hw_data->num_banks = ADF_C62XIOV_ETR_MAX_BANKS;
/linux-master/drivers/crypto/intel/qat/qat_dh895xccvf/
H A Dadf_dh895xccvf_hw_data.c65 hw_data->num_banks = ADF_DH895XCCIOV_ETR_MAX_BANKS;
/linux-master/drivers/leds/
H A Dleds-lm3697.c79 * @num_banks: Number of control banks
90 int num_banks; member in struct:lm3697
92 struct lm3697_led leds[] __counted_by(num_banks);
193 for (i = 0; i < priv->num_banks; i++) {
324 led->num_banks = count;
/linux-master/drivers/soc/qcom/
H A Docmem.c303 int i, j, ret, num_banks; local
371 num_banks = ocmem->num_ports / 2;
372 region_size = ocmem->config->macro_size * num_banks;
388 if (WARN_ON(num_banks > ARRAY_SIZE(region->macro_state))) {
394 region->num_macros = num_banks;
H A Dllcc-qcom.c1004 max_cap_cacheline = max_cap_cacheline / drv_data->num_banks;
1205 u32 num_banks; local
1243 ret = regmap_read(regmap, cfg->reg_offset[LLCC_COMMON_STATUS0], &num_banks);
1247 num_banks &= LLCC_LB_CNT_MASK;
1248 num_banks >>= LLCC_LB_CNT_SHIFT;
1249 drv_data->num_banks = num_banks;
1251 drv_data->regmaps = devm_kcalloc(dev, num_banks, sizeof(*drv_data->regmaps), GFP_KERNEL);
1260 for (i = 1; i < num_banks; i++) {
/linux-master/drivers/thermal/mediatek/
H A Dauxadc_thermal.c312 s32 num_banks; member in struct:mtk_thermal_data
486 .num_banks = MT8173_NUM_ZONES,
526 .num_banks = 1,
557 .num_banks = MT8365_NUM_BANKS,
591 .num_banks = 1,
616 .num_banks = MT7622_NUM_ZONES,
651 .num_banks = MT8183_NUM_ZONES,
676 .num_banks = MT7986_NUM_ZONES,
854 for (i = 0; i < mt->conf->num_banks; i++) {
1284 for (i = 0; i < mt->conf->num_banks;
[all...]
/linux-master/drivers/pinctrl/meson/
H A Dpinctrl-meson.h119 unsigned int num_banks; member in struct:meson_pinctrl_data
/linux-master/include/linux/soc/qcom/
H A Dllcc-qcom.h124 * @num_banks: Number of llcc banks
137 u32 num_banks; member in struct:llcc_drv_data
/linux-master/drivers/memory/
H A Djedec_ddr.h137 u32 num_banks; member in struct:lpddr2_addressing
/linux-master/drivers/crypto/intel/qat/qat_c62x/
H A Dadf_c62x_hw_data.c121 hw_data->num_banks = ADF_C62X_ETR_MAX_BANKS;
/linux-master/drivers/crypto/intel/qat/qat_c3xxx/
H A Dadf_c3xxx_hw_data.c119 hw_data->num_banks = ADF_C3XXX_ETR_MAX_BANKS;
/linux-master/drivers/gpu/drm/amd/display/dc/core/
H A Ddc_debug.c132 "plane_state->tiling_info.gfx8.num_banks = %d;\n"
143 plane_state->tiling_info.gfx8.num_banks,
224 "plane_info->tiling_info.gfx8.num_banks = %d;\n"
235 update->plane_info->tiling_info.gfx8.num_banks,
/linux-master/drivers/edac/
H A Dqcom_edac.c297 for (i = 0; i < drv->num_banks; i++) {
351 llcc_driv_data->num_banks, 1,
/linux-master/drivers/remoteproc/
H A Dxlnx_r5_remoteproc.c554 int i, num_banks, ret; local
564 num_banks = r5_core->tcm_bank_count;
571 for (i = 0; i < num_banks; i++) {
625 int i, num_banks, ret; local
637 num_banks = r5_core->tcm_bank_count;
646 for (i = 0; i < num_banks; i++) {

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