1// SPDX-License-Identifier: GPL-2.0
2/*
3 * Ingenic JZ47xx NAND driver
4 *
5 * Copyright (c) 2015 Imagination Technologies
6 * Author: Alex Smith <alex.smith@imgtec.com>
7 */
8
9#include <linux/delay.h>
10#include <linux/init.h>
11#include <linux/io.h>
12#include <linux/list.h>
13#include <linux/module.h>
14#include <linux/of.h>
15#include <linux/of_address.h>
16#include <linux/gpio/consumer.h>
17#include <linux/platform_device.h>
18#include <linux/slab.h>
19#include <linux/mtd/mtd.h>
20#include <linux/mtd/rawnand.h>
21#include <linux/mtd/partitions.h>
22
23#include <linux/jz4780-nemc.h>
24
25#include "ingenic_ecc.h"
26
27#define DRV_NAME	"ingenic-nand"
28
29struct jz_soc_info {
30	unsigned long data_offset;
31	unsigned long addr_offset;
32	unsigned long cmd_offset;
33	const struct mtd_ooblayout_ops *oob_layout;
34	bool oob_first;
35};
36
37struct ingenic_nand_cs {
38	unsigned int bank;
39	void __iomem *base;
40};
41
42struct ingenic_nfc {
43	struct device *dev;
44	struct ingenic_ecc *ecc;
45	const struct jz_soc_info *soc_info;
46	struct nand_controller controller;
47	unsigned int num_banks;
48	struct list_head chips;
49	struct ingenic_nand_cs cs[] __counted_by(num_banks);
50};
51
52struct ingenic_nand {
53	struct nand_chip chip;
54	struct list_head chip_list;
55
56	struct gpio_desc *busy_gpio;
57	struct gpio_desc *wp_gpio;
58	unsigned int reading: 1;
59};
60
61static inline struct ingenic_nand *to_ingenic_nand(struct mtd_info *mtd)
62{
63	return container_of(mtd_to_nand(mtd), struct ingenic_nand, chip);
64}
65
66static inline struct ingenic_nfc *to_ingenic_nfc(struct nand_controller *ctrl)
67{
68	return container_of(ctrl, struct ingenic_nfc, controller);
69}
70
71static int qi_lb60_ooblayout_ecc(struct mtd_info *mtd, int section,
72				 struct mtd_oob_region *oobregion)
73{
74	struct nand_chip *chip = mtd_to_nand(mtd);
75	struct nand_ecc_ctrl *ecc = &chip->ecc;
76
77	if (section || !ecc->total)
78		return -ERANGE;
79
80	oobregion->length = ecc->total;
81	oobregion->offset = 12;
82
83	return 0;
84}
85
86static int qi_lb60_ooblayout_free(struct mtd_info *mtd, int section,
87				  struct mtd_oob_region *oobregion)
88{
89	struct nand_chip *chip = mtd_to_nand(mtd);
90	struct nand_ecc_ctrl *ecc = &chip->ecc;
91
92	if (section)
93		return -ERANGE;
94
95	oobregion->length = mtd->oobsize - ecc->total - 12;
96	oobregion->offset = 12 + ecc->total;
97
98	return 0;
99}
100
101static const struct mtd_ooblayout_ops qi_lb60_ooblayout_ops = {
102	.ecc = qi_lb60_ooblayout_ecc,
103	.free = qi_lb60_ooblayout_free,
104};
105
106static int jz4725b_ooblayout_ecc(struct mtd_info *mtd, int section,
107				 struct mtd_oob_region *oobregion)
108{
109	struct nand_chip *chip = mtd_to_nand(mtd);
110	struct nand_ecc_ctrl *ecc = &chip->ecc;
111
112	if (section || !ecc->total)
113		return -ERANGE;
114
115	oobregion->length = ecc->total;
116	oobregion->offset = 3;
117
118	return 0;
119}
120
121static int jz4725b_ooblayout_free(struct mtd_info *mtd, int section,
122				  struct mtd_oob_region *oobregion)
123{
124	struct nand_chip *chip = mtd_to_nand(mtd);
125	struct nand_ecc_ctrl *ecc = &chip->ecc;
126
127	if (section)
128		return -ERANGE;
129
130	oobregion->length = mtd->oobsize - ecc->total - 3;
131	oobregion->offset = 3 + ecc->total;
132
133	return 0;
134}
135
136static const struct mtd_ooblayout_ops jz4725b_ooblayout_ops = {
137	.ecc = jz4725b_ooblayout_ecc,
138	.free = jz4725b_ooblayout_free,
139};
140
141static void ingenic_nand_ecc_hwctl(struct nand_chip *chip, int mode)
142{
143	struct ingenic_nand *nand = to_ingenic_nand(nand_to_mtd(chip));
144
145	nand->reading = (mode == NAND_ECC_READ);
146}
147
148static int ingenic_nand_ecc_calculate(struct nand_chip *chip, const u8 *dat,
149				      u8 *ecc_code)
150{
151	struct ingenic_nand *nand = to_ingenic_nand(nand_to_mtd(chip));
152	struct ingenic_nfc *nfc = to_ingenic_nfc(nand->chip.controller);
153	struct ingenic_ecc_params params;
154
155	/*
156	 * Don't need to generate the ECC when reading, the ECC engine does it
157	 * for us as part of decoding/correction.
158	 */
159	if (nand->reading)
160		return 0;
161
162	params.size = nand->chip.ecc.size;
163	params.bytes = nand->chip.ecc.bytes;
164	params.strength = nand->chip.ecc.strength;
165
166	return ingenic_ecc_calculate(nfc->ecc, &params, dat, ecc_code);
167}
168
169static int ingenic_nand_ecc_correct(struct nand_chip *chip, u8 *dat,
170				    u8 *read_ecc, u8 *calc_ecc)
171{
172	struct ingenic_nand *nand = to_ingenic_nand(nand_to_mtd(chip));
173	struct ingenic_nfc *nfc = to_ingenic_nfc(nand->chip.controller);
174	struct ingenic_ecc_params params;
175
176	params.size = nand->chip.ecc.size;
177	params.bytes = nand->chip.ecc.bytes;
178	params.strength = nand->chip.ecc.strength;
179
180	return ingenic_ecc_correct(nfc->ecc, &params, dat, read_ecc);
181}
182
183static int ingenic_nand_attach_chip(struct nand_chip *chip)
184{
185	struct mtd_info *mtd = nand_to_mtd(chip);
186	struct ingenic_nfc *nfc = to_ingenic_nfc(chip->controller);
187	int eccbytes;
188
189	if (chip->ecc.strength == 4) {
190		/* JZ4740 uses 9 bytes of ECC to correct maximum 4 errors */
191		chip->ecc.bytes = 9;
192	} else {
193		chip->ecc.bytes = fls((1 + 8) * chip->ecc.size)	*
194				  (chip->ecc.strength / 8);
195	}
196
197	switch (chip->ecc.engine_type) {
198	case NAND_ECC_ENGINE_TYPE_ON_HOST:
199		if (!nfc->ecc) {
200			dev_err(nfc->dev, "HW ECC selected, but ECC controller not found\n");
201			return -ENODEV;
202		}
203
204		chip->ecc.hwctl = ingenic_nand_ecc_hwctl;
205		chip->ecc.calculate = ingenic_nand_ecc_calculate;
206		chip->ecc.correct = ingenic_nand_ecc_correct;
207		fallthrough;
208	case NAND_ECC_ENGINE_TYPE_SOFT:
209		dev_info(nfc->dev, "using %s (strength %d, size %d, bytes %d)\n",
210			 (nfc->ecc) ? "hardware ECC" : "software ECC",
211			 chip->ecc.strength, chip->ecc.size, chip->ecc.bytes);
212		break;
213	case NAND_ECC_ENGINE_TYPE_NONE:
214		dev_info(nfc->dev, "not using ECC\n");
215		break;
216	default:
217		dev_err(nfc->dev, "ECC mode %d not supported\n",
218			chip->ecc.engine_type);
219		return -EINVAL;
220	}
221
222	/* The NAND core will generate the ECC layout for SW ECC */
223	if (chip->ecc.engine_type != NAND_ECC_ENGINE_TYPE_ON_HOST)
224		return 0;
225
226	/* Generate ECC layout. ECC codes are right aligned in the OOB area. */
227	eccbytes = mtd->writesize / chip->ecc.size * chip->ecc.bytes;
228
229	if (eccbytes > mtd->oobsize - 2) {
230		dev_err(nfc->dev,
231			"invalid ECC config: required %d ECC bytes, but only %d are available",
232			eccbytes, mtd->oobsize - 2);
233		return -EINVAL;
234	}
235
236	/*
237	 * The generic layout for BBT markers will most likely overlap with our
238	 * ECC bytes in the OOB, so move the BBT markers outside the OOB area.
239	 */
240	if (chip->bbt_options & NAND_BBT_USE_FLASH)
241		chip->bbt_options |= NAND_BBT_NO_OOB;
242
243	if (nfc->soc_info->oob_first)
244		chip->ecc.read_page = nand_read_page_hwecc_oob_first;
245
246	/* For legacy reasons we use a different layout on the qi,lb60 board. */
247	if (of_machine_is_compatible("qi,lb60"))
248		mtd_set_ooblayout(mtd, &qi_lb60_ooblayout_ops);
249	else if (nfc->soc_info->oob_layout)
250		mtd_set_ooblayout(mtd, nfc->soc_info->oob_layout);
251	else
252		mtd_set_ooblayout(mtd, nand_get_large_page_ooblayout());
253
254	return 0;
255}
256
257static int ingenic_nand_exec_instr(struct nand_chip *chip,
258				   struct ingenic_nand_cs *cs,
259				   const struct nand_op_instr *instr)
260{
261	struct ingenic_nand *nand = to_ingenic_nand(nand_to_mtd(chip));
262	struct ingenic_nfc *nfc = to_ingenic_nfc(chip->controller);
263	unsigned int i;
264
265	switch (instr->type) {
266	case NAND_OP_CMD_INSTR:
267		writeb(instr->ctx.cmd.opcode,
268		       cs->base + nfc->soc_info->cmd_offset);
269		return 0;
270	case NAND_OP_ADDR_INSTR:
271		for (i = 0; i < instr->ctx.addr.naddrs; i++)
272			writeb(instr->ctx.addr.addrs[i],
273			       cs->base + nfc->soc_info->addr_offset);
274		return 0;
275	case NAND_OP_DATA_IN_INSTR:
276		if (instr->ctx.data.force_8bit ||
277		    !(chip->options & NAND_BUSWIDTH_16))
278			ioread8_rep(cs->base + nfc->soc_info->data_offset,
279				    instr->ctx.data.buf.in,
280				    instr->ctx.data.len);
281		else
282			ioread16_rep(cs->base + nfc->soc_info->data_offset,
283				     instr->ctx.data.buf.in,
284				     instr->ctx.data.len);
285		return 0;
286	case NAND_OP_DATA_OUT_INSTR:
287		if (instr->ctx.data.force_8bit ||
288		    !(chip->options & NAND_BUSWIDTH_16))
289			iowrite8_rep(cs->base + nfc->soc_info->data_offset,
290				     instr->ctx.data.buf.out,
291				     instr->ctx.data.len);
292		else
293			iowrite16_rep(cs->base + nfc->soc_info->data_offset,
294				      instr->ctx.data.buf.out,
295				      instr->ctx.data.len);
296		return 0;
297	case NAND_OP_WAITRDY_INSTR:
298		if (!nand->busy_gpio)
299			return nand_soft_waitrdy(chip,
300						 instr->ctx.waitrdy.timeout_ms);
301
302		return nand_gpio_waitrdy(chip, nand->busy_gpio,
303					 instr->ctx.waitrdy.timeout_ms);
304	default:
305		break;
306	}
307
308	return -EINVAL;
309}
310
311static int ingenic_nand_exec_op(struct nand_chip *chip,
312				const struct nand_operation *op,
313				bool check_only)
314{
315	struct ingenic_nand *nand = to_ingenic_nand(nand_to_mtd(chip));
316	struct ingenic_nfc *nfc = to_ingenic_nfc(nand->chip.controller);
317	struct ingenic_nand_cs *cs;
318	unsigned int i;
319	int ret = 0;
320
321	if (check_only)
322		return 0;
323
324	cs = &nfc->cs[op->cs];
325	jz4780_nemc_assert(nfc->dev, cs->bank, true);
326	for (i = 0; i < op->ninstrs; i++) {
327		ret = ingenic_nand_exec_instr(chip, cs, &op->instrs[i]);
328		if (ret)
329			break;
330
331		if (op->instrs[i].delay_ns)
332			ndelay(op->instrs[i].delay_ns);
333	}
334	jz4780_nemc_assert(nfc->dev, cs->bank, false);
335
336	return ret;
337}
338
339static const struct nand_controller_ops ingenic_nand_controller_ops = {
340	.attach_chip = ingenic_nand_attach_chip,
341	.exec_op = ingenic_nand_exec_op,
342};
343
344static int ingenic_nand_init_chip(struct platform_device *pdev,
345				  struct ingenic_nfc *nfc,
346				  struct device_node *np,
347				  unsigned int chipnr)
348{
349	struct device *dev = &pdev->dev;
350	struct ingenic_nand *nand;
351	struct ingenic_nand_cs *cs;
352	struct nand_chip *chip;
353	struct mtd_info *mtd;
354	const __be32 *reg;
355	int ret = 0;
356
357	cs = &nfc->cs[chipnr];
358
359	reg = of_get_property(np, "reg", NULL);
360	if (!reg)
361		return -EINVAL;
362
363	cs->bank = be32_to_cpu(*reg);
364
365	jz4780_nemc_set_type(nfc->dev, cs->bank, JZ4780_NEMC_BANK_NAND);
366
367	cs->base = devm_platform_ioremap_resource(pdev, chipnr);
368	if (IS_ERR(cs->base))
369		return PTR_ERR(cs->base);
370
371	nand = devm_kzalloc(dev, sizeof(*nand), GFP_KERNEL);
372	if (!nand)
373		return -ENOMEM;
374
375	nand->busy_gpio = devm_gpiod_get_optional(dev, "rb", GPIOD_IN);
376
377	if (IS_ERR(nand->busy_gpio)) {
378		ret = PTR_ERR(nand->busy_gpio);
379		dev_err(dev, "failed to request busy GPIO: %d\n", ret);
380		return ret;
381	}
382
383	nand->wp_gpio = devm_gpiod_get_optional(dev, "wp", GPIOD_OUT_LOW);
384
385	if (IS_ERR(nand->wp_gpio)) {
386		ret = PTR_ERR(nand->wp_gpio);
387		dev_err(dev, "failed to request WP GPIO: %d\n", ret);
388		return ret;
389	}
390
391	chip = &nand->chip;
392	mtd = nand_to_mtd(chip);
393	mtd->name = devm_kasprintf(dev, GFP_KERNEL, "%s.%d", dev_name(dev),
394				   cs->bank);
395	if (!mtd->name)
396		return -ENOMEM;
397	mtd->dev.parent = dev;
398
399	chip->options = NAND_NO_SUBPAGE_WRITE;
400	chip->ecc.engine_type = NAND_ECC_ENGINE_TYPE_ON_HOST;
401	chip->controller = &nfc->controller;
402	nand_set_flash_node(chip, np);
403
404	chip->controller->ops = &ingenic_nand_controller_ops;
405	ret = nand_scan(chip, 1);
406	if (ret)
407		return ret;
408
409	ret = mtd_device_register(mtd, NULL, 0);
410	if (ret) {
411		nand_cleanup(chip);
412		return ret;
413	}
414
415	list_add_tail(&nand->chip_list, &nfc->chips);
416
417	return 0;
418}
419
420static void ingenic_nand_cleanup_chips(struct ingenic_nfc *nfc)
421{
422	struct ingenic_nand *ingenic_chip;
423	struct nand_chip *chip;
424	int ret;
425
426	while (!list_empty(&nfc->chips)) {
427		ingenic_chip = list_first_entry(&nfc->chips,
428						struct ingenic_nand, chip_list);
429		chip = &ingenic_chip->chip;
430		ret = mtd_device_unregister(nand_to_mtd(chip));
431		WARN_ON(ret);
432		nand_cleanup(chip);
433		list_del(&ingenic_chip->chip_list);
434	}
435}
436
437static int ingenic_nand_init_chips(struct ingenic_nfc *nfc,
438				   struct platform_device *pdev)
439{
440	struct device *dev = &pdev->dev;
441	struct device_node *np;
442	int i = 0;
443	int ret;
444	int num_chips = of_get_child_count(dev->of_node);
445
446	if (num_chips > nfc->num_banks) {
447		dev_err(dev, "found %d chips but only %d banks\n",
448			num_chips, nfc->num_banks);
449		return -EINVAL;
450	}
451
452	for_each_child_of_node(dev->of_node, np) {
453		ret = ingenic_nand_init_chip(pdev, nfc, np, i);
454		if (ret) {
455			ingenic_nand_cleanup_chips(nfc);
456			of_node_put(np);
457			return ret;
458		}
459
460		i++;
461	}
462
463	return 0;
464}
465
466static int ingenic_nand_probe(struct platform_device *pdev)
467{
468	struct device *dev = &pdev->dev;
469	unsigned int num_banks;
470	struct ingenic_nfc *nfc;
471	int ret;
472
473	num_banks = jz4780_nemc_num_banks(dev);
474	if (num_banks == 0) {
475		dev_err(dev, "no banks found\n");
476		return -ENODEV;
477	}
478
479	nfc = devm_kzalloc(dev, struct_size(nfc, cs, num_banks), GFP_KERNEL);
480	if (!nfc)
481		return -ENOMEM;
482
483	nfc->soc_info = device_get_match_data(dev);
484	if (!nfc->soc_info)
485		return -EINVAL;
486
487	/*
488	 * Check for ECC HW before we call nand_scan_ident, to prevent us from
489	 * having to call it again if the ECC driver returns -EPROBE_DEFER.
490	 */
491	nfc->ecc = of_ingenic_ecc_get(dev->of_node);
492	if (IS_ERR(nfc->ecc))
493		return PTR_ERR(nfc->ecc);
494
495	nfc->dev = dev;
496	nfc->num_banks = num_banks;
497
498	nand_controller_init(&nfc->controller);
499	INIT_LIST_HEAD(&nfc->chips);
500
501	ret = ingenic_nand_init_chips(nfc, pdev);
502	if (ret) {
503		if (nfc->ecc)
504			ingenic_ecc_release(nfc->ecc);
505		return ret;
506	}
507
508	platform_set_drvdata(pdev, nfc);
509	return 0;
510}
511
512static void ingenic_nand_remove(struct platform_device *pdev)
513{
514	struct ingenic_nfc *nfc = platform_get_drvdata(pdev);
515
516	if (nfc->ecc)
517		ingenic_ecc_release(nfc->ecc);
518
519	ingenic_nand_cleanup_chips(nfc);
520}
521
522static const struct jz_soc_info jz4740_soc_info = {
523	.data_offset = 0x00000000,
524	.cmd_offset = 0x00008000,
525	.addr_offset = 0x00010000,
526	.oob_first = true,
527};
528
529static const struct jz_soc_info jz4725b_soc_info = {
530	.data_offset = 0x00000000,
531	.cmd_offset = 0x00008000,
532	.addr_offset = 0x00010000,
533	.oob_layout = &jz4725b_ooblayout_ops,
534};
535
536static const struct jz_soc_info jz4780_soc_info = {
537	.data_offset = 0x00000000,
538	.cmd_offset = 0x00400000,
539	.addr_offset = 0x00800000,
540};
541
542static const struct of_device_id ingenic_nand_dt_match[] = {
543	{ .compatible = "ingenic,jz4740-nand", .data = &jz4740_soc_info },
544	{ .compatible = "ingenic,jz4725b-nand", .data = &jz4725b_soc_info },
545	{ .compatible = "ingenic,jz4780-nand", .data = &jz4780_soc_info },
546	{},
547};
548MODULE_DEVICE_TABLE(of, ingenic_nand_dt_match);
549
550static struct platform_driver ingenic_nand_driver = {
551	.probe		= ingenic_nand_probe,
552	.remove_new	= ingenic_nand_remove,
553	.driver	= {
554		.name	= DRV_NAME,
555		.of_match_table = ingenic_nand_dt_match,
556	},
557};
558module_platform_driver(ingenic_nand_driver);
559
560MODULE_AUTHOR("Alex Smith <alex@alex-smith.me.uk>");
561MODULE_AUTHOR("Harvey Hunt <harveyhuntnexus@gmail.com>");
562MODULE_DESCRIPTION("Ingenic JZ47xx NAND driver");
563MODULE_LICENSE("GPL v2");
564