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827eb27e |
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05-Sep-2022 |
Andy Shevchenko <andriy.shevchenko@linux.intel.com> |
pinctrl: meson: Switch to use fwnode instead of of_node GPIO library now accepts fwnode as a firmware node, so switch the driver to use it. Signed-off-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com> Reviewed-by: Neil Armstrong <narmstrong@baylibre.com> Link: https://lore.kernel.org/r/20220905180034.73132-1-andriy.shevchenko@linux.intel.com Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
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2b2dce80 |
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01-Apr-2022 |
Andy Shevchenko <andriy.shevchenko@linux.intel.com> |
pinctrl: meson: Rename REG_* to MESON_REG_* Currently compilation test fails on x86 due to name collision. The usual way to fix that is to move both conflicting parts to their own namespaces. Rename REG_* to MESON_REG_* as a prerequisite for enabling COMPILE_TEST. Signed-off-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com> Tested-by: Marek Szyprowski <m.szyprowski@samsung.com> Reviewed-by: Neil Armstrong <narmstrong@baylibre.com>
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9c65441e |
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26-Oct-2020 |
Kevin Hilman <khilman@baylibre.com> |
pinctrl/meson: enable building as modules Enable pinctrl drivers for 64-bit Amlogic SoCs to be built as modules. The default is still built-in, this only adds the option of building as modules. Signed-off-by: Kevin Hilman <khilman@baylibre.com> Link: https://lore.kernel.org/r/20201026183025.31768-1-khilman@baylibre.com Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
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dabad1ff |
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15-Nov-2019 |
Qianggui Song <qianggui.song@amlogic.com> |
pinctrl: meson: add pinctrl driver support for Meson-A1 SoC Meson A1 SoC share the same register layout of pinmux with previous Meson-G12A, however there is difference for gpio and pin config register in A1. The main difference is that registers before A1 are grouped by function while those of A1 are by bank. The new register layout is as below: /* first bank */ /* addr */ - P_PADCTRL_GPIOP_I base + 0x00 << 2 - P_PADCTRL_GPIOP_O base + 0x01 << 2 - P_PADCTRL_GPIOP_OEN base + 0x02 << 2 - P_PADCTRL_GPIOP_PULL_EN base + 0x03 << 2 - P_PADCTRL_GPIOP_PULL_UP base + 0x04 << 2 - P_PADCTRL_GPIOP_DS base + 0x05 << 2 /* second bank */ - P_PADCTRL_GPIOB_I base + 0x10 << 2 - P_PADCTRL_GPIOB_O base + 0x11 << 2 - P_PADCTRL_GPIOB_OEN base + 0x12 << 2 - P_PADCTRL_GPIOB_PULL_EN base + 0x13 << 2 - P_PADCTRL_GPIOB_PULL_UP base + 0x14 << 2 - P_PADCTRL_GPIOB_DS base + 0x15 << 2 Each bank contains at least 6 registers to be configured, if one bank has more than 16 gpios, an extra P_PADCTRL_GPIO[X]_DS_EXT is included. Between two adjacent P_PADCTRL_GPIO[X]_I, there is an offset 0x10, that is to say, for third bank, the offsets will be 0x20,0x21,0x22,0x23,0x24 ,0x25 according to above register layout. For previous chips, registers are grouped according to their functions while registers of A1 are according to bank.Also note that there is no AO bank any more in A1. Current Meson pinctrl driver can cover such change by using base address of GPIO as that of drive-strength. While simply giving reg_ds = reg_pullen make wrong value to reg_ds for Socs that do not support drive-strength like AXG.To make things simple, add an extra dt parser function for a1 and remain the old dt parser function for only reg parsing. Signed-off-by: Qianggui Song <qianggui.song@amlogic.com> Link: https://lore.kernel.org/r/1573819429-6937-3-git-send-email-qianggui.song@amlogic.com Reviewed-by: Neil Armstrong <narmstrong@baylibre.com> Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
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fd422964 |
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15-Nov-2019 |
Qianggui Song <qianggui.song@amlogic.com> |
pinctrl: meson: add a new callback for SoCs fixup In meson_pinctrl_parse_dt, it contains two parts: reg parsing and SoC relative fixup for AO. Several fixups in the same code make it hard to maintain, so move all fixups to each SoC's callback and make meson_pinctrl_parse_dt just do the reg parsing, separate these two parts.Overview of all current Meson SoCs fixup is as below: +------+--------------------------------------+--------------------------+ | | | | | SoC | EE domain | AO domain | +------+--------------------------------------+--------------------------+ |m8 | parse regs: | parse regs: | |m8b | gpio,mux,pull,pull-enable(skip ds) | gpio,mux,pull(skip ds)| |gxl | fixup: | fixup: | |gxbb | no | pull-enable = pull; | |axg | | | +------+--------------------------------------+--------------------------+ |g12a | parse regs: | parse regs: | |sm1 | gpio,mux,pull,pull-enable,ds | gpio,mux,ds | | | fixup: | fixup: | | | no | pull = gpio; | | | | pull-enable = gpio; | +------+--------------------------------------+--------------------------+ |a1 or | parse regs: | |later | gpio/mux (without ao domain) | |SoCs | fixup: | | | pull = gpio; pull-enable = gpio; ds = gpio; | +------+-----------------------------------------------------------------+ Since m8-axg share the same ao fixup, make a common function meson8_aobus_parse_dt_extra to do the job. Signed-off-by: Qianggui Song <qianggui.song@amlogic.com> Link: https://lore.kernel.org/r/1573819429-6937-2-git-send-email-qianggui.song@amlogic.com Reviewed-by: Neil Armstrong <narmstrong@baylibre.com> Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
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3c910ecb |
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01-Jun-2019 |
Thomas Gleixner <tglx@linutronix.de> |
treewide: Replace GPLv2 boilerplate/reference with SPDX - rule 446 Based on 1 normalized pattern(s): this program is free software you can redistribute it and or modify it under the terms of the gnu general public license version 2 as published by the free software foundation you should have received a copy of the gnu general public license along with this program if not see http www gnu org licenses extracted by the scancode license scanner the SPDX license identifier GPL-2.0-only has been chosen to replace the boilerplate/reference in 30 file(s). Signed-off-by: Thomas Gleixner <tglx@linutronix.de> Reviewed-by: Allison Randal <allison@lohutok.net> Cc: linux-spdx@vger.kernel.org Link: https://lkml.kernel.org/r/20190531190115.962665879@linutronix.de Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
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e0cdd3a0 |
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20-May-2019 |
Neil Armstrong <narmstrong@baylibre.com> |
pinctrl: meson: update with SPDX Licence identifier Signed-off-by: Neil Armstrong <narmstrong@baylibre.com> Reviewed-by: Martin Blumenstingl <martin.blumenstingl@googlemail.com> Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
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6ea3e3bb |
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14-May-2019 |
Guillaume La Roque <glaroque@baylibre.com> |
pinctrl: meson: add support of drive-strength-microamp drive-strength-microamp is a new feature needed for G12A SoC. the default DS setting after boot is usually 500uA and it is not enough for many functions. We need to be able to set the drive strength to reliably enable things like MMC, I2C, etc ... Signed-off-by: Guillaume La Roque <glaroque@baylibre.com> Reviewed-by: Martin Blumenstingl <martin.blumenstingl@googlemail.com> Tested-by: Martin Blumenstingl <martin.blumenstingl@googlemail.com> Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
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64856974 |
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17-Jan-2019 |
Jerome Brunet <jbrunet@baylibre.com> |
pinctrl: meson: add optional region for drive strength On the G12a, there is a new 'region' to handle the drive-strength. This is optional since the older do not have this. Fixes: 29ae0952e85f ("pinctrl: meson-g12a: add pinctrl driver support") Signed-off-by: Jerome Brunet <jbrunet@baylibre.com> Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
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1c5fb66a |
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13-Sep-2018 |
Linus Walleij <linus.walleij@linaro.org> |
pinctrl: Include <linux/gpio/driver.h> nothing else These drivers are GPIO drivers, and the do not need to use the legacy header in <linux/gpio.h>, go directly for <linux/gpio/driver.h> instead. Replace any use of GPIOF_* with 0/1, these flags are for consumers, not drivers. Get rid of a few gpio_to_irq() users that was littering around the place, use local callbacks or avoid using it at all. Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
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0fabe43f |
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20-Nov-2017 |
Xingyu Chen <xingyu.chen@amlogic.com> |
pinctrl: meson-axg: Introduce a pinctrl pinmux ops for Meson-AXG SoC The pin controller has been updated in the Amlogic Meson AXG series, which use continuous 4-bit register to select function for each pin. In order to support this, a new pinmux operations "meson_axg_pmx_ops" has been added. Reviewed-by: Neil Armstrong <narmstrong@baylibre.com> Signed-off-by: Xingyu Chen <xingyu.chen@amlogic.com> Signed-off-by: Yixun Lan <yixun.lan@amlogic.com> Reviewed-by: Jerome Brunet <jbrunet@baylibre.com> Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
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ce385aa2 |
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12-Oct-2017 |
Jerome Brunet <jbrunet@baylibre.com> |
pinctrl: meson: rework pinmux ops This change prepare the introduction of new meson SoC. This new SoC will share the same gpio/pinconf registers but the pinmux part will be different. While the format of the data associated with each pinmux group will change, the way to handle pinmuxing will be similar. To deal with this new situation, the meson_pmx_struture is kept but the data associated to it is now generic. This allows to reuse the basic functions which would otherwise be copy/pasted in each pinmux driver (such as getting the name a count of groups and functions) Only the functions actually using this specific data is taken out of the common code and is handling the SoC pinmuxing Reviewed-by: Neil Armstrong <narmstrong@baylibre.com> Reviewed-by: Kevin Hilman <khilman@baylibre.com> Signed-off-by: Jerome Brunet <jbrunet@baylibre.com> Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
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277d14eb |
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12-Oct-2017 |
Jerome Brunet <jbrunet@baylibre.com> |
pinctrl: meson: separate soc drivers When meson pinctrl is enabled, all meson platforms pinctrl drivers are built in the kernel, with a significant amount of data. This leads to situation where pinctrl drivers targeting an architecture are also compiled and shipped on another one (ex: meson8 - ARM - compiled and shipped on ARM64 builds). This is a waste of memory we can easily avoid. This change makes 4 pinctrl drivers (1 per SoC) out the original single driver, allowing to compile and ship only the ones required. Reviewed-by: Neil Armstrong <narmstrong@baylibre.com> Reviewed-by: Kevin Hilman <khilman@baylibre.com> Signed-off-by: Jerome Brunet <jbrunet@baylibre.com> Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
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6affd698 |
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06-Oct-2017 |
Jerome Brunet <jbrunet@baylibre.com> |
pinctrl: meson: remove unused pin_base While removing the need to have pin_base defined in meson pinctrl drivers, I forgot to remove the corresponding field from the pinctrl_data structure. Fixing this now. Fixes: 70e5ecb1b994 ("pinctrl: meson: get rid of pin_base") Signed-off-by: Jerome Brunet <jbrunet@baylibre.com> Reviewed-by: Kevin Hilman <khilman@baylibre.com> Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
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634e40b0 |
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20-Sep-2017 |
Jerome Brunet <jbrunet@baylibre.com> |
pinctrl: meson: remove offset from pinctrl Offset on meson pinctrl and gpios is something that was carried from the vendor driver, where there is a weird link between the 2 controllers. Since these 2 controllers are independent, this offset adds an unnecessary complexity. This patch remove this manually set offset and rely on pinctrl to figure out the gpio base offset Tested-by: Martin Blumenstingl <martin.blumenstingl@googlemail.com> Signed-off-by: Jerome Brunet <jbrunet@baylibre.com> Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
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6c9dc843 |
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08-Jun-2017 |
Jerome Brunet <jbrunet@baylibre.com> |
pinctrl: meson: add interrupts to pinctrl data Add GPIO interrupt information to pinctrl data. Added to the original version from Jerome was data for Meson GXL. Signed-off-by: Jerome Brunet <jbrunet@baylibre.com> Signed-off-by: Heiner Kallweit <hkallweit1@gmail.com> Acked-by: Neil Armstrong <narmstrong@baylibre.com> Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
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0f15f500 |
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31-Oct-2016 |
Neil Armstrong <narmstrong@baylibre.com> |
pinctrl: meson: Add GXL pinctrl definitions Add support for the Amlogic Meson GXL SoC, this is a partially complete definition only based on the Amlogic Vendor tree. This definition differs a lot from the GXBB and needs a separate entry. Acked-by: Rob Herring <robh@kernel.org> Signed-off-by: Neil Armstrong <narmstrong@baylibre.com> Acked-by: Kevin Hilman <khilman@baylibre.com> Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
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db80f0e1 |
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13-Aug-2016 |
Beniamino Galvani <b.galvani@gmail.com> |
pinctrl: meson: get rid of unneeded domain structures The driver originally supported more domains (register ranges) per pinctrl device, but since commit 9dab1868ec0d ("pinctrl: amlogic: Make driver independent from two-domain configuration") each device gets assigned a single domain and we instantiate multiple pinctrl devices in the DT. Therefore, now the 'meson_domain' and 'meson_domain_data' structures don't have any reason to exist and can be removed to make the model simpler to understand. This commit doesn't change behavior. Tested on a Odroid-C2. Signed-off-by: Beniamino Galvani <b.galvani@gmail.com> Acked-by: Kevin Hilman <khilman@baylibre.com> Tested-by: Kevin Hilman <khilman@baylibre.com> Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
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468c234f |
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02-May-2016 |
Carlo Caione <carlo@endlessm.com> |
pinctrl: amlogic: Add support for Amlogic Meson GXBB SoC This patch adds the basic platform file to support the pin controller found on the Amlogic Meson GXBB SoCs. Signed-off-by: Carlo Caione <carlo@endlessm.com> Reviewed-by: Kevin Hilman <khilman@baylibre.com> Tested-by: Kevin Hilman <khilman@baylibre.com> Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
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9dab1868 |
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01-Mar-2016 |
Carlo Caione <carlo@endlessm.com> |
pinctrl: amlogic: Make driver independent from two-domain configuration In the Amlogic Meson8 / Meson8b platforms we have two different buses: cbus and aobus, corresponding to 2 different power domains (regular and always-on). On each bus a different set of registers is mapped to manage muxes, GPIOs and in general to control a clear subset of the pins. Considering this architecture, having two different pinctrl devices, one for each bus / power domain, makes much more sense than just having one single device. Right now we have one single pin controller driver that uses two different domains (represented by 'gpio' and 'gpio-ao' sub-nodes in the DTS) to manage the set of registers on the two buses. This dual-domain configuration is hardcoded into the driver that strictly requires one domain for each bus in the same pin controller device. With this patch we refactor the driver to allow splitting the driver in two parts. This change is needed to have a proper description of the HW in the device-tree where we want to introduce aobus and cbus. Signed-off-by: Carlo Caione <carlo@endlessm.com> Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
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0fefcb68 |
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28-Mar-2015 |
Carlo Caione <carlo@endlessm.com> |
pinctrl: Add support for Meson8b This patch adds support for the AmLogic Meson8b SoC. Signed-off-by: Carlo Caione <carlo@endlessm.com> Acked-by: Beniamino Galvani <b.galvani@gmail.com> Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
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0cf6f3c2 |
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19-Mar-2015 |
Carlo Caione <carlo@endlessm.com> |
pinctrl: Cleanup Meson8 driver This patch introduces a new PIN macro and few small modifications to simplify and shorten the Meson pinctrl drivers and cleanup the support file for the AmLogic Meson8 SoC. Signed-off-by: Carlo Caione <carlo@endlessm.com> Acked-by: Beniamino Galvani <b.galvani@gmail.com> Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
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6ac73095 |
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17-Jan-2015 |
Beniamino Galvani <b.galvani@gmail.com> |
pinctrl: add driver for Amlogic Meson SoCs This is a driver for the pinmux and GPIO controller available in Amlogic Meson SoCs. It currently supports only Meson8, however the common code should be generic enough to work also for other SoCs after having defined the proper set of functions and groups. GPIO interrupts are not supported at the moment due to lack of documentation. Signed-off-by: Beniamino Galvani <b.galvani@gmail.com> Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
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