/linux-master/drivers/gpu/drm/radeon/ |
H A D | rv740_dpm.c | 93 u32 rv740_get_dll_speed(bool is_gddr5, u32 memory_clock) argument 104 data_rate = (u16)(memory_clock * factor / 1000); 186 u32 engine_clock, u32 memory_clock, 204 memory_clock, false, ÷rs); 246 u32 vco_freq = memory_clock * dividers.post_div; 269 memory_clock); 274 mclk->mclk770.mclk_value = cpu_to_be32(memory_clock); 408 u8 rv740_get_mclk_frequency_ratio(u32 memory_clock) argument 412 if ((memory_clock < 10000) || (memory_clock > 4750 185 rv740_populate_mclk_value(struct radeon_device *rdev, u32 engine_clock, u32 memory_clock, RV7XX_SMC_MCLK_VALUE *mclk) argument [all...] |
H A D | rv770_dpm.h | 184 u32 engine_clock, u32 memory_clock, 205 u32 engine_clock, u32 memory_clock, 212 u8 rv740_get_mclk_frequency_ratio(u32 memory_clock); 213 u32 rv740_get_dll_speed(bool is_gddr5, u32 memory_clock);
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H A D | cypress_dpm.h | 125 u32 engine_clock, u32 memory_clock); 157 u32 memory_clock, bool strobe_mode);
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H A D | si_dpm.h | 230 u8 si_get_ddr3_mclk_frequency_ratio(u32 memory_clock); 231 u8 si_get_mclk_frequency_ratio(u32 memory_clock, bool strobe_mode);
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H A D | cypress_dpm.c | 473 u32 engine_clock, u32 memory_clock, 500 memory_clock, strobe_mode, ÷rs); 554 u32 vco_freq = memory_clock * dividers.post_div; 577 memory_clock); 600 mclk->mclk770.mclk_value = cpu_to_be32(memory_clock); 614 u32 memory_clock, bool strobe_mode) 620 if (memory_clock < 10000) 622 else if (memory_clock > 47500) 625 mc_para_index = (u8)((memory_clock - 10000) / 2500); 627 if (memory_clock < 6500 472 cypress_populate_mclk_value(struct radeon_device *rdev, u32 engine_clock, u32 memory_clock, RV7XX_SMC_MCLK_VALUE *mclk, bool strobe_mode, bool dll_state_on) argument 613 cypress_get_mclk_frequency_ratio(struct radeon_device *rdev, u32 memory_clock, bool strobe_mode) argument 906 cypress_calculate_burst_time(struct radeon_device *rdev, u32 engine_clock, u32 memory_clock) argument [all...] |
H A D | rv730_dpm.c | 117 u32 engine_clock, u32 memory_clock, 133 memory_clock, false, ÷rs); 165 u32 vco_freq = memory_clock * post_divider; 185 mclk->mclk730.mclk_value = cpu_to_be32(memory_clock); 116 rv730_populate_mclk_value(struct radeon_device *rdev, u32 engine_clock, u32 memory_clock, LPRV7XX_SMC_MCLK_VALUE mclk) argument
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H A D | ci_dpm.c | 2453 const u32 memory_clock, 2465 if ((memory_clock > 100000) && (memory_clock <= 125000)) { 2469 } else if ((memory_clock > 125000) && (memory_clock <= 137500)) { 2745 u32 memory_clock, 2763 ret = radeon_atom_get_memory_pll_dividers(rdev, memory_clock, strobe_mode, &mpll_param); 2790 freq_nom = memory_clock * 4 * (1 << mpll_param.post_div); 2792 freq_nom = memory_clock * 2 * (1 << mpll_param.post_div); 2817 mclk->MclkFrequency = memory_clock; 2451 ci_register_patching_mc_arb(struct radeon_device *rdev, const u32 engine_clock, const u32 memory_clock, u32 *dram_timimg2) argument 2744 ci_calculate_mclk_params(struct radeon_device *rdev, u32 memory_clock, SMU7_Discrete_MemoryLevel *mclk, bool strobe_mode, bool dll_state_on) argument 2831 ci_populate_single_memory_level(struct radeon_device *rdev, u32 memory_clock, SMU7_Discrete_MemoryLevel *memory_level) argument 4674 ci_convert_mc_reg_table_entry_to_smc(struct radeon_device *rdev, const u32 memory_clock, SMU7_Discrete_MCRegisterSet *mc_reg_table_data) argument [all...] |
H A D | rv770_dpm.c | 319 static void rv770_calculate_fractional_mpll_feedback_divider(u32 memory_clock, argument 330 fyclk = (memory_clock * 8) / 2; 332 fyclk = (memory_clock * 4) / 2; 388 u32 engine_clock, u32 memory_clock, 412 memory_clock, false, ÷rs); 419 rv770_calculate_fractional_mpll_feedback_divider(memory_clock, reference_clock, 446 rv770_calculate_fractional_mpll_feedback_divider(memory_clock, 474 mclk->mclk770.mclk_value = cpu_to_be32(memory_clock); 387 rv770_populate_mclk_value(struct radeon_device *rdev, u32 engine_clock, u32 memory_clock, RV7XX_SMC_MCLK_VALUE *mclk) argument
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H A D | si_dpm.c | 3760 u8 si_get_ddr3_mclk_frequency_ratio(u32 memory_clock) argument 3764 if (memory_clock < 10000) 3766 else if (memory_clock >= 80000) 3769 mc_para_index = (u8)((memory_clock - 10000) / 5000 + 1); 3773 u8 si_get_mclk_frequency_ratio(u32 memory_clock, bool strobe_mode) argument 3778 if (memory_clock < 12500) 3780 else if (memory_clock > 47500) 3783 mc_para_index = (u8)((memory_clock - 10000) / 2500); 3785 if (memory_clock < 65000) 3787 else if (memory_clock > 13500 4810 si_populate_mclk_value(struct radeon_device *rdev, u32 engine_clock, u32 memory_clock, SISLANDS_SMC_MCLK_VALUE *mclk, bool strobe_mode, bool dll_state_on) argument [all...] |
H A D | ni_dpm.c | 2162 u32 memory_clock, 2184 memory_clock, strobe_mode, ÷rs); 2238 u32 vco_freq = memory_clock * dividers.post_div; 2261 memory_clock); 2285 mclk->mclk_value = cpu_to_be32(memory_clock); 2160 ni_populate_mclk_value(struct radeon_device *rdev, u32 engine_clock, u32 memory_clock, NISLANDS_SMC_MCLK_VALUE *mclk, bool strobe_mode, bool dll_state_on) argument
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/linux-master/drivers/gpu/drm/amd/pm/powerplay/smumgr/ |
H A D | iceland_smumgr.c | 1046 uint32_t memory_clock, 1068 memory_clock, &mpll_param, strobe_mode); 1119 freq_nom = memory_clock * 4 * (1 << mpll_param.mpll_post_divider); 1121 freq_nom = memory_clock * 2 * (1 << mpll_param.mpll_post_divider); 1155 mclk->MclkFrequency = memory_clock; 1169 static uint8_t iceland_get_mclk_frequency_ratio(uint32_t memory_clock, argument 1175 if (memory_clock < 12500) { 1177 } else if (memory_clock > 47500) { 1180 mc_para_index = (uint8_t)((memory_clock - 10000) / 2500); 1183 if (memory_clock < 6500 1044 iceland_calculate_mclk_params( struct pp_hwmgr *hwmgr, uint32_t memory_clock, SMU71_Discrete_MemoryLevel *mclk, bool strobe_mode, bool dllStateOn ) argument 1195 iceland_get_ddr3_mclk_frequency_ratio(uint32_t memory_clock) argument 1210 iceland_populate_phase_value_based_on_mclk(struct pp_hwmgr *hwmgr, const struct phm_phase_shedding_limits_table *pl, uint32_t memory_clock, uint32_t *p_shed) argument 1227 iceland_populate_single_memory_level( struct pp_hwmgr *hwmgr, uint32_t memory_clock, SMU71_Discrete_MemoryLevel *memory_level ) argument 1582 iceland_populate_memory_timing_parameters( struct pp_hwmgr *hwmgr, uint32_t engine_clock, uint32_t memory_clock, struct SMU71_Discrete_MCArbDramTimingTableEntry *arb_regs ) argument 1728 iceland_convert_mc_reg_table_entry_to_smc(struct pp_hwmgr *hwmgr, const uint32_t memory_clock, SMU71_Discrete_MCRegisterSet *mc_reg_table_data ) argument [all...] |
H A D | ci_smumgr.c | 1025 uint32_t memory_clock, 1046 memory_clock, &mpll_param, strobe_mode); 1078 freq_nom = memory_clock * 4 * (1 << mpll_param.mpll_post_divider); 1080 freq_nom = memory_clock * 2 * (1 << mpll_param.mpll_post_divider); 1105 mclk->MclkFrequency = memory_clock; 1119 static uint8_t ci_get_mclk_frequency_ratio(uint32_t memory_clock, argument 1125 if (memory_clock < 12500) 1127 else if (memory_clock > 47500) 1130 mc_para_index = (uint8_t)((memory_clock - 10000) / 2500); 1132 if (memory_clock < 6500 1023 ci_calculate_mclk_params( struct pp_hwmgr *hwmgr, uint32_t memory_clock, SMU7_Discrete_MemoryLevel *mclk, bool strobe_mode, bool dllStateOn ) argument 1143 ci_get_ddr3_mclk_frequency_ratio(uint32_t memory_clock) argument 1157 ci_populate_phase_value_based_on_mclk(struct pp_hwmgr *hwmgr, const struct phm_phase_shedding_limits_table *pl, uint32_t memory_clock, uint32_t *p_shed) argument 1174 ci_populate_single_memory_level( struct pp_hwmgr *hwmgr, uint32_t memory_clock, SMU7_Discrete_MemoryLevel *memory_level ) argument 1621 ci_populate_memory_timing_parameters( struct pp_hwmgr *hwmgr, uint32_t engine_clock, uint32_t memory_clock, struct SMU7_Discrete_MCArbDramTimingTableEntry *arb_regs ) argument 1762 ci_convert_mc_reg_table_entry_to_smc( struct pp_hwmgr *hwmgr, const uint32_t memory_clock, SMU7_Discrete_MCRegisterSet *mc_reg_table_data ) argument [all...] |
H A D | tonga_smumgr.c | 789 uint32_t memory_clock, 811 memory_clock, &mpll_param, strobe_mode); 871 freq_nom = memory_clock * 4 * (1 << mpll_param.mpll_post_divider); 873 freq_nom = memory_clock * 2 * (1 << mpll_param.mpll_post_divider); 906 mclk->MclkFrequency = memory_clock; 920 static uint8_t tonga_get_mclk_frequency_ratio(uint32_t memory_clock, argument 926 if (memory_clock < 12500) 928 else if (memory_clock > 47500) 931 mc_para_index = (uint8_t)((memory_clock - 10000) / 2500); 933 if (memory_clock < 6500 787 tonga_calculate_mclk_params( struct pp_hwmgr *hwmgr, uint32_t memory_clock, SMU72_Discrete_MemoryLevel *mclk, bool strobe_mode, bool dllStateOn ) argument 944 tonga_get_ddr3_mclk_frequency_ratio(uint32_t memory_clock) argument 959 tonga_populate_single_memory_level( struct pp_hwmgr *hwmgr, uint32_t memory_clock, SMU72_Discrete_MemoryLevel *memory_level ) argument 1457 tonga_populate_memory_timing_parameters( struct pp_hwmgr *hwmgr, uint32_t engine_clock, uint32_t memory_clock, struct SMU72_Discrete_MCArbDramTimingTableEntry *arb_regs ) argument 2106 tonga_convert_mc_reg_table_entry_to_smc( struct pp_hwmgr *hwmgr, const uint32_t memory_clock, SMU72_Discrete_MCRegisterSet *mc_reg_table_data ) argument [all...] |
/linux-master/drivers/gpu/drm/amd/pm/powerplay/hwmgr/ |
H A D | ppatomctrl.h | 299 extern int atomctrl_get_memory_clock_spread_spectrum(struct pp_hwmgr *hwmgr, const uint32_t memory_clock, pp_atomctrl_internal_ss_info *ssInfo); 303 extern int atomctrl_set_engine_dram_timings_rv770(struct pp_hwmgr *hwmgr, uint32_t engine_clock, uint32_t memory_clock); 322 extern int atomctrl_set_ac_timing_ai(struct pp_hwmgr *hwmgr, uint32_t memory_clock,
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H A D | smu7_hwmgr.c | 3348 if (smu7_ps->performance_levels[i].memory_clock > max_limits->mclk) 3349 smu7_ps->performance_levels[i].memory_clock = max_limits->mclk; 3402 mclk = smu7_ps->performance_levels[0].memory_clock; 3408 [smu7_ps->performance_level_count - 1].memory_clock; 3419 smu7_ps->performance_levels[0].memory_clock = mclk; 3428 if (mclk < smu7_ps->performance_levels[1].memory_clock) 3429 mclk = smu7_ps->performance_levels[1].memory_clock; 3442 smu7_ps->performance_levels[0].memory_clock) && 3444 smu7_ps->performance_levels[1].memory_clock)) { 3458 mclk = smu7_ps->performance_levels[1].memory_clock; 3798 uint32_t engine_clock, memory_clock; local [all...] |
H A D | hardwaremanager.c | 401 pclock_info->min_mem_clk = performance_level.memory_clock; 411 pclock_info->max_mem_clk = performance_level.memory_clock;
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H A D | smu7_hwmgr.h | 55 uint32_t memory_clock; member in struct:smu7_performance_level
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H A D | ppatomctrl.c | 212 uint32_t memory_clock) 225 cpu_to_le32(memory_clock & SET_CLOCK_FREQ_MASK); 1322 const uint32_t memory_clock, 1326 ASIC_INTERNAL_MEMORY_SS, memory_clock, ssInfo); 1368 int atomctrl_set_ac_timing_ai(struct pp_hwmgr *hwmgr, uint32_t memory_clock, argument 1376 memory_clock & SET_CLOCK_FREQ_MASK; 209 atomctrl_set_engine_dram_timings_rv770( struct pp_hwmgr *hwmgr, uint32_t engine_clock, uint32_t memory_clock) argument 1320 atomctrl_get_memory_clock_spread_spectrum( struct pp_hwmgr *hwmgr, const uint32_t memory_clock, pp_atomctrl_internal_ss_info *ssInfo) argument
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H A D | smu10_hwmgr.c | 1118 level->memory_clock = data->clock_vol_info.vdd_dep_on_fclk->entries[0].clk; 1121 level->memory_clock = data->clock_vol_info.vdd_dep_on_fclk->entries[
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H A D | smu8_hwmgr.c | 1624 level->memory_clock = data->sys_info.nbp_memory_clock[SMU8_NUM_NBPMEMORYCLOCK - 1]; 1626 level->memory_clock = data->sys_info.nbp_memory_clock[0];
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/linux-master/drivers/gpu/drm/amd/pm/powerplay/inc/ |
H A D | hardwaremanager.h | 272 uint32_t memory_clock; member in struct:PHM_PerformanceLevel
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/linux-master/drivers/gpu/drm/amd/pm/swsmu/inc/ |
H A D | amdgpu_smu.h | 269 uint32_t memory_clock; member in struct:smu_performance_level 401 uint32_t memory_clock; member in struct:smu_clocks
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/linux-master/drivers/gpu/drm/amd/pm/legacy-dpm/ |
H A D | si_dpm.c | 4284 static u8 si_get_ddr3_mclk_frequency_ratio(u32 memory_clock) argument 4288 if (memory_clock < 10000) 4290 else if (memory_clock >= 80000) 4293 mc_para_index = (u8)((memory_clock - 10000) / 5000 + 1); 4297 static u8 si_get_mclk_frequency_ratio(u32 memory_clock, bool strobe_mode) argument 4302 if (memory_clock < 12500) 4304 else if (memory_clock > 47500) 4307 mc_para_index = (u8)((memory_clock - 10000) / 2500); 4309 if (memory_clock < 65000) 4311 else if (memory_clock > 13500 5356 si_populate_mclk_value(struct amdgpu_device *adev, u32 engine_clock, u32 memory_clock, SISLANDS_SMC_MCLK_VALUE *mclk, bool strobe_mode, bool dll_state_on) argument [all...] |
/linux-master/drivers/gpu/drm/amd/pm/swsmu/smu11/ |
H A D | navi10_ppt.c | 2083 min_clocks.memory_clock = smu->display_config->min_mem_set_clock; 2107 ret = smu_v11_0_set_hard_freq_limited_range(smu, SMU_UCLK, min_clocks.memory_clock/100, 0);
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H A D | sienna_cichlid_ppt.c | 1799 min_clocks.memory_clock = smu->display_config->min_mem_set_clock; 1823 ret = smu_v11_0_set_hard_freq_limited_range(smu, SMU_UCLK, min_clocks.memory_clock/100, 0);
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