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88f489d2 |
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08-Jun-2019 |
Sam Ravnborg <sam@ravnborg.org> |
drm/radeon: prepare header files for drmP.h removal While removing drmP.h from all .c files the list of header files are also sorted alphabetically. To allow this adjust the header files to pull in the dependencies they needed to allow this. Signed-off-by: Sam Ravnborg <sam@ravnborg.org> Reviewed-by: Alex Deucher <alexander.deucher@amd.com> Cc: "Christian König" <christian.koenig@amd.com> Cc: "David (ChunMing) Zhou" <David1.Zhou@amd.com> Cc: David Airlie <airlied@linux.ie> Cc: Daniel Vetter <daniel@ffwll.ch> Link: https://patchwork.freedesktop.org/patch/msgid/20190608080241.4958-6-sam@ravnborg.org
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49ead33b |
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14-Jan-2015 |
Alex Deucher <alexander.deucher@amd.com> |
drm/radeon: comment out some currently unused 7xx dpm code Keep it around for reference. Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
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e14cd2bb |
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19-Dec-2013 |
Alex Deucher <alexander.deucher@amd.com> |
drm/radeon/dpm: switch on new late_enable callback Right now it's called right after enable, but after reworking the dpm init order, it will get called later to accomodate loading the smc early, but enabling thermal interrupts and block powergating later after the ring tests are complete. Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
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b841ce7b |
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31-Jul-2013 |
Alex Deucher <alexander.deucher@amd.com> |
drm/radeon/dpm: fix spread spectrum setup (v2) Need to check for engine and memory clock ss separately and only enable dynamic ss if either of them are found. This should fix systems which have a ss table, but do not have entries for engine or memory. On those systems we may enable dynamic spread spectrum without enabling it on the engine or memory clocks which can lead to a hang in some cases. fixes some systems reported here: https://bugs.freedesktop.org/show_bug.cgi?id=66963 v2: fix typo Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
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8b5e6b7f |
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02-Jul-2013 |
Alex Deucher <alexander.deucher@amd.com> |
drm/radeon/dpm: implement force performance levels for 7xx/eg/btc Allows you to limit the selected power levels via sysfs. Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
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a9e61410 |
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25-Jun-2013 |
Alex Deucher <alexander.deucher@amd.com> |
drm/radeon/kms: add dpm support for SI (v7) This adds dpm support for SI asics. This includes: - dynamic engine clock scaling - dynamic memory clock scaling - dynamic voltage scaling - dynamic pcie gen1/gen2/gen3 switching - power containment - shader power scaling Set radeon.dpm=1 to enable. v2: enable hainan support, rebase v3: guard acpi stuff v4: fix 64 bit math v5: fix 64 bit div harder v6: fix thermal interrupt check noticed by Jerome v7: attempt fix state enable Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
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5d77d776 |
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27-Jun-2013 |
Alex Deucher <alexander.deucher@amd.com> |
drm/radeon/dpm/rv7xx: restructure code Needed to properly handle dynamic state adjustment. Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
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f85392bc |
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25-Jun-2013 |
Alex Deucher <alexander.deucher@amd.com> |
drm/radeon: add dpm UVD handling for evergreen/btc asics Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
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7c464f68 |
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27-Jun-2013 |
Alex Deucher <alexander.deucher@amd.com> |
drm/radeon: add dpm UVD handling for r7xx asics Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
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dc50ba7f |
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25-Jun-2013 |
Alex Deucher <alexander.deucher@amd.com> |
drm/radeon/kms: add dpm support for evergreen (v4) This adds dpm support for evergreen asics. This includes: - clockgating - dynamic engine clock scaling - dynamic memory clock scaling - dynamic voltage scaling - dynamic pcie gen1/gen2 switching (requires additional acpi support) Set radeon.dpm=1 to enable. v2: reduce stack usage, rename ulv struct v3: fix thermal interrupt check notices by Jerome v4: fix state enable Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
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66229b20 |
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25-Jun-2013 |
Alex Deucher <alexander.deucher@amd.com> |
drm/radeon/kms: add dpm support for rv7xx (v4) This adds dpm support for rv7xx asics. This includes: - clockgating - dynamic engine clock scaling - dynamic memory clock scaling - dynamic voltage scaling - dynamic pcie gen1/gen2 switching Set radeon.dpm=1 to enable. v2: reduce stack usage v3: fix 64 bit div v4: fix state enable Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
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