Searched refs:mdiv (Results 1 - 25 of 34) sorted by relevance

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/linux-master/drivers/clk/bcm/
H A Dclk-ns2.c52 .mdiv = REG_VAL(0x18, 0, 8),
58 .mdiv = REG_VAL(0x18, 8, 8),
64 .mdiv = REG_VAL(0x14, 0, 8),
70 .mdiv = REG_VAL(0x14, 8, 8),
76 .mdiv = REG_VAL(0x14, 16, 8),
82 .mdiv = REG_VAL(0x14, 24, 8),
114 .mdiv = REG_VAL(0x18, 0, 8),
120 .mdiv = REG_VAL(0x18, 8, 8),
126 .mdiv = REG_VAL(0x14, 0, 8),
132 .mdiv
[all...]
H A Dclk-sr.c52 .mdiv = REG_VAL(0x18, 0, 9),
58 .mdiv = REG_VAL(0x18, 10, 9),
64 .mdiv = REG_VAL(0x18, 20, 9),
70 .mdiv = REG_VAL(0x1c, 0, 9),
76 .mdiv = REG_VAL(0x1c, 10, 9),
82 .mdiv = REG_VAL(0x1c, 20, 9),
112 .mdiv = REG_VAL(0x18, 0, 9),
118 .mdiv = REG_VAL(0x18, 10, 9),
124 .mdiv = REG_VAL(0x18, 20, 9),
130 .mdiv
[all...]
H A Dclk-cygnus.c66 .mdiv = REG_VAL(0x20, 0, 8),
72 .mdiv = REG_VAL(0x20, 10, 8),
78 .mdiv = REG_VAL(0x20, 20, 8),
84 .mdiv = REG_VAL(0x24, 0, 8),
90 .mdiv = REG_VAL(0x24, 10, 8),
96 .mdiv = REG_VAL(0x24, 20, 8),
124 .mdiv = REG_VAL(0x8, 0, 8),
130 .mdiv = REG_VAL(0x8, 10, 8),
136 .mdiv = REG_VAL(0x8, 20, 8),
142 .mdiv
[all...]
H A Dclk-iproc-armpll.c99 * Determine the mdiv (post divider) based on the frequency ID being used.
109 int mdiv; local
117 mdiv = 1;
122 mdiv = val & IPROC_CLK_PLLARMC_MDIV_MASK;
123 if (mdiv == 0)
124 mdiv = 256;
129 mdiv = val & IPROC_CLK_PLLARMCTL5_H_MDIV_MASK;
130 if (mdiv == 0)
131 mdiv = 256;
135 mdiv
190 int mdiv; local
[all...]
H A Dclk-nsp.c51 .mdiv = REG_VAL(0x18, 16, 8),
57 .mdiv = REG_VAL(0x18, 8, 8),
63 .mdiv = REG_VAL(0x18, 0, 8),
69 .mdiv = REG_VAL(0x1c, 16, 8),
75 .mdiv = REG_VAL(0x1c, 8, 8),
81 .mdiv = REG_VAL(0x1c, 0, 8),
108 .mdiv = REG_VAL(0x8, 24, 8),
114 .mdiv = REG_VAL(0x8, 16, 8),
120 .mdiv = REG_VAL(0x8, 8, 8),
H A Dclk-iproc-pll.c617 unsigned int mdiv; local
623 val = readl(pll->control_base + ctrl->mdiv.offset);
624 mdiv = (val >> ctrl->mdiv.shift) & bit_mask(ctrl->mdiv.width);
625 if (mdiv == 0)
626 mdiv = 256;
629 rate = parent_rate / (mdiv * 2);
631 rate = parent_rate / mdiv;
677 val = readl(pll->control_base + ctrl->mdiv
[all...]
H A Dclk-iproc.h187 struct iproc_clk_reg_op mdiv; member in struct:iproc_clk_ctrl
/linux-master/drivers/clk/samsung/
H A Dclk-pll.h55 .mdiv = (_m), \
64 .mdiv = (_m), \
74 .mdiv = (_m), \
84 .mdiv = (_m), \
95 .mdiv = (_m), \
109 unsigned int mdiv; member in struct:samsung_pll_rate_table
H A Dclk-pll.c153 u32 pll_con, mdiv, pdiv, sdiv; local
157 mdiv = (pll_con >> PLL2126_MDIV_SHIFT) & PLL2126_MDIV_MASK;
161 fvco *= (mdiv + 8);
186 u32 pll_con, mdiv, pdiv, sdiv; local
190 mdiv = (pll_con >> PLL3000_MDIV_SHIFT) & PLL3000_MDIV_MASK;
194 fvco *= (2 * (mdiv + 8));
223 u32 mdiv, pdiv, sdiv, pll_con; local
227 mdiv = (pll_con >> PLL35XX_MDIV_SHIFT) & PLL35XX_MDIV_MASK;
231 fvco *= mdiv;
245 return (rate->mdiv !
327 u32 mdiv, pdiv, sdiv, pll_con0, pll_con1; local
437 u32 mdiv, pdiv, sdiv, pll_con3; local
525 u32 mdiv, pdiv, sdiv, pll_con3, pll_con5; local
623 u32 mdiv, pdiv, sdiv, pll_con; local
756 u32 mdiv, pdiv, sdiv, kdiv, pll_con0, pll_con1, shift; local
885 u32 mdiv, pdiv, sdiv, pll_con; local
925 u32 mdiv, pdiv, sdiv, kdiv, pll_con0, pll_con1; local
1004 u32 mdiv, pdiv, sdiv, pll_con; local
1018 samsung_pll2550xx_mp_change(u32 mdiv, u32 pdiv, u32 pll_con) argument
1105 u32 mdiv, pdiv, sdiv, pll_con0, pll_con1; local
1196 u32 mdiv, pdiv, sdiv, pll_con0, pll_con2; local
[all...]
/linux-master/drivers/clk/imx/
H A Dclk-pll14xx.c104 static long pll14xx_calc_rate(struct clk_pll14xx *pll, int mdiv, int pdiv, argument
110 fout *= (mdiv * 65536 + kdiv);
118 static long pll1443x_calc_kdiv(int mdiv, int pdiv, int sdiv, argument
123 /* calc kdiv = round(rate * pdiv * 65536 * 2^sdiv / prate) - (mdiv * 65536) */
124 kdiv = ((rate * ((pdiv * 65536) << sdiv) + prate / 2) / prate) - (mdiv * 65536);
133 int mdiv, pdiv, sdiv, kdiv; local
155 t->mdiv = tt->mdiv;
163 mdiv = FIELD_GET(MDIV_MASK, pll_div_ctl0);
169 rate_min = pll14xx_calc_rate(pll, mdiv, pdi
248 u32 mdiv, pdiv, sdiv, kdiv, pll_div_ctl0, pll_div_ctl1; local
[all...]
H A Dclk.h60 unsigned int mdiv; member in struct:imx_pll14xx_rate_table
266 .mdiv = (_m), \
274 .mdiv = (_m), \
/linux-master/drivers/clk/socfpga/
H A Dclk-pll-s10.c65 unsigned long arefdiv, reg, mdiv; local
74 /* Read mdiv and fdiv from the fdbck register */
76 mdiv = reg & SOCFPGA_AGILEX_PLL_MDIV_MASK;
78 vco_freq = (unsigned long long)vco_freq * mdiv;
86 unsigned long mdiv; local
98 /* Read mdiv and fdiv from the fdbck register */
100 mdiv = (reg & SOCFPGA_PLL_MDIV_MASK) >> SOCFPGA_PLL_MDIV_SHIFT;
101 vco_freq = (unsigned long long)vco_freq * (mdiv + 6);
/linux-master/drivers/clk/st/
H A Dclkgen-fsyn.c35 unsigned long mdiv; member in struct:stm_fs
58 struct clkgen_field mdiv[QUADFS_MAX_CHAN]; member in struct:clkgen_quadfs_data
102 .mdiv = { CLKGEN_FIELD(0x304, 0x1f, 15),
165 .mdiv = { CLKGEN_FIELD(0x2b4, 0x1f, 15),
554 CLKGEN_WRITE(fs, mdiv[fs->chan], fs->md);
639 res = (P20 * (32 + fs->mdiv) + 32 * fs->pe) * s * ns;
663 fs_tmp.mdiv = (unsigned long) m;
673 fs->mdiv = m;
719 fs_tmp.mdiv = fs->mdiv;
[all...]
/linux-master/drivers/media/dvb-frontends/
H A Dhorus3a.c172 u8 mdiv = 0; local
190 mdiv = 1;
193 mdiv = 0;
296 data[4] = (u8)(mdiv << 7);
/linux-master/drivers/gpu/drm/nouveau/nvkm/subdev/clk/
H A Dgk104.c35 u32 mdiv; member in struct:gk104_clk_info
320 info->mdiv |= 0x80000000;
321 info->mdiv |= div1D;
327 info->mdiv |= 0x80000000;
328 info->mdiv |= div1P << 8;
416 nvkm_mask(device, 0x137250 + (idx * 0x04), 0x00003f00, info->mdiv);
418 nvkm_mask(device, 0x137250 + (idx * 0x04), 0x0000003f, info->mdiv);
H A Dgf100.c35 u32 mdiv; member in struct:gf100_clk_info
307 info->mdiv |= 0x80000000;
308 info->mdiv |= div1D;
314 info->mdiv |= 0x80000000;
315 info->mdiv |= div1P << 8;
412 nvkm_mask(device, 0x137250 + (idx * 0x04), 0x00003f3f, info->mdiv);
/linux-master/sound/soc/codecs/
H A Dak4375.c279 unsigned int mclk, plm, mdiv, div; local
327 mdiv = freq_out / mclk - 1;
332 mdiv = freq_out / mclk - 1;
337 mdiv = 4;
359 snd_soc_component_write(component, AK4375_14_DAC_CLK_DIVIDER, mdiv);
362 ak4375->rate, mclk, freq_in, freq_out, ak4375->pld, plm, mdiv, div);
/linux-master/drivers/gpu/drm/nouveau/include/nvkm/subdev/
H A Dclk.h79 int mdiv; member in struct:nvkm_domain
/linux-master/drivers/gpu/drm/nouveau/nvkm/engine/device/
H A Dctrl.c126 args->v0.min = lo / domain->mdiv;
127 args->v0.max = hi / domain->mdiv;
/linux-master/drivers/phy/rockchip/
H A Dphy-rockchip-samsung-hdptx.c689 u32 mdiv, sdiv, n = 8; local
703 mdiv = DIV_ROUND_UP(fvco, fref);
704 if (mdiv < 20 || mdiv > 255)
707 if (fref * mdiv - fvco) {
709 if (sdc * n > fref * mdiv)
715 rational_best_approximation(fref * mdiv - fvco,
721 rational_best_approximation(sdc * n - fref * mdiv,
735 cfg->pms_mdiv = mdiv;
736 cfg->pms_mdiv_afc = mdiv;
[all...]
/linux-master/drivers/iio/frequency/
H A Dadf4350.c140 u16 mdiv, r_cnt = 0; local
148 mdiv = 75;
151 mdiv = 23;
187 } while (mdiv > st->r0_int);
/linux-master/drivers/gpu/drm/i915/display/
H A Dintel_dpll.c488 u32 mdiv; local
496 mdiv = vlv_dpio_read(dev_priv, phy, VLV_PLL_DW3(crtc->pipe));
499 clock.m1 = (mdiv >> DPIO_M1DIV_SHIFT) & 7;
500 clock.m2 = mdiv & DPIO_M2DIV_MASK;
501 clock.n = (mdiv >> DPIO_N_SHIFT) & 0xf;
502 clock.p1 = (mdiv >> DPIO_P1_SHIFT) & 7;
503 clock.p2 = (mdiv >> DPIO_P2_SHIFT) & 0x1f;
1848 u32 mdiv; local
1878 mdiv = ((bestm1 << DPIO_M1DIV_SHIFT) | (bestm2 & DPIO_M2DIV_MASK));
1879 mdiv |
[all...]
/linux-master/drivers/clk/
H A Dclk-versaclock3.c246 u8 mdiv; local
258 mdiv = VC3_PLL1_M_DIV(prediv);
269 mdiv = VC3_PLL2_M_DIV(prediv);
275 mdiv = VC3_PLL3_M_DIV(prediv);
281 rate = parent_rate / mdiv;
/linux-master/drivers/i2c/busses/
H A Di2c-octeon-core.c661 int thp = 0x18, mdiv = 2, ndiv = 0, delta_hz = 1000000; local
665 * An mdiv value of less than 2 seems to not work well
670 * For given ndiv and mdiv values check the
689 mdiv = mdiv_idx;
696 octeon_i2c_reg_write(i2c, SW_TWSI_EOP_TWSI_CLKCTL, (mdiv << 3) | ndiv);
/linux-master/drivers/clk/nxp/
H A Dclk-lpc18xx-cgu.c351 u32 ctrl, mdiv, msel, npdiv; local
354 mdiv = readl(pll->reg + LPC18XX_CGU_PLL0USB_MDIV);
365 msel = lpc18xx_pll0_mdec2msel(mdiv & LPC18XX_PLL0_MDIV_MDEC_MASK);

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