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f713c6bf |
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15-Oct-2015 |
Jon Mason <jonmason@broadcom.com> |
clk: iproc: Split off dig_filter The PLL loop filter/gain can be located in a separate register on some SoCs. Split these off into a separate variable, so that an offset can be added if necessary. Also, make the necessary modifications to the Cygnus and NSP drivers for this change. Signed-off-by: Jon Mason <jonmason@broadcom.com> Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>
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5f024b06 |
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15-Oct-2015 |
Jon Mason <jonmason@broadcom.com> |
clk: nsp: add clock support for Broadcom Northstar Plus SoC The Broadcom Northstar Plus SoC is architected under the iProc architecture. It has the following PLLs: ARMPLL, GENPLL, LCPLL0, all derived from an onboard crystal. Signed-off-by: Jon Mason <jonmason@broadcom.com> Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>
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