1176491Smarcel// SPDX-License-Identifier: GPL-2.0-only 2176491Smarcel// Copyright (C) 2015 Broadcom Corporation 3176491Smarcel 4176491Smarcel#include <linux/kernel.h> 5176491Smarcel#include <linux/err.h> 6176491Smarcel#include <linux/clk-provider.h> 7176491Smarcel#include <linux/io.h> 8176491Smarcel#include <linux/of.h> 9176491Smarcel#include <linux/of_address.h> 10176491Smarcel 11176491Smarcel#include <dt-bindings/clock/bcm-nsp.h> 12176491Smarcel#include "clk-iproc.h" 13176491Smarcel 14176491Smarcel#define REG_VAL(o, s, w) { .offset = o, .shift = s, .width = w, } 15176491Smarcel 16176491Smarcel#define AON_VAL(o, pw, ps, is) { .offset = o, .pwr_width = pw, \ 17176491Smarcel .pwr_shift = ps, .iso_shift = is } 18176491Smarcel 19176491Smarcel#define RESET_VAL(o, rs, prs) { .offset = o, .reset_shift = rs, \ 20176491Smarcel .p_reset_shift = prs } 21176491Smarcel 22176491Smarcel#define DF_VAL(o, kis, kiw, kps, kpw, kas, kaw) { .offset = o, .ki_shift = kis,\ 23176491Smarcel .ki_width = kiw, .kp_shift = kps, .kp_width = kpw, .ka_shift = kas, \ 24176491Smarcel .ka_width = kaw } 25176491Smarcel 26176491Smarcel#define ENABLE_VAL(o, es, hs, bs) { .offset = o, .enable_shift = es, \ 27176491Smarcel .hold_shift = hs, .bypass_shift = bs } 28176491Smarcel 29176491Smarcelstatic void __init nsp_armpll_init(struct device_node *node) 30176491Smarcel{ 31176491Smarcel iproc_armpll_setup(node); 32176491Smarcel} 33176491SmarcelCLK_OF_DECLARE(nsp_armpll, "brcm,nsp-armpll", nsp_armpll_init); 34176491Smarcel 35176491Smarcelstatic const struct iproc_pll_ctrl genpll = { 36176491Smarcel .flags = IPROC_CLK_PLL_HAS_NDIV_FRAC | IPROC_CLK_EMBED_PWRCTRL, 37176491Smarcel .aon = AON_VAL(0x0, 1, 12, 0), 38176491Smarcel .reset = RESET_VAL(0x0, 11, 10), 39176491Smarcel .dig_filter = DF_VAL(0x0, 4, 3, 0, 4, 7, 3), 40176491Smarcel .ndiv_int = REG_VAL(0x14, 20, 10), 41176491Smarcel .ndiv_frac = REG_VAL(0x14, 0, 20), 42176491Smarcel .pdiv = REG_VAL(0x18, 24, 3), 43176491Smarcel .status = REG_VAL(0x20, 12, 1), 44176491Smarcel}; 45176491Smarcel 46176491Smarcelstatic const struct iproc_clk_ctrl genpll_clk[] = { 47176491Smarcel [BCM_NSP_GENPLL_PHY_CLK] = { 48176491Smarcel .channel = BCM_NSP_GENPLL_PHY_CLK, 49176491Smarcel .flags = IPROC_CLK_AON, 50178030Sgrehan .enable = ENABLE_VAL(0x4, 12, 6, 18), 51176491Smarcel .mdiv = REG_VAL(0x18, 16, 8), 52176491Smarcel }, 53176491Smarcel [BCM_NSP_GENPLL_ENET_SW_CLK] = { 54176491Smarcel .channel = BCM_NSP_GENPLL_ENET_SW_CLK, 55176491Smarcel .flags = IPROC_CLK_AON, 56176491Smarcel .enable = ENABLE_VAL(0x4, 13, 7, 19), 57176491Smarcel .mdiv = REG_VAL(0x18, 8, 8), 58176491Smarcel }, 59176491Smarcel [BCM_NSP_GENPLL_USB_PHY_REF_CLK] = { 60176491Smarcel .channel = BCM_NSP_GENPLL_USB_PHY_REF_CLK, 61176491Smarcel .flags = IPROC_CLK_AON, 62176491Smarcel .enable = ENABLE_VAL(0x4, 14, 8, 20), 63176491Smarcel .mdiv = REG_VAL(0x18, 0, 8), 64176491Smarcel }, 65176491Smarcel [BCM_NSP_GENPLL_IPROCFAST_CLK] = { 66176491Smarcel .channel = BCM_NSP_GENPLL_IPROCFAST_CLK, 67176491Smarcel .flags = IPROC_CLK_AON, 68176491Smarcel .enable = ENABLE_VAL(0x4, 15, 9, 21), 69176491Smarcel .mdiv = REG_VAL(0x1c, 16, 8), 70176491Smarcel }, 71176491Smarcel [BCM_NSP_GENPLL_SATA1_CLK] = { 72176491Smarcel .channel = BCM_NSP_GENPLL_SATA1_CLK, 73176491Smarcel .flags = IPROC_CLK_AON, 74176491Smarcel .enable = ENABLE_VAL(0x4, 16, 10, 22), 75176491Smarcel .mdiv = REG_VAL(0x1c, 8, 8), 76176491Smarcel }, 77176491Smarcel [BCM_NSP_GENPLL_SATA2_CLK] = { 78176491Smarcel .channel = BCM_NSP_GENPLL_SATA2_CLK, 79176491Smarcel .flags = IPROC_CLK_AON, 80176491Smarcel .enable = ENABLE_VAL(0x4, 17, 11, 23), 81176491Smarcel .mdiv = REG_VAL(0x1c, 0, 8), 82176491Smarcel }, 83176491Smarcel}; 84176491Smarcel 85176491Smarcelstatic void __init nsp_genpll_clk_init(struct device_node *node) 86176491Smarcel{ 87176491Smarcel iproc_pll_clk_setup(node, &genpll, NULL, 0, genpll_clk, 88176491Smarcel ARRAY_SIZE(genpll_clk)); 89176491Smarcel} 90176491SmarcelCLK_OF_DECLARE(nsp_genpll_clk, "brcm,nsp-genpll", nsp_genpll_clk_init); 91176491Smarcel 92176491Smarcelstatic const struct iproc_pll_ctrl lcpll0 = { 93176491Smarcel .flags = IPROC_CLK_PLL_HAS_NDIV_FRAC | IPROC_CLK_EMBED_PWRCTRL, 94176491Smarcel .aon = AON_VAL(0x0, 1, 24, 0), 95176491Smarcel .reset = RESET_VAL(0x0, 23, 22), 96176491Smarcel .dig_filter = DF_VAL(0x0, 16, 3, 12, 4, 19, 4), 97176491Smarcel .ndiv_int = REG_VAL(0x4, 20, 8), 98176491Smarcel .ndiv_frac = REG_VAL(0x4, 0, 20), 99176491Smarcel .pdiv = REG_VAL(0x4, 28, 3), 100176491Smarcel .status = REG_VAL(0x10, 12, 1), 101176491Smarcel}; 102176491Smarcel 103176491Smarcelstatic const struct iproc_clk_ctrl lcpll0_clk[] = { 104176491Smarcel [BCM_NSP_LCPLL0_PCIE_PHY_REF_CLK] = { 105176491Smarcel .channel = BCM_NSP_LCPLL0_PCIE_PHY_REF_CLK, 106176491Smarcel .flags = IPROC_CLK_AON, 107176491Smarcel .enable = ENABLE_VAL(0x0, 6, 3, 9), 108176491Smarcel .mdiv = REG_VAL(0x8, 24, 8), 109176491Smarcel }, 110176491Smarcel [BCM_NSP_LCPLL0_SDIO_CLK] = { 111176491Smarcel .channel = BCM_NSP_LCPLL0_SDIO_CLK, 112176491Smarcel .flags = IPROC_CLK_AON, 113176491Smarcel .enable = ENABLE_VAL(0x0, 7, 4, 10), 114176491Smarcel .mdiv = REG_VAL(0x8, 16, 8), 115176491Smarcel }, 116176491Smarcel [BCM_NSP_LCPLL0_DDR_PHY_CLK] = { 117176491Smarcel .channel = BCM_NSP_LCPLL0_DDR_PHY_CLK, 118176491Smarcel .flags = IPROC_CLK_AON, 119176491Smarcel .enable = ENABLE_VAL(0x0, 8, 5, 11), 120176491Smarcel .mdiv = REG_VAL(0x8, 8, 8), 121176491Smarcel }, 122176491Smarcel}; 123176491Smarcel 124176491Smarcelstatic void __init nsp_lcpll0_clk_init(struct device_node *node) 125176491Smarcel{ 126176491Smarcel iproc_pll_clk_setup(node, &lcpll0, NULL, 0, lcpll0_clk, 127176491Smarcel ARRAY_SIZE(lcpll0_clk)); 128176491Smarcel} 129176491SmarcelCLK_OF_DECLARE(nsp_lcpll0_clk, "brcm,nsp-lcpll0", nsp_lcpll0_clk_init); 130176491Smarcel