Searched refs:mc_reg_address (Results 1 - 23 of 23) sorted by relevance

/linux-master/drivers/gpu/drm/amd/pm/powerplay/smumgr/
H A Dci_smumgr.h58 SMU7_Discrete_MCRegisterAddress mc_reg_address[SMU7_DISCRETE_MC_REGISTER_ARRAY_SIZE]; member in struct:ci_mc_reg_table
H A Diceland_smumgr.h57 SMU71_Discrete_MCRegisterAddress mc_reg_address[SMU71_DISCRETE_MC_REGISTER_ARRAY_SIZE]; member in struct:iceland_mc_reg_table
H A Dtonga_smumgr.h59 SMU72_Discrete_MCRegisterAddress mc_reg_address[SMU72_DISCRETE_MC_REGISTER_ARRAY_SIZE]; member in struct:tonga_mc_reg_table
H A Diceland_smumgr.c1700 PP_HOST_TO_SMC_US(smu_data->mc_reg_table.mc_reg_address[j].s0);
1702 PP_HOST_TO_SMC_US(smu_data->mc_reg_table.mc_reg_address[j].s1);
2474 table->mc_reg_address[i].s0 =
2475 iceland_check_s0_mc_reg_index(table->mc_reg_address[i].s1, &address)
2476 ? address : table->mc_reg_address[i].s1;
2492 ni_table->mc_reg_address[i].s1 = table->mc_reg_address[i].s1;
2521 switch (table->mc_reg_address[i].s1) {
2525 table->mc_reg_address[j].s1 = mmMC_PMG_CMD_EMRS;
2526 table->mc_reg_address[
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H A Dtonga_smumgr.c2078 PP_HOST_TO_SMC_US(smu_data->mc_reg_table.mc_reg_address[j].s0);
2080 PP_HOST_TO_SMC_US(smu_data->mc_reg_table.mc_reg_address[j].s1);
2936 table->mc_reg_address[i].s0 =
2937 tonga_check_s0_mc_reg_index(table->mc_reg_address[i].s1,
2940 table->mc_reg_address[i].s1;
2956 ni_table->mc_reg_address[i].s1 = table->mc_reg_address[i].s1;
2985 switch (table->mc_reg_address[i].s1) {
2990 table->mc_reg_address[j].s1 = mmMC_PMG_CMD_EMRS;
2991 table->mc_reg_address[
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H A Dci_smumgr.c1735 PP_HOST_TO_SMC_US(smu_data->mc_reg_table.mc_reg_address[j].s0);
1737 PP_HOST_TO_SMC_US(smu_data->mc_reg_table.mc_reg_address[j].s1);
2547 table->mc_reg_address[i].s0 =
2548 ci_check_s0_mc_reg_index(table->mc_reg_address[i].s1, &address)
2549 ? address : table->mc_reg_address[i].s1;
2565 ni_table->mc_reg_address[i].s1 = table->mc_reg_address[i].s1;
2594 switch (table->mc_reg_address[i].s1) {
2598 table->mc_reg_address[j].s1 = mmMC_PMG_CMD_EMRS;
2599 table->mc_reg_address[
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/linux-master/drivers/gpu/drm/radeon/
H A Dcypress_dpm.c959 cpu_to_be16(eg_pi->mc_reg_table.mc_reg_address[j].s0);
961 cpu_to_be16(eg_pi->mc_reg_table.mc_reg_address[j].s1);
974 eg_pi->mc_reg_table.mc_reg_address[i].s0 = MC_SEQ_RAS_TIMING_LP >> 2;
975 eg_pi->mc_reg_table.mc_reg_address[i].s1 = MC_SEQ_RAS_TIMING >> 2;
978 eg_pi->mc_reg_table.mc_reg_address[i].s0 = MC_SEQ_CAS_TIMING_LP >> 2;
979 eg_pi->mc_reg_table.mc_reg_address[i].s1 = MC_SEQ_CAS_TIMING >> 2;
982 eg_pi->mc_reg_table.mc_reg_address[i].s0 = MC_SEQ_MISC_TIMING_LP >> 2;
983 eg_pi->mc_reg_table.mc_reg_address[i].s1 = MC_SEQ_MISC_TIMING >> 2;
986 eg_pi->mc_reg_table.mc_reg_address[i].s0 = MC_SEQ_MISC_TIMING2_LP >> 2;
987 eg_pi->mc_reg_table.mc_reg_address[
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H A Dcypress_dpm.h39 SMC_Evergreen_MCRegisterAddress mc_reg_address[SMC_EVERGREEN_MC_REGISTER_ARRAY_SIZE]; member in struct:evergreen_mc_reg_table
H A Dsi_dpm.h112 SMC_NIslands_MCRegisterAddress mc_reg_address[SMC_SISLANDS_MC_REGISTER_ARRAY_SIZE]; member in struct:si_mc_reg_table
H A Dni_dpm.h57 SMC_NIslands_MCRegisterAddress mc_reg_address[SMC_NISLANDS_MC_REGISTER_ARRAY_SIZE]; member in struct:ni_mc_reg_table
H A Dci_dpm.h87 SMU7_Discrete_MCRegisterAddress mc_reg_address[SMU7_DISCRETE_MC_REGISTER_ARRAY_SIZE]; member in struct:ci_mc_reg_table
H A Dbtc_dpm.c1894 switch (table->mc_reg_address[i].s1) {
1897 table->mc_reg_address[j].s1 = MC_PMG_CMD_EMRS >> 2;
1898 table->mc_reg_address[j].s0 = MC_SEQ_PMG_CMD_EMRS_LP >> 2;
1910 table->mc_reg_address[j].s1 = MC_PMG_CMD_MRS >> 2;
1911 table->mc_reg_address[j].s0 = MC_SEQ_PMG_CMD_MRS_LP >> 2;
1926 table->mc_reg_address[j].s1 = MC_PMG_CMD_MRS1 >> 2;
1927 table->mc_reg_address[j].s0 = MC_SEQ_PMG_CMD_MRS1_LP >> 2;
1954 table->mc_reg_address[i].s0 =
1955 btc_check_s0_mc_reg_index(table->mc_reg_address[i].s1, &address) ?
1956 address : table->mc_reg_address[
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H A Dni_dpm.c2722 switch (table->mc_reg_address[i].s1) {
2727 table->mc_reg_address[j].s1 = MC_PMG_CMD_EMRS >> 2;
2728 table->mc_reg_address[j].s0 = MC_SEQ_PMG_CMD_EMRS_LP >> 2;
2738 table->mc_reg_address[j].s1 = MC_PMG_CMD_MRS >> 2;
2739 table->mc_reg_address[j].s0 = MC_SEQ_PMG_CMD_MRS_LP >> 2;
2753 table->mc_reg_address[j].s1 = MC_PMG_CMD_MRS1 >> 2;
2754 table->mc_reg_address[j].s0 = MC_SEQ_PMG_CMD_MRS1_LP >> 2;
2843 table->mc_reg_address[i].s0 =
2844 ni_check_s0_mc_reg_index(table->mc_reg_address[i].s1, &address) ?
2845 address : table->mc_reg_address[
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H A Dci_dpm.c4302 switch (table->mc_reg_address[i].s1 << 2) {
4305 table->mc_reg_address[j].s1 = MC_PMG_CMD_EMRS >> 2;
4306 table->mc_reg_address[j].s0 = MC_SEQ_PMG_CMD_EMRS_LP >> 2;
4316 table->mc_reg_address[j].s1 = MC_PMG_CMD_MRS >> 2;
4317 table->mc_reg_address[j].s0 = MC_SEQ_PMG_CMD_MRS_LP >> 2;
4329 table->mc_reg_address[j].s1 = MC_PMG_AUTO_CMD >> 2;
4330 table->mc_reg_address[j].s0 = MC_PMG_AUTO_CMD >> 2;
4342 table->mc_reg_address[j].s1 = MC_PMG_CMD_MRS1 >> 2;
4343 table->mc_reg_address[j].s0 = MC_SEQ_PMG_CMD_MRS1_LP >> 2;
4457 table->mc_reg_address[
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H A Dsi_dpm.c5302 switch (table->mc_reg_address[i].s1 << 2) {
5305 table->mc_reg_address[j].s1 = MC_PMG_CMD_EMRS >> 2;
5306 table->mc_reg_address[j].s0 = MC_SEQ_PMG_CMD_EMRS_LP >> 2;
5316 table->mc_reg_address[j].s1 = MC_PMG_CMD_MRS >> 2;
5317 table->mc_reg_address[j].s0 = MC_SEQ_PMG_CMD_MRS_LP >> 2;
5330 table->mc_reg_address[j].s1 = MC_PMG_AUTO_CMD >> 2;
5331 table->mc_reg_address[j].s0 = MC_PMG_AUTO_CMD >> 2;
5342 table->mc_reg_address[j].s1 = MC_PMG_CMD_MRS1 >> 2;
5343 table->mc_reg_address[j].s0 = MC_SEQ_PMG_CMD_MRS1_LP >> 2;
5437 table->mc_reg_address[
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H A Dradeon_mode.h629 struct atom_mc_register_address mc_reg_address[VBIOS_MC_REGISTER_ARRAY_SIZE]; member in struct:atom_mc_reg_table
H A Dradeon_atombios.c4024 reg_table->mc_reg_address[i].s1 =
4026 reg_table->mc_reg_address[i].pre_reg_data =
4042 if ((reg_table->mc_reg_address[i].pre_reg_data & LOW_NIBBLE_MASK) == DATA_FROM_TABLE) {
4046 } else if ((reg_table->mc_reg_address[i].pre_reg_data & LOW_NIBBLE_MASK) == DATA_EQU_PREV) {
/linux-master/drivers/gpu/drm/amd/amdgpu/
H A Damdgpu_atombios.h115 struct atom_mc_register_address mc_reg_address[VBIOS_MC_REGISTER_ARRAY_SIZE]; member in struct:atom_mc_reg_table
H A Damdgpu_atombios.c1464 reg_table->mc_reg_address[i].s1 =
1466 reg_table->mc_reg_address[i].pre_reg_data =
1482 if ((reg_table->mc_reg_address[i].pre_reg_data & LOW_NIBBLE_MASK) == DATA_FROM_TABLE) {
1486 } else if ((reg_table->mc_reg_address[i].pre_reg_data & LOW_NIBBLE_MASK) == DATA_EQU_PREV) {
/linux-master/drivers/gpu/drm/amd/pm/powerplay/hwmgr/
H A Dppatomctrl.h242 pp_atomctrl_mc_register_address mc_reg_address[VBIOS_MC_REGISTER_ARRAY_SIZE]; member in struct:pp_atomctrl_mc_reg_table
H A Dppatomctrl.c69 if ((table->mc_reg_address[i].uc_pre_reg_data &
74 } else if ((table->mc_reg_address[i].uc_pre_reg_data &
118 table->mc_reg_address[i].s1 =
120 table->mc_reg_address[i].uc_pre_reg_data =
/linux-master/drivers/gpu/drm/amd/pm/legacy-dpm/
H A Dsi_dpm.h279 SMC_Evergreen_MCRegisterAddress mc_reg_address[SMC_EVERGREEN_MC_REGISTER_ARRAY_SIZE]; member in struct:evergreen_mc_reg_table
632 SMC_NIslands_MCRegisterAddress mc_reg_address[SMC_NISLANDS_MC_REGISTER_ARRAY_SIZE]; member in struct:ni_mc_reg_table
940 SMC_NIslands_MCRegisterAddress mc_reg_address[SMC_SISLANDS_MC_REGISTER_ARRAY_SIZE]; member in struct:si_mc_reg_table
H A Dsi_dpm.c5844 switch (table->mc_reg_address[i].s1) {
5847 table->mc_reg_address[j].s1 = MC_PMG_CMD_EMRS;
5848 table->mc_reg_address[j].s0 = MC_SEQ_PMG_CMD_EMRS_LP;
5858 table->mc_reg_address[j].s1 = MC_PMG_CMD_MRS;
5859 table->mc_reg_address[j].s0 = MC_SEQ_PMG_CMD_MRS_LP;
5872 table->mc_reg_address[j].s1 = MC_PMG_AUTO_CMD;
5873 table->mc_reg_address[j].s0 = MC_PMG_AUTO_CMD;
5882 table->mc_reg_address[j].s1 = MC_PMG_CMD_MRS1;
5883 table->mc_reg_address[j].s0 = MC_SEQ_PMG_CMD_MRS1_LP;
5974 table->mc_reg_address[
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