Searched refs:levels (Results 1 - 25 of 116) sorted by relevance

12345

/linux-master/drivers/gpu/drm/radeon/
H A Drv730_dpm.c244 &table->ACPIState.levels[0].vddc);
245 table->ACPIState.levels[0].gen2PCIE = pi->pcie_gen2 ?
247 table->ACPIState.levels[0].gen2XSP =
251 &table->ACPIState.levels[0].vddc);
252 table->ACPIState.levels[0].gen2PCIE = 0;
294 table->ACPIState.levels[0].mclk.mclk730.vMPLL_FUNC_CNTL = cpu_to_be32(mpll_func_cntl);
295 table->ACPIState.levels[0].mclk.mclk730.vMPLL_FUNC_CNTL2 = cpu_to_be32(mpll_func_cntl_2);
296 table->ACPIState.levels[0].mclk.mclk730.vMPLL_FUNC_CNTL3 = cpu_to_be32(mpll_func_cntl_3);
297 table->ACPIState.levels[0].mclk.mclk730.vMCLK_PWRMGT_CNTL = cpu_to_be32(mclk_pwrmgt_cntl);
298 table->ACPIState.levels[
[all...]
H A Drv740_dpm.c337 &table->ACPIState.levels[0].vddc);
338 table->ACPIState.levels[0].gen2PCIE =
341 table->ACPIState.levels[0].gen2XSP =
345 &table->ACPIState.levels[0].vddc);
346 table->ACPIState.levels[0].gen2PCIE = 0;
376 table->ACPIState.levels[0].mclk.mclk770.vMPLL_AD_FUNC_CNTL = cpu_to_be32(mpll_ad_func_cntl);
377 table->ACPIState.levels[0].mclk.mclk770.vMPLL_AD_FUNC_CNTL_2 = cpu_to_be32(mpll_ad_func_cntl_2);
378 table->ACPIState.levels[0].mclk.mclk770.vMPLL_DQ_FUNC_CNTL = cpu_to_be32(mpll_dq_func_cntl);
379 table->ACPIState.levels[0].mclk.mclk770.vMPLL_DQ_FUNC_CNTL_2 = cpu_to_be32(mpll_dq_func_cntl_2);
380 table->ACPIState.levels[
[all...]
H A Dcypress_dpm.c778 &smc_state->levels[0],
785 &smc_state->levels[1],
792 &smc_state->levels[2],
797 smc_state->levels[0].arbValue = MC_CG_ARB_FREQ_F1;
798 smc_state->levels[1].arbValue = MC_CG_ARB_FREQ_F2;
799 smc_state->levels[2].arbValue = MC_CG_ARB_FREQ_F3;
802 smc_state->levels[0].ACIndex = 2;
803 smc_state->levels[1].ACIndex = 3;
804 smc_state->levels[2].ACIndex = 4;
806 smc_state->levels[
[all...]
H A Drv770_dpm.c291 smc_state->levels[i].aT = cpu_to_be32(a_t);
297 smc_state->levels[RV770_SMC_PERFORMANCE_LEVELS_PER_SWSTATE - 1].aT =
311 smc_state->levels[i].bSP = cpu_to_be32(pi->dsp);
313 smc_state->levels[RV770_SMC_PERFORMANCE_LEVELS_PER_SWSTATE - 1].bSP =
687 &smc_state->levels[0],
694 &smc_state->levels[1],
701 &smc_state->levels[2],
706 smc_state->levels[0].arbValue = MC_CG_ARB_FREQ_F1;
707 smc_state->levels[1].arbValue = MC_CG_ARB_FREQ_F2;
708 smc_state->levels[
[all...]
H A Dsumo_dpm.c345 u32 highest_engine_clock = ps->levels[ps->num_levels - 1].sclk;
409 m_a = asi * ps->levels[i].sclk / 100;
668 pi->boost_pl = new_ps->levels[new_ps->num_levels - 1];
760 sumo_program_power_level(rdev, &new_ps->levels[i], i);
842 if (new_ps->levels[new_ps->num_levels - 1].sclk >=
843 current_ps->levels[current_ps->num_levels - 1].sclk)
860 if (new_ps->levels[new_ps->num_levels - 1].sclk <
861 current_ps->levels[current_ps->num_levels - 1].sclk)
1051 current_vddc = current_ps->levels[current_index].vddc_index;
1052 current_sclk = current_ps->levels[current_inde
[all...]
H A Dtrinity_dpm.c801 trinity_program_power_level(rdev, &new_ps->levels[i], i);
921 if (new_ps->levels[new_ps->num_levels - 1].sclk >=
922 current_ps->levels[current_ps->num_levels - 1].sclk)
935 if (new_ps->levels[new_ps->num_levels - 1].sclk <
936 current_ps->levels[current_ps->num_levels - 1].sclk)
1283 ps->levels[0] = pi->boot_pl;
1306 pi->current_ps.levels[0] = pi->boot_pl;
1361 current_vddc = current_ps->levels[current_index].vddc_index;
1362 current_sclk = current_ps->levels[current_index].sclk;
1368 ps->levels[
[all...]
/linux-master/drivers/gpu/drm/nouveau/nvkm/subdev/mmu/
H A Dr535.c71 ctrl->levels[0].physAddress = vmm->pd->pt[0]->addr;
72 ctrl->levels[0].size = 0x20;
73 ctrl->levels[0].aperture = 1;
74 ctrl->levels[0].pageShift = 0x2f;
75 ctrl->levels[1].physAddress = vmm->pd->pde[0]->pt[0]->addr;
76 ctrl->levels[1].size = 0x1000;
77 ctrl->levels[1].aperture = 1;
78 ctrl->levels[1].pageShift = 0x26;
80 ctrl->levels[2].physAddress = vmm->pd->pde[0]->pde[0]->pt[0]->addr;
81 ctrl->levels[
[all...]
/linux-master/arch/arc/include/asm/
H A Dpgtable.h11 #include <asm/pgtable-levels.h>
/linux-master/include/linux/
H A Dpwm_backlight.h15 unsigned int *levels; member in struct:platform_pwm_backlight_data
H A Dcacheinfo.h104 unsigned int *levels, unsigned int *split_levels)
110 unsigned int *levels, unsigned int *split_levels);
103 acpi_get_cache_info(unsigned int cpu, unsigned int *levels, unsigned int *split_levels) argument
/linux-master/arch/mips/kernel/
H A Dcacheinfo.c24 int levels = 0, leaves = 0; local
31 levels += 1;
39 levels++;
44 levels++;
49 levels++;
53 this_cpu_ci->num_levels = levels;
/linux-master/drivers/gpu/drm/nouveau/include/nvrm/535.113.01/common/sdk/nvidia/inc/ctrl/
H A Dctrl90f1.h65 * [in] Number of PDE levels to copy.
92 } levels[GMMU_FMT_MAX_LEVELS]; member in struct:NV90F1_CTRL_VASPACE_COPY_SERVER_RESERVED_PDES_PARAMS
/linux-master/arch/powerpc/platforms/powernv/
H A Dpci-ioda-tce.c81 unsigned long size, unsigned int levels);
217 unsigned long size, unsigned int levels)
222 if (levels) {
233 levels - 1);
257 unsigned int levels, unsigned long limit,
268 --levels;
269 if (!levels) {
276 levels, limit, current_offset, total_allocated);
291 __u32 page_shift, __u64 window_size, __u32 levels,
303 if (!levels || (level
216 pnv_pci_ioda2_table_do_free_pages(__be64 *addr, unsigned long size, unsigned int levels) argument
256 pnv_pci_ioda2_table_do_alloc_pages(int nid, unsigned int shift, unsigned int levels, unsigned long limit, unsigned long *current_offset, unsigned long *total_allocated) argument
290 pnv_pci_ioda2_table_alloc_pages(int nid, __u64 bus_offset, __u32 page_shift, __u64 window_size, __u32 levels, bool alloc_userspace_copy, struct iommu_table *tbl) argument
[all...]
/linux-master/drivers/video/backlight/
H A Dled_bl.c20 unsigned int *levels; member in struct:led_bl_data
30 if (priv->levels)
31 bkl_brightness = priv->levels[level];
134 num_levels = of_property_count_u32_elems(node, "brightness-levels");
138 u32 *levels = NULL; local
140 levels = devm_kzalloc(dev, sizeof(u32) * num_levels,
142 if (!levels)
145 ret = of_property_read_u32_array(node, "brightness-levels",
146 levels,
157 if ((i && db > levels[
[all...]
H A Dpwm_bl.c26 unsigned int *levels; member in struct:pwm_bl_data
82 if (pb->levels)
83 duty_cycle = pb->levels[brightness];
201 * Once we have 4096 levels there's little point going much higher...
208 data->levels = devm_kcalloc(dev, data->max_brightness,
209 sizeof(*data->levels), GFP_KERNEL);
210 if (!data->levels)
220 data->levels[i] = (unsigned int)retval;
255 * Determine the number of brightness levels, if this property is not
256 * set a default table of brightness levels wil
[all...]
H A Dmp3309c.c63 unsigned int *levels; member in struct:mp3309c_platform_data
133 chip->pdata->levels[brightness],
134 chip->pdata->levels[chip->pdata->max_brightness]);
233 * In I2C control mode the dimming levels (0..31) are fixed by the
240 * levels
253 if (device_property_present(dev, "brightness-levels")) {
254 /* Read brightness levels from DT */
255 num_levels = device_property_count_u32(dev, "brightness-levels");
259 /* Use default brightness levels */
264 /* Fill brightness levels arra
[all...]
/linux-master/arch/riscv/kernel/
H A Dcacheinfo.c80 int levels = 1, level = 1; local
97 if (level <= levels)
105 levels = level;
/linux-master/drivers/acpi/
H A Dacpi_video.c84 * the rest are all supported levels.
91 ACPI_VIDEO_FIRST_LEVEL, /* actual supported levels begin here */
186 u8 _BCL:1; /* Query list of brightness control levels supported */
231 if (vd->brightness->levels[i] == cur_level)
244 vd->brightness->levels[request_level]);
273 if (level == video->brightness->levels[offset]) {
291 level = video->brightness->levels[state - 1];
309 union acpi_object **levels)
316 *levels = NULL;
328 *levels
308 acpi_video_device_lcd_query_levels(acpi_handle handle, union acpi_object **levels) argument
1779 union acpi_object *levels; local
[all...]
H A Dpptt.c84 * @split_levels: Number of split cache levels (data/instruction).
91 * of cache levels for the cache node.
94 * down each level of caches, counting how many levels are found
181 * levels and split cache levels (data/instruction).
184 * @levels: Number of levels if success.
185 * @split_levels: Number of split cache levels (data/instruction) if
189 * how many levels exist solely for it, and then walk up each level until we hit
191 * caches that exist across packages). Count the number of cache levels an
195 acpi_count_levels(struct acpi_table_header *table_hdr, struct acpi_pptt_processor *cpu_node, unsigned int *levels, unsigned int *split_levels) argument
621 acpi_get_cache_info(unsigned int cpu, unsigned int *levels, unsigned int *split_levels) argument
[all...]
/linux-master/arch/arm64/mm/
H A Dtrans_pgd.c239 unsigned long level_mask, prev_level_entry, *levels[4]; local
246 levels[this_level] = trans_alloc(info);
247 if (!levels[this_level])
255 *(levels[this_level] + index) = prev_level_entry;
257 pfn = virt_to_pfn(levels[this_level]);
/linux-master/drivers/thermal/intel/int340x_thermal/
H A Dint3406_thermal.c60 acpi_level = d->br->levels[d->upper_limit - state];
83 if (acpi_level <= d->br->levels[index])
115 d->lower_limit = int3406_thermal_get_index(d->br->levels,
120 d->upper_limit = int3406_thermal_get_index(d->br->levels,
/linux-master/include/acpi/
H A Dvideo.h9 u8 _BCL_no_ac_battery_levels:1; /* no AC/Battery levels in _BCL */
17 int *levels; member in struct:acpi_video_device_brightness
/linux-master/tools/power/x86/intel-speed-select/
H A Disst-core.c199 isst_display_error_info_message(1, "Failed to get number of levels", 0, 0);
203 if (level > pkg_dev.levels) {
239 isst_display_error_info_message(1, "Failed to get number of levels", 0, 0);
243 if (level > pkg_dev.levels) {
344 for (i = 0; i < pkg_dev->levels; ++i) {
372 debug_printf("cpu: %d ctdp enable:%d current level: %d levels:%d\n",
374 pkg_dev->levels);
376 if (tdp_level != 0xff && tdp_level > pkg_dev->levels) {
384 for (i = 0; i <= pkg_dev->levels; ++i) {
458 isst_display_error_info_message(0, "Invalid level, Can't get TDP control information at specified levels o
[all...]
/linux-master/drivers/xen/xenbus/
H A Dxenbus.h43 unsigned int levels; member in struct:xen_bus_type
/linux-master/arch/arm64/include/asm/
H A Dkvm_arm.h210 #define VTCR_EL2_LVLS_TO_SL0(levels) \
211 ((VTCR_EL2_TGRAN_SL0_BASE - (4 - (levels))) << VTCR_EL2_SL0_SHIFT)
233 * intermediate levels must be always aligned to the PAGE_SIZE (i.e,
245 * | Level: 0 (4 levels) | 28 | - | - |
247 * | Level: 1 (3 levels) | 37 | 31 | 25 |
249 * | Level: 2 (2 levels) | 46 | 42 | 38 |
264 * = IPA_SHIFT - ((PAGE_SHIFT - 3) * Number of levels)
275 * where n = number of levels, and since each pointer is 8bytes, we have:
281 * levels for a given IPA size (which we do, see stage2_pt_levels())
283 #define ARM64_VTTBR_X(ipa, levels) ((ip
[all...]

Completed in 259 milliseconds

12345