drm/radeon/sumo_dpm.c

345 	u32 highest_engine_clock = ps->levels[ps->num_levels - 1].sclk;
409 		m_a = asi * ps->levels[i].sclk / 100;
668 		pi->boost_pl = new_ps->levels[new_ps->num_levels - 1];
760 		sumo_program_power_level(rdev, &new_ps->levels[i], i);
842 	if (new_ps->levels[new_ps->num_levels - 1].sclk >=
843 	    current_ps->levels[current_ps->num_levels - 1].sclk)
860 	if (new_ps->levels[new_ps->num_levels - 1].sclk <
861 	    current_ps->levels[current_ps->num_levels - 1].sclk)
1051 		current_vddc = current_ps->levels[current_index].vddc_index;
1052 		current_sclk = current_ps->levels[current_index].sclk;
1058 	ps->levels[0].vddc_index = current_vddc;
1060 	if (ps->levels[0].sclk > current_sclk)
1061 		ps->levels[0].sclk = current_sclk;
1063 	ps->levels[0].ss_divider_index =
1064 		sumo_get_sleep_divider_id_from_clock(rdev, ps->levels[0].sclk, sclk_in_sr);
1066 	ps->levels[0].ds_divider_index =
1067 		sumo_get_sleep_divider_id_from_clock(rdev, ps->levels[0].sclk, SUMO_MINIMUM_ENGINE_CLOCK);
1069 	if (ps->levels[0].ds_divider_index > ps->levels[0].ss_divider_index + 1)
1070 		ps->levels[0].ds_divider_index = ps->levels[0].ss_divider_index + 1;
1072 	if (ps->levels[0].ss_divider_index == ps->levels[0].ds_divider_index) {
1073 		if (ps->levels[0].ss_divider_index > 1)
1074 			ps->levels[0].ss_divider_index = ps->levels[0].ss_divider_index - 1;
1077 	if (ps->levels[0].ss_divider_index == 0)
1078 		ps->levels[0].ds_divider_index = 0;
1080 	if (ps->levels[0].ds_divider_index == 0)
1081 		ps->levels[0].ss_divider_index = 0;
1110 		if (ps->levels[i].vddc_index < min_voltage)
1111 			ps->levels[i].vddc_index = min_voltage;
1113 		if (ps->levels[i].sclk < min_sclk)
1114 			ps->levels[i].sclk =
1117 		ps->levels[i].ss_divider_index =
1118 			sumo_get_sleep_divider_id_from_clock(rdev, ps->levels[i].sclk, sclk_in_sr);
1120 		ps->levels[i].ds_divider_index =
1121 			sumo_get_sleep_divider_id_from_clock(rdev, ps->levels[i].sclk, SUMO_MINIMUM_ENGINE_CLOCK);
1123 		if (ps->levels[i].ds_divider_index > ps->levels[i].ss_divider_index + 1)
1124 			ps->levels[i].ds_divider_index = ps->levels[i].ss_divider_index + 1;
1126 		if (ps->levels[i].ss_divider_index == ps->levels[i].ds_divider_index) {
1127 			if (ps->levels[i].ss_divider_index > 1)
1128 				ps->levels[i].ss_divider_index = ps->levels[i].ss_divider_index - 1;
1131 		if (ps->levels[i].ss_divider_index == 0)
1132 			ps->levels[i].ds_divider_index = 0;
1134 		if (ps->levels[i].ds_divider_index == 0)
1135 			ps->levels[i].ss_divider_index = 0;
1138 			ps->levels[i].allow_gnb_slow = 1;
1141 			ps->levels[i].allow_gnb_slow = 0;
1143 			ps->levels[i].allow_gnb_slow = 0;
1145 			ps->levels[i].allow_gnb_slow = 1;
1397 	ps->levels[0] = pi->boot_pl;
1433 	struct sumo_pl *pl = &ps->levels[index];
1737 	pi->current_ps.levels[0] = pi->boot_pl;
1804 		struct sumo_pl *pl = &ps->levels[i];
1832 		pl = &ps->levels[current_index];
1856 		pl = &ps->levels[current_index];
1883 		pl = &ps->levels[current_index];
1907 		return requested_state->levels[0].sclk;
1909 		return requested_state->levels[requested_state->num_levels - 1].sclk;