Lines Matching refs:levels

291 		smc_state->levels[i].aT = cpu_to_be32(a_t);
297 smc_state->levels[RV770_SMC_PERFORMANCE_LEVELS_PER_SWSTATE - 1].aT =
311 smc_state->levels[i].bSP = cpu_to_be32(pi->dsp);
313 smc_state->levels[RV770_SMC_PERFORMANCE_LEVELS_PER_SWSTATE - 1].bSP =
687 &smc_state->levels[0],
694 &smc_state->levels[1],
701 &smc_state->levels[2],
706 smc_state->levels[0].arbValue = MC_CG_ARB_FREQ_F1;
707 smc_state->levels[1].arbValue = MC_CG_ARB_FREQ_F2;
708 smc_state->levels[2].arbValue = MC_CG_ARB_FREQ_F3;
710 smc_state->levels[0].seqValue = rv770_get_seq_value(rdev,
712 smc_state->levels[1].seqValue = rv770_get_seq_value(rdev,
714 smc_state->levels[2].seqValue = rv770_get_seq_value(rdev,
944 &table->ACPIState.levels[0].vddc);
947 table->ACPIState.levels[0].gen2PCIE = 1;
949 table->ACPIState.levels[0].gen2PCIE = 0;
951 table->ACPIState.levels[0].gen2PCIE = 0;
953 table->ACPIState.levels[0].gen2XSP = 1;
955 table->ACPIState.levels[0].gen2XSP = 0;
958 &table->ACPIState.levels[0].vddc);
959 table->ACPIState.levels[0].gen2PCIE = 0;
983 table->ACPIState.levels[0].mclk.mclk770.vMPLL_AD_FUNC_CNTL = cpu_to_be32(mpll_ad_func_cntl);
984 table->ACPIState.levels[0].mclk.mclk770.vMPLL_AD_FUNC_CNTL_2 = cpu_to_be32(mpll_ad_func_cntl_2);
985 table->ACPIState.levels[0].mclk.mclk770.vMPLL_DQ_FUNC_CNTL = cpu_to_be32(mpll_dq_func_cntl);
986 table->ACPIState.levels[0].mclk.mclk770.vMPLL_DQ_FUNC_CNTL_2 = cpu_to_be32(mpll_dq_func_cntl_2);
988 table->ACPIState.levels[0].mclk.mclk770.vMCLK_PWRMGT_CNTL = cpu_to_be32(mclk_pwrmgt_cntl);
989 table->ACPIState.levels[0].mclk.mclk770.vDLL_CNTL = cpu_to_be32(dll_cntl);
991 table->ACPIState.levels[0].mclk.mclk770.mclk_value = 0;
993 table->ACPIState.levels[0].sclk.vCG_SPLL_FUNC_CNTL = cpu_to_be32(spll_func_cntl);
994 table->ACPIState.levels[0].sclk.vCG_SPLL_FUNC_CNTL_2 = cpu_to_be32(spll_func_cntl_2);
995 table->ACPIState.levels[0].sclk.vCG_SPLL_FUNC_CNTL_3 = cpu_to_be32(spll_func_cntl_3);
997 table->ACPIState.levels[0].sclk.sclk_value = 0;
999 rv770_populate_mvdd_value(rdev, 0, &table->ACPIState.levels[0].mvdd);
1001 table->ACPIState.levels[1] = table->ACPIState.levels[0];
1002 table->ACPIState.levels[2] = table->ACPIState.levels[0];
1032 table->initialState.levels[0].mclk.mclk770.vMPLL_AD_FUNC_CNTL =
1034 table->initialState.levels[0].mclk.mclk770.vMPLL_AD_FUNC_CNTL_2 =
1036 table->initialState.levels[0].mclk.mclk770.vMPLL_DQ_FUNC_CNTL =
1038 table->initialState.levels[0].mclk.mclk770.vMPLL_DQ_FUNC_CNTL_2 =
1040 table->initialState.levels[0].mclk.mclk770.vMCLK_PWRMGT_CNTL =
1042 table->initialState.levels[0].mclk.mclk770.vDLL_CNTL =
1045 table->initialState.levels[0].mclk.mclk770.vMPLL_SS =
1047 table->initialState.levels[0].mclk.mclk770.vMPLL_SS2 =
1050 table->initialState.levels[0].mclk.mclk770.mclk_value =
1053 table->initialState.levels[0].sclk.vCG_SPLL_FUNC_CNTL =
1055 table->initialState.levels[0].sclk.vCG_SPLL_FUNC_CNTL_2 =
1057 table->initialState.levels[0].sclk.vCG_SPLL_FUNC_CNTL_3 =
1059 table->initialState.levels[0].sclk.vCG_SPLL_SPREAD_SPECTRUM =
1061 table->initialState.levels[0].sclk.vCG_SPLL_SPREAD_SPECTRUM_2 =
1064 table->initialState.levels[0].sclk.sclk_value =
1067 table->initialState.levels[0].arbValue = MC_CG_ARB_FREQ_F0;
1069 table->initialState.levels[0].seqValue =
1074 &table->initialState.levels[0].vddc);
1076 &table->initialState.levels[0].mvdd);
1079 table->initialState.levels[0].aT = cpu_to_be32(a_t);
1081 table->initialState.levels[0].bSP = cpu_to_be32(pi->dsp);
1084 table->initialState.levels[0].gen2PCIE = 1;
1086 table->initialState.levels[0].gen2PCIE = 0;
1088 table->initialState.levels[0].gen2XSP = 1;
1090 table->initialState.levels[0].gen2XSP = 0;
1095 table->initialState.levels[0].strobeMode =
1098 table->initialState.levels[0].strobeMode = 0;
1101 table->initialState.levels[0].mcFlags = SMC_MC_EDC_RD_FLAG | SMC_MC_EDC_WR_FLAG;
1103 table->initialState.levels[0].mcFlags = 0;
1107 table->initialState.levels[1] = table->initialState.levels[0];
1108 table->initialState.levels[2] = table->initialState.levels[0];