/linux-master/drivers/net/ethernet/altera/ |
H A D | altera_utils.c | 9 void tse_set_bit(void __iomem *ioaddr, size_t offs, u32 bit_mask) argument 11 u32 value = csrrd32(ioaddr, offs); 13 csrwr32(value, ioaddr, offs); 16 void tse_clear_bit(void __iomem *ioaddr, size_t offs, u32 bit_mask) argument 18 u32 value = csrrd32(ioaddr, offs); 20 csrwr32(value, ioaddr, offs); 23 int tse_bit_is_set(void __iomem *ioaddr, size_t offs, u32 bit_mask) argument 25 u32 value = csrrd32(ioaddr, offs); 29 int tse_bit_is_clear(void __iomem *ioaddr, size_t offs, u32 bit_mask) argument 31 u32 value = csrrd32(ioaddr, off [all...] |
H A D | altera_utils.h | 12 void tse_set_bit(void __iomem *ioaddr, size_t offs, u32 bit_mask); 13 void tse_clear_bit(void __iomem *ioaddr, size_t offs, u32 bit_mask); 14 int tse_bit_is_set(void __iomem *ioaddr, size_t offs, u32 bit_mask); 15 int tse_bit_is_clear(void __iomem *ioaddr, size_t offs, u32 bit_mask);
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/linux-master/drivers/net/ethernet/samsung/sxgbe/ |
H A D | sxgbe_dma.h | 22 int (*init)(void __iomem *ioaddr, int fix_burst, int burst_map); 23 void (*cha_init)(void __iomem *ioaddr, int cha_num, int fix_burst, 26 void (*enable_dma_transmission)(void __iomem *ioaddr, int dma_cnum); 27 void (*enable_dma_irq)(void __iomem *ioaddr, int dma_cnum); 28 void (*disable_dma_irq)(void __iomem *ioaddr, int dma_cnum); 29 void (*start_tx)(void __iomem *ioaddr, int tchannels); 30 void (*start_tx_queue)(void __iomem *ioaddr, int dma_cnum); 31 void (*stop_tx)(void __iomem *ioaddr, int tchannels); 32 void (*stop_tx_queue)(void __iomem *ioaddr, int dma_cnum); 33 void (*start_rx)(void __iomem *ioaddr, in [all...] |
H A D | sxgbe_core.c | 21 static void sxgbe_core_init(void __iomem *ioaddr) argument 26 regval = readl(ioaddr + SXGBE_CORE_TX_CONFIG_REG); 31 writel(regval, ioaddr + SXGBE_CORE_TX_CONFIG_REG); 34 regval = readl(ioaddr + SXGBE_CORE_RX_CONFIG_REG); 40 writel(regval, ioaddr + SXGBE_CORE_RX_CONFIG_REG); 44 static void sxgbe_core_dump_regs(void __iomem *ioaddr) argument 48 static int sxgbe_get_lpi_status(void __iomem *ioaddr, const u32 irq_status) argument 54 lpi_status = readl(ioaddr + SXGBE_CORE_LPI_CTRL_STATUS); 69 static int sxgbe_core_host_irq_status(void __iomem *ioaddr, argument 74 irq_status = readl(ioaddr 83 sxgbe_core_pmt(void __iomem *ioaddr, unsigned long mode) argument 88 sxgbe_core_set_umac_addr(void __iomem *ioaddr, const unsigned char *addr, unsigned int reg_n) argument 101 sxgbe_core_get_umac_addr(void __iomem *ioaddr, unsigned char *addr, unsigned int reg_n) argument 118 sxgbe_enable_tx(void __iomem *ioaddr, bool enable) argument 130 sxgbe_enable_rx(void __iomem *ioaddr, bool enable) argument 142 sxgbe_get_controller_version(void __iomem *ioaddr) argument 148 sxgbe_get_hw_feature(void __iomem *ioaddr, unsigned char feature_index) argument 154 sxgbe_core_set_speed(void __iomem *ioaddr, unsigned char speed) argument 166 sxgbe_core_enable_rxqueue(void __iomem *ioaddr, int queue_num) argument 176 sxgbe_core_disable_rxqueue(void __iomem *ioaddr, int queue_num) argument 186 sxgbe_set_eee_mode(void __iomem *ioaddr) argument 200 sxgbe_reset_eee_mode(void __iomem *ioaddr) argument 209 sxgbe_set_eee_pls(void __iomem *ioaddr, const int link) argument 224 sxgbe_set_eee_timer(void __iomem *ioaddr, const int ls, const int tw) argument 239 sxgbe_enable_rx_csum(void __iomem *ioaddr) argument 248 sxgbe_disable_rx_csum(void __iomem *ioaddr) argument [all...] |
H A D | sxgbe_mtl.c | 20 static void sxgbe_mtl_init(void __iomem *ioaddr, unsigned int etsalg, argument 25 reg_val = readl(ioaddr + SXGBE_MTL_OP_MODE_REG); 40 writel(reg_val, ioaddr + SXGBE_MTL_OP_MODE_REG); 50 writel(reg_val, ioaddr + SXGBE_MTL_OP_MODE_REG); 54 static void sxgbe_mtl_dma_dm_rxqueue(void __iomem *ioaddr) argument 56 writel(RX_QUEUE_DYNAMIC, ioaddr + SXGBE_MTL_RXQ_DMAMAP0_REG); 57 writel(RX_QUEUE_DYNAMIC, ioaddr + SXGBE_MTL_RXQ_DMAMAP1_REG); 58 writel(RX_QUEUE_DYNAMIC, ioaddr + SXGBE_MTL_RXQ_DMAMAP2_REG); 61 static void sxgbe_mtl_set_txfifosize(void __iomem *ioaddr, int queue_num, argument 68 reg_val = readl(ioaddr 73 sxgbe_mtl_set_rxfifosize(void __iomem *ioaddr, int queue_num, int queue_fifo) argument 85 sxgbe_mtl_enable_txqueue(void __iomem *ioaddr, int queue_num) argument 94 sxgbe_mtl_disable_txqueue(void __iomem *ioaddr, int queue_num) argument 103 sxgbe_mtl_fc_active(void __iomem *ioaddr, int queue_num, int threshold) argument 115 sxgbe_mtl_fc_enable(void __iomem *ioaddr, int queue_num) argument 124 sxgbe_mtl_fc_deactive(void __iomem *ioaddr, int queue_num, int threshold) argument 136 sxgbe_mtl_fep_enable(void __iomem *ioaddr, int queue_num) argument 146 sxgbe_mtl_fep_disable(void __iomem *ioaddr, int queue_num) argument 156 sxgbe_mtl_fup_enable(void __iomem *ioaddr, int queue_num) argument 166 sxgbe_mtl_fup_disable(void __iomem *ioaddr, int queue_num) argument 177 sxgbe_set_tx_mtl_mode(void __iomem *ioaddr, int queue_num, int tx_mode) argument 208 sxgbe_set_rx_mtl_mode(void __iomem *ioaddr, int queue_num, int rx_mode) argument [all...] |
H A D | sxgbe_mtl.h | 61 void (*mtl_init)(void __iomem *ioaddr, unsigned int etsalg, 64 void (*mtl_set_txfifosize)(void __iomem *ioaddr, int queue_num, 67 void (*mtl_set_rxfifosize)(void __iomem *ioaddr, int queue_num, 70 void (*mtl_enable_txqueue)(void __iomem *ioaddr, int queue_num); 72 void (*mtl_disable_txqueue)(void __iomem *ioaddr, int queue_num); 74 void (*set_tx_mtl_mode)(void __iomem *ioaddr, int queue_num, 77 void (*set_rx_mtl_mode)(void __iomem *ioaddr, int queue_num, 80 void (*mtl_dynamic_dma_rxqueue)(void __iomem *ioaddr); 82 void (*mtl_fc_active)(void __iomem *ioaddr, int queue_num, 85 void (*mtl_fc_deactive)(void __iomem *ioaddr, in [all...] |
H A D | sxgbe_dma.c | 21 static int sxgbe_dma_init(void __iomem *ioaddr, int fix_burst, int burst_map) argument 25 reg_val = readl(ioaddr + SXGBE_DMA_SYSBUS_MODE_REG); 38 writel(reg_val, ioaddr + SXGBE_DMA_SYSBUS_MODE_REG); 43 static void sxgbe_dma_channel_init(void __iomem *ioaddr, int cha_num, argument 50 reg_val = readl(ioaddr + SXGBE_DMA_CHA_CTL_REG(cha_num)); 54 writel(reg_val, ioaddr + SXGBE_DMA_CHA_CTL_REG(cha_num)); 56 reg_val = readl(ioaddr + SXGBE_DMA_CHA_TXCTL_REG(cha_num)); 58 writel(reg_val, ioaddr + SXGBE_DMA_CHA_TXCTL_REG(cha_num)); 60 reg_val = readl(ioaddr + SXGBE_DMA_CHA_RXCTL_REG(cha_num)); 62 writel(reg_val, ioaddr 96 sxgbe_enable_dma_transmission(void __iomem *ioaddr, int cha_num) argument 105 sxgbe_enable_dma_irq(void __iomem *ioaddr, int dma_cnum) argument 112 sxgbe_disable_dma_irq(void __iomem *ioaddr, int dma_cnum) argument 118 sxgbe_dma_start_tx(void __iomem *ioaddr, int tchannels) argument 131 sxgbe_dma_start_tx_queue(void __iomem *ioaddr, int dma_cnum) argument 140 sxgbe_dma_stop_tx_queue(void __iomem *ioaddr, int dma_cnum) argument 149 sxgbe_dma_stop_tx(void __iomem *ioaddr, int tchannels) argument 161 sxgbe_dma_start_rx(void __iomem *ioaddr, int rchannels) argument 174 sxgbe_dma_stop_rx(void __iomem *ioaddr, int rchannels) argument 186 sxgbe_tx_dma_int_status(void __iomem *ioaddr, int channel_no, struct sxgbe_extra_stats *x) argument 258 sxgbe_rx_dma_int_status(void __iomem *ioaddr, int channel_no, struct sxgbe_extra_stats *x) argument 325 sxgbe_dma_rx_watchdog(void __iomem *ioaddr, u32 riwt) argument 335 sxgbe_enable_tso(void __iomem *ioaddr, u8 chan_num) argument [all...] |
/linux-master/drivers/vfio/platform/reset/ |
H A D | vfio_platform_amdxgbe.c | 27 static unsigned int xmdio_read(void __iomem *ioaddr, unsigned int mmd, argument 33 iowrite32(mmd_address >> 8, ioaddr + (PCS_MMD_SELECT << 2)); 34 value = ioread32(ioaddr + ((mmd_address & 0xff) << 2)); 38 static void xmdio_write(void __iomem *ioaddr, unsigned int mmd, argument 44 iowrite32(mmd_address >> 8, ioaddr + (PCS_MMD_SELECT << 2)); 45 iowrite32(value, ioaddr + ((mmd_address & 0xff) << 2)); 55 if (!xgmac_regs->ioaddr) { 56 xgmac_regs->ioaddr = 58 if (!xgmac_regs->ioaddr) 61 if (!xpcs_regs->ioaddr) { [all...] |
H A D | vfio_platform_calxedaxgmac.c | 37 static inline void xgmac_mac_disable(void __iomem *ioaddr) argument 39 u32 value = readl(ioaddr + XGMAC_DMA_CONTROL); 42 writel(value, ioaddr + XGMAC_DMA_CONTROL); 44 value = readl(ioaddr + XGMAC_CONTROL); 46 writel(value, ioaddr + XGMAC_CONTROL); 53 if (!reg->ioaddr) { 54 reg->ioaddr = 56 if (!reg->ioaddr) 61 writel(0, reg->ioaddr + XGMAC_DMA_INTR_ENA); 64 xgmac_mac_disable(reg->ioaddr); [all...] |
/linux-master/drivers/net/ |
H A D | sb1000.c | 90 static int card_wait_for_busy_clear(const int ioaddr[], 92 static int card_wait_for_ready(const int ioaddr[], const char* name, 94 static int card_send_command(const int ioaddr[], const char* name, 98 static int sb1000_wait_for_ready(const int ioaddr[], const char* name); 99 static int sb1000_wait_for_ready_clear(const int ioaddr[], 101 static void sb1000_send_command(const int ioaddr[], const char* name, 103 static void sb1000_read_status(const int ioaddr[], unsigned char in[]); 104 static void sb1000_issue_read_command(const int ioaddr[], 108 static int sb1000_reset(const int ioaddr[], const char* name); 109 static int sb1000_check_CRC(const int ioaddr[], cons 149 unsigned short ioaddr[2], irq; local 262 card_wait_for_busy_clear(const int ioaddr[], const char* name) argument 286 card_wait_for_ready(const int ioaddr[], const char* name, unsigned char in[]) argument 317 card_send_command(const int ioaddr[], const char* name, const unsigned char out[], unsigned char in[]) argument 364 sb1000_wait_for_ready(const int ioaddr[], const char* name) argument 390 sb1000_wait_for_ready_clear(const int ioaddr[], const char* name) argument 415 sb1000_send_command(const int ioaddr[], const char* name, const unsigned char out[]) argument 431 sb1000_read_status(const int ioaddr[], unsigned char in[]) argument 442 sb1000_issue_read_command(const int ioaddr[], const char* name) argument 457 sb1000_reset(const int ioaddr[], const char* name) argument 487 sb1000_check_CRC(const int ioaddr[], const char* name) argument 503 sb1000_start_get_set_command(const int ioaddr[], const char* name) argument 513 sb1000_end_get_set_command(const int ioaddr[], const char* name) argument 527 sb1000_activate(const int ioaddr[], const char* name) argument 554 sb1000_get_firmware_version(const int ioaddr[], const char* name, unsigned char version[], int do_end) argument 578 sb1000_get_frequency(const int ioaddr[], const char* name, int* frequency) argument 596 sb1000_set_frequency(const int ioaddr[], const char* name, int frequency) argument 626 sb1000_get_PIDs(const int ioaddr[], const char* name, short PID[]) argument 661 sb1000_set_PIDs(const int ioaddr[], const char* name, const short PID[]) argument 748 int ioaddr, ns; local 910 int ioaddr[2]; local 935 int ioaddr[2], status; local 1001 int ioaddr[2], status, frequency; local 1098 int ioaddr[2]; local 1149 int ioaddr[2]; local [all...] |
/linux-master/drivers/net/arcnet/ |
H A D | com90io.c | 73 int ioaddr = dev->base_addr; local 75 arcnet_outb(offset >> 8, ioaddr, COM9026_REG_W_ADDR_HI); 76 arcnet_outb(offset & 0xff, ioaddr, COM9026_REG_W_ADDR_LO); 78 return arcnet_inb(ioaddr, COM9026_REG_RW_MEMDATA); 85 int ioaddr = dev->base_addr; local 87 arcnet_outb(offset >> 8, ioaddr, COM9026_REG_W_ADDR_HI); 88 arcnet_outb(offset & 0xff, ioaddr, COM9026_REG_W_ADDR_LO); 90 arcnet_outb(datum, ioaddr, COM9026_REG_RW_MEMDATA); 98 int ioaddr = dev->base_addr; local 100 arcnet_outb((offset >> 8) | AUTOINCflag, ioaddr, COM9026_REG_W_ADDR_H 114 int ioaddr = dev->base_addr; local 132 int ioaddr = dev->base_addr, status; local 224 int ioaddr = dev->base_addr; local 282 short ioaddr = dev->base_addr; local 313 short ioaddr = dev->base_addr; local 320 short ioaddr = dev->base_addr; local 327 short ioaddr = dev->base_addr; local 411 int ioaddr = dev->base_addr; local [all...] |
H A D | com20020.c | 65 int ioaddr = dev->base_addr, ofs = 512 * bufnum + offset; local 69 ioaddr, COM20020_REG_W_ADDR_HI); 70 arcnet_outb(ofs & 0xff, ioaddr, COM20020_REG_W_ADDR_LO); 74 arcnet_insb(ioaddr, COM20020_REG_RW_MEMDATA, buf, count)); 80 int ioaddr = dev->base_addr, ofs = 512 * bufnum + offset; local 83 arcnet_outb((ofs >> 8) | AUTOINCflag, ioaddr, COM20020_REG_W_ADDR_HI); 84 arcnet_outb(ofs & 0xff, ioaddr, COM20020_REG_W_ADDR_LO); 88 arcnet_outsb(ioaddr, COM20020_REG_RW_MEMDATA, buf, count)); 94 int ioaddr = dev->base_addr, status; local 97 arcnet_outb(XTOcfg(3) | RESETcfg, ioaddr, COM20020_REG_W_CONFI 156 int ioaddr = dev->base_addr; local 169 int ioaddr = dev->base_addr; local 180 int ioaddr = dev->base_addr; local 206 int ioaddr = dev->base_addr; local 285 u_int ioaddr = dev->base_addr; local 334 u_int ioaddr = dev->base_addr; local 342 u_int ioaddr = dev->base_addr; local 349 u_int ioaddr = dev->base_addr; local 358 int ioaddr = dev->base_addr; local 375 int ioaddr = dev->base_addr; local [all...] |
/linux-master/drivers/net/ethernet/stmicro/stmmac/ |
H A D | dwxgmac2_dma.c | 11 static int dwxgmac2_dma_reset(void __iomem *ioaddr) argument 13 u32 value = readl(ioaddr + XGMAC_DMA_MODE); 16 writel(value | XGMAC_SWR, ioaddr + XGMAC_DMA_MODE); 18 return readl_poll_timeout(ioaddr + XGMAC_DMA_MODE, value, 22 static void dwxgmac2_dma_init(void __iomem *ioaddr, argument 25 u32 value = readl(ioaddr + XGMAC_DMA_SYSBUS_MODE); 33 writel(value, ioaddr + XGMAC_DMA_SYSBUS_MODE); 37 void __iomem *ioaddr, 40 u32 value = readl(ioaddr + XGMAC_DMA_CH_CONTROL(chan)); 45 writel(value, ioaddr 36 dwxgmac2_dma_init_chan(struct stmmac_priv *priv, void __iomem *ioaddr, struct stmmac_dma_cfg *dma_cfg, u32 chan) argument 49 dwxgmac2_dma_init_rx_chan(struct stmmac_priv *priv, void __iomem *ioaddr, struct stmmac_dma_cfg *dma_cfg, dma_addr_t phy, u32 chan) argument 66 dwxgmac2_dma_init_tx_chan(struct stmmac_priv *priv, void __iomem *ioaddr, struct stmmac_dma_cfg *dma_cfg, dma_addr_t phy, u32 chan) argument 84 dwxgmac2_dma_axi(void __iomem *ioaddr, struct stmmac_axi *axi) argument 137 dwxgmac2_dma_dump_regs(struct stmmac_priv *priv, void __iomem *ioaddr, u32 *reg_space) argument 146 dwxgmac2_dma_rx_mode(struct stmmac_priv *priv, void __iomem *ioaddr, int mode, u32 channel, int fifosz, u8 qmode) argument 212 dwxgmac2_dma_tx_mode(struct stmmac_priv *priv, void __iomem *ioaddr, int mode, u32 channel, int fifosz, u8 qmode) argument 255 dwxgmac2_enable_dma_irq(struct stmmac_priv *priv, void __iomem *ioaddr, u32 chan, bool rx, bool tx) argument 269 dwxgmac2_disable_dma_irq(struct stmmac_priv *priv, void __iomem *ioaddr, u32 chan, bool rx, bool tx) argument 283 dwxgmac2_dma_start_tx(struct stmmac_priv *priv, void __iomem *ioaddr, u32 chan) argument 297 dwxgmac2_dma_stop_tx(struct stmmac_priv *priv, void __iomem *ioaddr, u32 chan) argument 311 dwxgmac2_dma_start_rx(struct stmmac_priv *priv, void __iomem *ioaddr, u32 chan) argument 325 dwxgmac2_dma_stop_rx(struct stmmac_priv *priv, void __iomem *ioaddr, u32 chan) argument 335 dwxgmac2_dma_interrupt(struct stmmac_priv *priv, void __iomem *ioaddr, struct stmmac_extra_stats *x, u32 chan, u32 dir) argument 388 dwxgmac2_get_hw_feature(void __iomem *ioaddr, struct dma_features *dma_cap) argument 503 dwxgmac2_rx_watchdog(struct stmmac_priv *priv, void __iomem *ioaddr, u32 riwt, u32 queue) argument 509 dwxgmac2_set_rx_ring_len(struct stmmac_priv *priv, void __iomem *ioaddr, u32 len, u32 chan) argument 515 dwxgmac2_set_tx_ring_len(struct stmmac_priv *priv, void __iomem *ioaddr, u32 len, u32 chan) argument 521 dwxgmac2_set_rx_tail_ptr(struct stmmac_priv *priv, void __iomem *ioaddr, u32 ptr, u32 chan) argument 527 dwxgmac2_set_tx_tail_ptr(struct stmmac_priv *priv, void __iomem *ioaddr, u32 ptr, u32 chan) argument 533 dwxgmac2_enable_tso(struct stmmac_priv *priv, void __iomem *ioaddr, bool en, u32 chan) argument 546 dwxgmac2_qmode(struct stmmac_priv *priv, void __iomem *ioaddr, u32 channel, u8 qmode) argument 564 dwxgmac2_set_bfsize(struct stmmac_priv *priv, void __iomem *ioaddr, int bfsize, u32 chan) argument 575 dwxgmac2_enable_sph(struct stmmac_priv *priv, void __iomem *ioaddr, bool en, u32 chan) argument 592 dwxgmac2_enable_tbs(struct stmmac_priv *priv, void __iomem *ioaddr, bool en, u32 chan) argument [all...] |
H A D | dwmac_lib.c | 17 int dwmac_dma_reset(void __iomem *ioaddr) argument 19 u32 value = readl(ioaddr + DMA_BUS_MODE); 23 writel(value, ioaddr + DMA_BUS_MODE); 25 return readl_poll_timeout(ioaddr + DMA_BUS_MODE, value, 31 void dwmac_enable_dma_transmission(void __iomem *ioaddr) argument 33 writel(1, ioaddr + DMA_XMT_POLL_DEMAND); 36 void dwmac_enable_dma_irq(struct stmmac_priv *priv, void __iomem *ioaddr, argument 39 u32 value = readl(ioaddr + DMA_INTR_ENA); 46 writel(value, ioaddr + DMA_INTR_ENA); 49 void dwmac_disable_dma_irq(struct stmmac_priv *priv, void __iomem *ioaddr, argument 62 dwmac_dma_start_tx(struct stmmac_priv *priv, void __iomem *ioaddr, u32 chan) argument 70 dwmac_dma_stop_tx(struct stmmac_priv *priv, void __iomem *ioaddr, u32 chan) argument 77 dwmac_dma_start_rx(struct stmmac_priv *priv, void __iomem *ioaddr, u32 chan) argument 85 dwmac_dma_stop_rx(struct stmmac_priv *priv, void __iomem *ioaddr, u32 chan) argument 162 dwmac_dma_interrupt(struct stmmac_priv *priv, void __iomem *ioaddr, struct stmmac_extra_stats *x, u32 chan, u32 dir) argument 243 dwmac_dma_flush_tx_fifo(void __iomem *ioaddr) argument 251 stmmac_set_mac_addr(void __iomem *ioaddr, const u8 addr[6], unsigned int high, unsigned int low) argument 268 stmmac_set_mac(void __iomem *ioaddr, bool enable) argument 284 stmmac_get_mac_addr(void __iomem *ioaddr, unsigned char *addr, unsigned int high, unsigned int low) argument [all...] |
H A D | dwmac4_lib.c | 16 int dwmac4_dma_reset(void __iomem *ioaddr) argument 18 u32 value = readl(ioaddr + DMA_BUS_MODE); 22 writel(value, ioaddr + DMA_BUS_MODE); 24 return readl_poll_timeout(ioaddr + DMA_BUS_MODE, value, 29 void dwmac4_set_rx_tail_ptr(struct stmmac_priv *priv, void __iomem *ioaddr, argument 34 writel(tail_ptr, ioaddr + DMA_CHAN_RX_END_ADDR(dwmac4_addrs, chan)); 37 void dwmac4_set_tx_tail_ptr(struct stmmac_priv *priv, void __iomem *ioaddr, argument 42 writel(tail_ptr, ioaddr + DMA_CHAN_TX_END_ADDR(dwmac4_addrs, chan)); 45 void dwmac4_dma_start_tx(struct stmmac_priv *priv, void __iomem *ioaddr, argument 49 u32 value = readl(ioaddr 59 dwmac4_dma_stop_tx(struct stmmac_priv *priv, void __iomem *ioaddr, u32 chan) argument 70 dwmac4_dma_start_rx(struct stmmac_priv *priv, void __iomem *ioaddr, u32 chan) argument 86 dwmac4_dma_stop_rx(struct stmmac_priv *priv, void __iomem *ioaddr, u32 chan) argument 96 dwmac4_set_tx_ring_len(struct stmmac_priv *priv, void __iomem *ioaddr, u32 len, u32 chan) argument 104 dwmac4_set_rx_ring_len(struct stmmac_priv *priv, void __iomem *ioaddr, u32 len, u32 chan) argument 112 dwmac4_enable_dma_irq(struct stmmac_priv *priv, void __iomem *ioaddr, u32 chan, bool rx, bool tx) argument 126 dwmac410_enable_dma_irq(struct stmmac_priv *priv, void __iomem *ioaddr, u32 chan, bool rx, bool tx) argument 140 dwmac4_disable_dma_irq(struct stmmac_priv *priv, void __iomem *ioaddr, u32 chan, bool rx, bool tx) argument 154 dwmac410_disable_dma_irq(struct stmmac_priv *priv, void __iomem *ioaddr, u32 chan, bool rx, bool tx) argument 168 dwmac4_dma_interrupt(struct stmmac_priv *priv, void __iomem *ioaddr, struct stmmac_extra_stats *x, u32 chan, u32 dir) argument 225 stmmac_dwmac4_set_mac_addr(void __iomem *ioaddr, const u8 addr[6], unsigned int high, unsigned int low) argument 242 stmmac_dwmac4_set_mac(void __iomem *ioaddr, bool enable) argument 256 stmmac_dwmac4_get_mac_addr(void __iomem *ioaddr, unsigned char *addr, unsigned int high, unsigned int low) argument [all...] |
H A D | dwmac5.c | 78 void __iomem *ioaddr, bool correctable, 83 value = readl(ioaddr + MAC_DPP_FSM_INT_STATUS); 84 writel(value, ioaddr + MAC_DPP_FSM_INT_STATUS); 126 void __iomem *ioaddr, bool correctable, 131 value = readl(ioaddr + MTL_ECC_INT_STATUS); 132 writel(value, ioaddr + MTL_ECC_INT_STATUS); 174 void __iomem *ioaddr, bool correctable, 179 value = readl(ioaddr + DMA_ECC_INT_STATUS); 180 writel(value, ioaddr + DMA_ECC_INT_STATUS); 186 int dwmac5_safety_feat_config(void __iomem *ioaddr, unsigne argument 77 dwmac5_handle_mac_err(struct net_device *ndev, void __iomem *ioaddr, bool correctable, struct stmmac_safety_stats *stats) argument 125 dwmac5_handle_mtl_err(struct net_device *ndev, void __iomem *ioaddr, bool correctable, struct stmmac_safety_stats *stats) argument 173 dwmac5_handle_dma_err(struct net_device *ndev, void __iomem *ioaddr, bool correctable, struct stmmac_safety_stats *stats) argument 267 dwmac5_safety_feat_irq_status(struct net_device *ndev, void __iomem *ioaddr, unsigned int asp, struct stmmac_safety_stats *stats) argument 330 dwmac5_rxp_disable(void __iomem *ioaddr) argument 342 dwmac5_rxp_enable(void __iomem *ioaddr) argument 351 dwmac5_rxp_update_single_entry(void __iomem *ioaddr, struct stmmac_tc_entry *entry, int pos) argument 433 dwmac5_rxp_config(void __iomem *ioaddr, struct stmmac_tc_entry *entries, unsigned int count) argument 520 dwmac5_flex_pps_config(void __iomem *ioaddr, int index, struct stmmac_pps_cfg *cfg, bool enable, u32 sub_second_inc, u32 systime_flags) argument 576 dwmac5_fpe_configure(void __iomem *ioaddr, struct stmmac_fpe_cfg *cfg, u32 num_txq, u32 num_rxq, bool enable) argument 594 dwmac5_fpe_irq_status(void __iomem *ioaddr, struct net_device *dev) argument 629 dwmac5_fpe_send_mpacket(void __iomem *ioaddr, struct stmmac_fpe_cfg *cfg, enum stmmac_mpacket_type type) argument [all...] |
H A D | stmmac_hwtstamp.c | 21 static void config_hw_tstamping(void __iomem *ioaddr, u32 data) argument 23 writel(data, ioaddr + PTP_TCR); 26 static void config_sub_second_increment(void __iomem *ioaddr, argument 29 u32 value = readl(ioaddr + PTP_TCR); 57 writel(reg_value, ioaddr + PTP_SSIR); 65 void __iomem *ioaddr = priv->ptpaddr; local 72 scaled_ns = readl(ioaddr + PTP_TS_INGR_LAT); 77 val = readl(ioaddr + PTP_TCR); 92 writel(reg_tsic, ioaddr + PTP_TS_INGR_CORR_NS); 93 writel(reg_tsicsns, ioaddr 105 init_systime(void __iomem *ioaddr, u32 sec, u32 nsec) argument 122 config_addend(void __iomem *ioaddr, u32 addend) argument 146 adjust_systime(void __iomem *ioaddr, u32 sec, u32 nsec, int add_sub, int gmac4) argument 189 get_systime(void __iomem *ioaddr, u64 *systime) argument [all...] |
H A D | dwmac100_dma.c | 21 static void dwmac100_dma_init(void __iomem *ioaddr, argument 26 ioaddr + DMA_BUS_MODE); 29 writel(DMA_INTR_DEFAULT_MASK, ioaddr + DMA_INTR_ENA); 32 static void dwmac100_dma_init_rx(struct stmmac_priv *priv, void __iomem *ioaddr, argument 37 writel(lower_32_bits(dma_rx_phy), ioaddr + DMA_RCV_BASE_ADDR); 40 static void dwmac100_dma_init_tx(struct stmmac_priv *priv, void __iomem *ioaddr, argument 45 writel(lower_32_bits(dma_tx_phy), ioaddr + DMA_TX_BASE_ADDR); 54 void __iomem *ioaddr, int mode, 57 u32 csr6 = readl(ioaddr + DMA_CONTROL); 66 writel(csr6, ioaddr 53 dwmac100_dma_operation_mode_tx(struct stmmac_priv *priv, void __iomem *ioaddr, int mode, u32 channel, int fifosz, u8 qmode) argument 69 dwmac100_dump_dma_regs(struct stmmac_priv *priv, void __iomem *ioaddr, u32 *reg_space) argument 85 dwmac100_dma_diagnostic_fr(struct stmmac_extra_stats *x, void __iomem *ioaddr) argument [all...] |
H A D | dwmac1000_core.c | 26 void __iomem *ioaddr = hw->pcsr; local 27 u32 value = readl(ioaddr + GMAC_CONTROL); 55 writel(value, ioaddr + GMAC_CONTROL); 63 writel(value, ioaddr + GMAC_INT_MASK); 67 writel(0x0, ioaddr + GMAC_VLAN_TAG); 73 void __iomem *ioaddr = hw->pcsr; local 74 u32 value = readl(ioaddr + GMAC_CONTROL); 81 writel(value, ioaddr + GMAC_CONTROL); 83 value = readl(ioaddr + GMAC_CONTROL); 90 void __iomem *ioaddr local 101 void __iomem *ioaddr = hw->pcsr; local 110 void __iomem *ioaddr = hw->pcsr; local 115 dwmac1000_set_mchash(void __iomem *ioaddr, u32 *mcfilterbits, int mcbitslog2) argument 143 void __iomem *ioaddr = (void __iomem *)dev->base_addr; local 223 void __iomem *ioaddr = hw->pcsr; local 249 void __iomem *ioaddr = hw->pcsr; local 265 dwmac1000_rgsmii(void __iomem *ioaddr, struct stmmac_extra_stats *x) argument 300 void __iomem *ioaddr = hw->pcsr; local 347 void __iomem *ioaddr = hw->pcsr; local 363 void __iomem *ioaddr = hw->pcsr; local 373 void __iomem *ioaddr = hw->pcsr; local 388 void __iomem *ioaddr = hw->pcsr; local 401 dwmac1000_ctrl_ane(void __iomem *ioaddr, bool ane, bool srgmi_ral, bool loopback) argument 407 dwmac1000_rane(void __iomem *ioaddr, bool restart) argument 412 dwmac1000_get_adv_lp(void __iomem *ioaddr, struct rgmii_adv *adv) argument 417 dwmac1000_debug(struct stmmac_priv *priv, void __iomem *ioaddr, struct stmmac_extra_stats *x, u32 rx_queues, u32 tx_queues) argument 493 dwmac1000_set_mac_loopback(void __iomem *ioaddr, bool enable) argument [all...] |
/linux-master/drivers/net/ethernet/realtek/ |
H A D | atp.h | 108 static inline unsigned char read_byte_mode0(short ioaddr) argument 112 outb(Ctrl_LNibRead, ioaddr + PAR_CONTROL); 113 inbyte(ioaddr + PAR_STATUS); 114 low_nib = (inbyte(ioaddr + PAR_STATUS) >> 3) & 0x0f; 115 outb(Ctrl_HNibRead, ioaddr + PAR_CONTROL); 116 inbyte(ioaddr + PAR_STATUS); /* Settling time delay -- needed! */ 117 inbyte(ioaddr + PAR_STATUS); /* Settling time delay -- needed! */ 118 return low_nib | ((inbyte(ioaddr + PAR_STATUS) << 1) & 0xf0); 122 static inline unsigned char read_byte_mode2(short ioaddr) argument 126 outb(Ctrl_LNibRead, ioaddr 135 read_byte_mode4(short ioaddr) argument 146 read_byte_mode6(short ioaddr) argument 224 write_byte_mode0(short ioaddr, unsigned char value) argument 230 write_byte_mode1(short ioaddr, unsigned char value) argument 239 write_word_mode0(short ioaddr, unsigned short value) argument [all...] |
/linux-master/drivers/rtc/ |
H A D | rtc-ds1742.c | 58 void __iomem *ioaddr = pdata->ioaddr_rtc; local 63 writeb(RTC_WRITE, ioaddr + RTC_CONTROL); 65 writeb(bin2bcd(tm->tm_year % 100), ioaddr + RTC_YEAR); 66 writeb(bin2bcd(tm->tm_mon + 1), ioaddr + RTC_MONTH); 67 writeb(bin2bcd(tm->tm_wday) & RTC_DAY_MASK, ioaddr + RTC_DAY); 68 writeb(bin2bcd(tm->tm_mday), ioaddr + RTC_DATE); 69 writeb(bin2bcd(tm->tm_hour), ioaddr + RTC_HOURS); 70 writeb(bin2bcd(tm->tm_min), ioaddr + RTC_MINUTES); 71 writeb(bin2bcd(tm->tm_sec) & RTC_SECONDS_MASK, ioaddr + RTC_SECONDS); 74 writeb(RTC_WRITE | (century & RTC_CENTURY_MASK), ioaddr 82 void __iomem *ioaddr = pdata->ioaddr_rtc; local 121 void __iomem *ioaddr = pdata->ioaddr_nvram; local 133 void __iomem *ioaddr = pdata->ioaddr_nvram; local 147 void __iomem *ioaddr; local [all...] |
H A D | rtc-stk17ta8.c | 61 void __iomem *ioaddr; member in struct:rtc_plat_data 75 void __iomem *ioaddr = pdata->ioaddr; local 78 flags = readb(pdata->ioaddr + RTC_FLAGS); 79 writeb(flags | RTC_WRITE, pdata->ioaddr + RTC_FLAGS); 81 writeb(bin2bcd(tm->tm_year % 100), ioaddr + RTC_YEAR); 82 writeb(bin2bcd(tm->tm_mon + 1), ioaddr + RTC_MONTH); 83 writeb(bin2bcd(tm->tm_wday) & RTC_DAY_MASK, ioaddr + RTC_DAY); 84 writeb(bin2bcd(tm->tm_mday), ioaddr + RTC_DATE); 85 writeb(bin2bcd(tm->tm_hour), ioaddr 97 void __iomem *ioaddr = pdata->ioaddr; local 132 void __iomem *ioaddr = pdata->ioaddr; local 193 void __iomem *ioaddr = pdata->ioaddr; local 237 void __iomem *ioaddr = pdata->ioaddr; local 249 void __iomem *ioaddr = pdata->ioaddr; local 262 void __iomem *ioaddr; local [all...] |
H A D | rtc-ds1553.c | 60 void __iomem *ioaddr; member in struct:rtc_plat_data 74 void __iomem *ioaddr = pdata->ioaddr; local 79 writeb(RTC_WRITE, pdata->ioaddr + RTC_CONTROL); 81 writeb(bin2bcd(tm->tm_year % 100), ioaddr + RTC_YEAR); 82 writeb(bin2bcd(tm->tm_mon + 1), ioaddr + RTC_MONTH); 83 writeb(bin2bcd(tm->tm_wday) & RTC_DAY_MASK, ioaddr + RTC_DAY); 84 writeb(bin2bcd(tm->tm_mday), ioaddr + RTC_DATE); 85 writeb(bin2bcd(tm->tm_hour), ioaddr + RTC_HOURS); 86 writeb(bin2bcd(tm->tm_min), ioaddr 98 void __iomem *ioaddr = pdata->ioaddr; local 130 void __iomem *ioaddr = pdata->ioaddr; local 185 void __iomem *ioaddr = pdata->ioaddr; local 229 void __iomem *ioaddr = pdata->ioaddr; local 242 void __iomem *ioaddr = pdata->ioaddr; local 254 void __iomem *ioaddr; local [all...] |
/linux-master/drivers/net/ethernet/3com/ |
H A D | 3c574_cs.c | 131 #define EL3WINDOW(win_num) outw(SelectWindow + (win_num), ioaddr + EL3_CMD) 220 static void mdio_sync(unsigned int ioaddr, int bits); 221 static int mdio_read(unsigned int ioaddr, int phy_id, int location); 222 static void mdio_write(unsigned int ioaddr, int phy_id, int location, 224 static unsigned short read_eeprom(unsigned int ioaddr, int index); 309 unsigned int ioaddr; local 339 ioaddr = dev->base_addr; 354 addr[i] = htons(read_eeprom(ioaddr, i + 10)); 369 outw(2<<11, ioaddr + RunnerRdCtrl); 370 mcr = inb(ioaddr 473 unsigned int ioaddr = dev->base_addr; local 502 read_eeprom(unsigned int ioaddr, int index) argument 530 mdio_sync(unsigned int ioaddr, int bits) argument 541 mdio_read(unsigned int ioaddr, int phy_id, int location) argument 566 mdio_write(unsigned int ioaddr, int phy_id, int location, int value) argument 593 unsigned int ioaddr = dev->base_addr; local 694 unsigned int ioaddr = dev->base_addr; local 708 unsigned int ioaddr = dev->base_addr; local 732 unsigned int ioaddr = dev->base_addr; local 769 unsigned int ioaddr; local 863 unsigned int ioaddr = dev->base_addr; local 952 unsigned int ioaddr = dev->base_addr; local 986 unsigned int ioaddr = dev->base_addr; local 1037 unsigned int ioaddr = dev->base_addr; local 1092 unsigned int ioaddr = dev->base_addr; local 1115 unsigned int ioaddr = dev->base_addr; local [all...] |
/linux-master/drivers/net/ethernet/smsc/ |
H A D | smc9194.c | 268 static int smc_probe(struct net_device *dev, int ioaddr); 290 static void smc_reset( int ioaddr ); 293 static void smc_enable( int ioaddr ); 296 static void smc_shutdown( int ioaddr ); 300 static int smc_findirq( int ioaddr ); 303 . Function: smc_reset( int ioaddr ) 319 static void smc_reset( int ioaddr ) 324 outw( RCR_SOFTRESET, ioaddr + RCR ); 331 outw( RCR_CLEAR, ioaddr + RCR ); 332 outw( TCR_CLEAR, ioaddr 421 smc_setmulticast(int ioaddr, struct net_device *dev) argument 471 unsigned int ioaddr = dev->base_addr; local 584 unsigned int ioaddr; local 739 smc_findirq(int ioaddr) argument 845 smc_probe(struct net_device *dev, int ioaddr) argument 1050 int ioaddr = dev->base_addr; local 1128 int ioaddr = dev->base_addr; local 1249 int ioaddr = dev->base_addr; local 1314 int ioaddr = dev->base_addr; local 1454 short ioaddr = dev->base_addr; local [all...] |