stmicro/stmmac/dwmac1000_core.c

26 	void __iomem *ioaddr = hw->pcsr;
27 	u32 value = readl(ioaddr + GMAC_CONTROL);
55 	writel(value, ioaddr + GMAC_CONTROL);
63 	writel(value, ioaddr + GMAC_INT_MASK);
67 	writel(0x0, ioaddr + GMAC_VLAN_TAG);
73 	void __iomem *ioaddr = hw->pcsr;
74 	u32 value = readl(ioaddr + GMAC_CONTROL);
81 	writel(value, ioaddr + GMAC_CONTROL);
83 	value = readl(ioaddr + GMAC_CONTROL);
90 	void __iomem *ioaddr = hw->pcsr;
94 		reg_space[i] = readl(ioaddr + i * 4);
101 	void __iomem *ioaddr = hw->pcsr;
102 	stmmac_set_mac_addr(ioaddr, addr, GMAC_ADDR_HIGH(reg_n),
110 	void __iomem *ioaddr = hw->pcsr;
111 	stmmac_get_mac_addr(ioaddr, addr, GMAC_ADDR_HIGH(reg_n),
115 static void dwmac1000_set_mchash(void __iomem *ioaddr, u32 *mcfilterbits,
122 		writel(mcfilterbits[0], ioaddr + GMAC_HASH_LOW);
123 		writel(mcfilterbits[1], ioaddr + GMAC_HASH_HIGH);
137 		       ioaddr + GMAC_EXTHASH_BASE + regs * 4);
143 	void __iomem *ioaddr = (void __iomem *)dev->base_addr;
185 	dwmac1000_set_mchash(ioaddr, mc_filter, mcbitslog2);
198 			stmmac_set_mac_addr(ioaddr, ha->addr,
205 			writel(0, ioaddr + GMAC_ADDR_HIGH(reg));
206 			writel(0, ioaddr + GMAC_ADDR_LOW(reg));
215 	writel(value, ioaddr + GMAC_FRAME_FILTER);
223 	void __iomem *ioaddr = hw->pcsr;
244 	writel(flow, ioaddr + GMAC_FLOW_CTRL);
249 	void __iomem *ioaddr = hw->pcsr;
261 	writel(pmt, ioaddr + GMAC_PMT);
265 static void dwmac1000_rgsmii(void __iomem *ioaddr, struct stmmac_extra_stats *x)
269 	status = readl(ioaddr + GMAC_RGSMIIIS);
300 	void __iomem *ioaddr = hw->pcsr;
301 	u32 intr_status = readl(ioaddr + GMAC_INT_STATUS);
302 	u32 intr_mask = readl(ioaddr + GMAC_INT_MASK);
317 		readl(ioaddr + GMAC_PMT);
324 		ret = readl(ioaddr + LPI_CTRL_STATUS);
336 	dwmac_pcs_isr(ioaddr, GMAC_PCS_BASE, intr_status, x);
339 		dwmac1000_rgsmii(ioaddr, x);
347 	void __iomem *ioaddr = hw->pcsr;
356 	value = readl(ioaddr + LPI_CTRL_STATUS);
358 	writel(value, ioaddr + LPI_CTRL_STATUS);
363 	void __iomem *ioaddr = hw->pcsr;
366 	value = readl(ioaddr + LPI_CTRL_STATUS);
368 	writel(value, ioaddr + LPI_CTRL_STATUS);
373 	void __iomem *ioaddr = hw->pcsr;
376 	value = readl(ioaddr + LPI_CTRL_STATUS);
383 	writel(value, ioaddr + LPI_CTRL_STATUS);
388 	void __iomem *ioaddr = hw->pcsr;
398 	writel(value, ioaddr + LPI_TIMER_CTRL);
401 static void dwmac1000_ctrl_ane(void __iomem *ioaddr, bool ane, bool srgmi_ral,
404 	dwmac_ctrl_ane(ioaddr, GMAC_PCS_BASE, ane, srgmi_ral, loopback);
407 static void dwmac1000_rane(void __iomem *ioaddr, bool restart)
409 	dwmac_rane(ioaddr, GMAC_PCS_BASE, restart);
412 static void dwmac1000_get_adv_lp(void __iomem *ioaddr, struct rgmii_adv *adv)
414 	dwmac_get_adv_lp(ioaddr, GMAC_PCS_BASE, adv);
417 static void dwmac1000_debug(struct stmmac_priv *priv, void __iomem *ioaddr,
421 	u32 value = readl(ioaddr + GMAC_DEBUG);
493 static void dwmac1000_set_mac_loopback(void __iomem *ioaddr, bool enable)
495 	u32 value = readl(ioaddr + GMAC_CONTROL);
502 	writel(value, ioaddr + GMAC_CONTROL);
534 	mac->pcsr = priv->ioaddr;