stmicro/stmmac/dwxgmac2_dma.c

11 static int dwxgmac2_dma_reset(void __iomem *ioaddr)
13 	u32 value = readl(ioaddr + XGMAC_DMA_MODE);
16 	writel(value | XGMAC_SWR, ioaddr + XGMAC_DMA_MODE);
18 	return readl_poll_timeout(ioaddr + XGMAC_DMA_MODE, value,
22 static void dwxgmac2_dma_init(void __iomem *ioaddr,
25 	u32 value = readl(ioaddr + XGMAC_DMA_SYSBUS_MODE);
33 	writel(value, ioaddr + XGMAC_DMA_SYSBUS_MODE);
37 				   void __iomem *ioaddr,
40 	u32 value = readl(ioaddr + XGMAC_DMA_CH_CONTROL(chan));
45 	writel(value, ioaddr + XGMAC_DMA_CH_CONTROL(chan));
46 	writel(XGMAC_DMA_INT_DEFAULT_EN, ioaddr + XGMAC_DMA_CH_INT_EN(chan));
50 				      void __iomem *ioaddr,
57 	value = readl(ioaddr + XGMAC_DMA_CH_RX_CONTROL(chan));
60 	writel(value, ioaddr + XGMAC_DMA_CH_RX_CONTROL(chan));
62 	writel(upper_32_bits(phy), ioaddr + XGMAC_DMA_CH_RxDESC_HADDR(chan));
63 	writel(lower_32_bits(phy), ioaddr + XGMAC_DMA_CH_RxDESC_LADDR(chan));
67 				      void __iomem *ioaddr,
74 	value = readl(ioaddr + XGMAC_DMA_CH_TX_CONTROL(chan));
78 	writel(value, ioaddr + XGMAC_DMA_CH_TX_CONTROL(chan));
80 	writel(upper_32_bits(phy), ioaddr + XGMAC_DMA_CH_TxDESC_HADDR(chan));
81 	writel(lower_32_bits(phy), ioaddr + XGMAC_DMA_CH_TxDESC_LADDR(chan));
84 static void dwxgmac2_dma_axi(void __iomem *ioaddr, struct stmmac_axi *axi)
86 	u32 value = readl(ioaddr + XGMAC_DMA_SYSBUS_MODE);
132 	writel(value, ioaddr + XGMAC_DMA_SYSBUS_MODE);
133 	writel(XGMAC_TDPS, ioaddr + XGMAC_TX_EDMA_CTRL);
134 	writel(XGMAC_RDPS, ioaddr + XGMAC_RX_EDMA_CTRL);
138 				   void __iomem *ioaddr, u32 *reg_space)
143 		reg_space[i] = readl(ioaddr + i * 4);
146 static void dwxgmac2_dma_rx_mode(struct stmmac_priv *priv, void __iomem *ioaddr,
149 	u32 value = readl(ioaddr + XGMAC_MTL_RXQ_OPMODE(channel));
170 		u32 flow = readl(ioaddr + XGMAC_MTL_RXQ_FLOW_CONTROL(channel));
202 		writel(flow, ioaddr + XGMAC_MTL_RXQ_FLOW_CONTROL(channel));
205 	writel(value, ioaddr + XGMAC_MTL_RXQ_OPMODE(channel));
208 	value = readl(ioaddr + XGMAC_MTL_QINTEN(channel));
209 	writel(value | XGMAC_RXOIE, ioaddr + XGMAC_MTL_QINTEN(channel));
212 static void dwxgmac2_dma_tx_mode(struct stmmac_priv *priv, void __iomem *ioaddr,
215 	u32 value = readl(ioaddr + XGMAC_MTL_TXQ_OPMODE(channel));
252 	writel(value, ioaddr +  XGMAC_MTL_TXQ_OPMODE(channel));
256 				    void __iomem *ioaddr, u32 chan,
259 	u32 value = readl(ioaddr + XGMAC_DMA_CH_INT_EN(chan));
266 	writel(value, ioaddr + XGMAC_DMA_CH_INT_EN(chan));
270 				     void __iomem *ioaddr, u32 chan,
273 	u32 value = readl(ioaddr + XGMAC_DMA_CH_INT_EN(chan));
280 	writel(value, ioaddr + XGMAC_DMA_CH_INT_EN(chan));
284 				  void __iomem *ioaddr, u32 chan)
288 	value = readl(ioaddr + XGMAC_DMA_CH_TX_CONTROL(chan));
290 	writel(value, ioaddr + XGMAC_DMA_CH_TX_CONTROL(chan));
292 	value = readl(ioaddr + XGMAC_TX_CONFIG);
294 	writel(value, ioaddr + XGMAC_TX_CONFIG);
297 static void dwxgmac2_dma_stop_tx(struct stmmac_priv *priv, void __iomem *ioaddr,
302 	value = readl(ioaddr + XGMAC_DMA_CH_TX_CONTROL(chan));
304 	writel(value, ioaddr + XGMAC_DMA_CH_TX_CONTROL(chan));
306 	value = readl(ioaddr + XGMAC_TX_CONFIG);
308 	writel(value, ioaddr + XGMAC_TX_CONFIG);
312 				  void __iomem *ioaddr, u32 chan)
316 	value = readl(ioaddr + XGMAC_DMA_CH_RX_CONTROL(chan));
318 	writel(value, ioaddr + XGMAC_DMA_CH_RX_CONTROL(chan));
320 	value = readl(ioaddr + XGMAC_RX_CONFIG);
322 	writel(value, ioaddr + XGMAC_RX_CONFIG);
325 static void dwxgmac2_dma_stop_rx(struct stmmac_priv *priv, void __iomem *ioaddr,
330 	value = readl(ioaddr + XGMAC_DMA_CH_RX_CONTROL(chan));
332 	writel(value, ioaddr + XGMAC_DMA_CH_RX_CONTROL(chan));
336 				  void __iomem *ioaddr,
341 	u32 intr_status = readl(ioaddr + XGMAC_DMA_CH_STATUS(chan));
342 	u32 intr_en = readl(ioaddr + XGMAC_DMA_CH_INT_EN(chan));
383 	writel(intr_en & intr_status, ioaddr + XGMAC_DMA_CH_STATUS(chan));
388 static int dwxgmac2_get_hw_feature(void __iomem *ioaddr,
394 	hw_cap = readl(ioaddr + XGMAC_HW_FEATURE0);
417 	hw_cap = readl(ioaddr + XGMAC_HW_FEATURE1);
463 	hw_cap = readl(ioaddr + XGMAC_HW_FEATURE2);
476 	hw_cap = readl(ioaddr + XGMAC_HW_FEATURE3);
496 	hw_cap = readl(ioaddr + XGMAC_HW_FEATURE4);
503 static void dwxgmac2_rx_watchdog(struct stmmac_priv *priv, void __iomem *ioaddr,
506 	writel(riwt & XGMAC_RWT, ioaddr + XGMAC_DMA_CH_Rx_WATCHDOG(queue));
510 				     void __iomem *ioaddr, u32 len, u32 chan)
512 	writel(len, ioaddr + XGMAC_DMA_CH_RxDESC_RING_LEN(chan));
516 				     void __iomem *ioaddr, u32 len, u32 chan)
518 	writel(len, ioaddr + XGMAC_DMA_CH_TxDESC_RING_LEN(chan));
522 				     void __iomem *ioaddr, u32 ptr, u32 chan)
524 	writel(ptr, ioaddr + XGMAC_DMA_CH_RxDESC_TAIL_LPTR(chan));
528 				     void __iomem *ioaddr, u32 ptr, u32 chan)
530 	writel(ptr, ioaddr + XGMAC_DMA_CH_TxDESC_TAIL_LPTR(chan));
533 static void dwxgmac2_enable_tso(struct stmmac_priv *priv, void __iomem *ioaddr,
536 	u32 value = readl(ioaddr + XGMAC_DMA_CH_TX_CONTROL(chan));
543 	writel(value, ioaddr + XGMAC_DMA_CH_TX_CONTROL(chan));
546 static void dwxgmac2_qmode(struct stmmac_priv *priv, void __iomem *ioaddr,
549 	u32 value = readl(ioaddr + XGMAC_MTL_TXQ_OPMODE(channel));
550 	u32 flow = readl(ioaddr + XGMAC_RX_FLOW_CTRL);
555 		writel(0, ioaddr + XGMAC_MTL_TCx_ETS_CONTROL(channel));
558 		writel(flow & (~XGMAC_RFE), ioaddr + XGMAC_RX_FLOW_CTRL);
561 	writel(value, ioaddr +  XGMAC_MTL_TXQ_OPMODE(channel));
564 static void dwxgmac2_set_bfsize(struct stmmac_priv *priv, void __iomem *ioaddr,
569 	value = readl(ioaddr + XGMAC_DMA_CH_RX_CONTROL(chan));
572 	writel(value, ioaddr + XGMAC_DMA_CH_RX_CONTROL(chan));
575 static void dwxgmac2_enable_sph(struct stmmac_priv *priv, void __iomem *ioaddr,
578 	u32 value = readl(ioaddr + XGMAC_RX_CONFIG);
582 	writel(value, ioaddr + XGMAC_RX_CONFIG);
584 	value = readl(ioaddr + XGMAC_DMA_CH_CONTROL(chan));
589 	writel(value, ioaddr + XGMAC_DMA_CH_CONTROL(chan));
592 static int dwxgmac2_enable_tbs(struct stmmac_priv *priv, void __iomem *ioaddr,
595 	u32 value = readl(ioaddr + XGMAC_DMA_CH_TX_CONTROL(chan));
602 	writel(value, ioaddr + XGMAC_DMA_CH_TX_CONTROL(chan));
604 	value = readl(ioaddr + XGMAC_DMA_CH_TX_CONTROL(chan)) & XGMAC_EDSE;
608 	writel(XGMAC_DEF_FTOS, ioaddr + XGMAC_DMA_TBS_CTRL0);
609 	writel(XGMAC_DEF_FTOS, ioaddr + XGMAC_DMA_TBS_CTRL1);
610 	writel(XGMAC_DEF_FTOS, ioaddr + XGMAC_DMA_TBS_CTRL2);
611 	writel(XGMAC_DEF_FTOS, ioaddr + XGMAC_DMA_TBS_CTRL3);