stmicro/stmmac/stmmac_hwtstamp.c

21 static void config_hw_tstamping(void __iomem *ioaddr, u32 data)
23 	writel(data, ioaddr + PTP_TCR);
26 static void config_sub_second_increment(void __iomem *ioaddr,
29 	u32 value = readl(ioaddr + PTP_TCR);
57 	writel(reg_value, ioaddr + PTP_SSIR);
65 	void __iomem *ioaddr = priv->ptpaddr;
72 	scaled_ns = readl(ioaddr + PTP_TS_INGR_LAT);
77 	val = readl(ioaddr + PTP_TCR);
92 	writel(reg_tsic, ioaddr + PTP_TS_INGR_CORR_NS);
93 	writel(reg_tsicsns, ioaddr + PTP_TS_INGR_CORR_SNS);
96 	scaled_ns = readl(ioaddr + PTP_TS_EGR_LAT);
101 	writel(reg_tsec, ioaddr + PTP_TS_EGR_CORR_NS);
102 	writel(reg_tsecsns, ioaddr + PTP_TS_EGR_CORR_SNS);
105 static int init_systime(void __iomem *ioaddr, u32 sec, u32 nsec)
109 	writel(sec, ioaddr + PTP_STSUR);
110 	writel(nsec, ioaddr + PTP_STNSUR);
112 	value = readl(ioaddr + PTP_TCR);
114 	writel(value, ioaddr + PTP_TCR);
117 	return readl_poll_timeout_atomic(ioaddr + PTP_TCR, value,
122 static int config_addend(void __iomem *ioaddr, u32 addend)
127 	writel(addend, ioaddr + PTP_TAR);
129 	value = readl(ioaddr + PTP_TCR);
131 	writel(value, ioaddr + PTP_TCR);
136 		if (!(readl(ioaddr + PTP_TCR) & PTP_TCR_TSADDREG))
146 static int adjust_systime(void __iomem *ioaddr, u32 sec, u32 nsec,
160 		value = readl(ioaddr + PTP_TCR);
167 	writel(sec, ioaddr + PTP_STSUR);
169 	writel(value, ioaddr + PTP_STNSUR);
172 	value = readl(ioaddr + PTP_TCR);
174 	writel(value, ioaddr + PTP_TCR);
179 		if (!(readl(ioaddr + PTP_TCR) & PTP_TCR_TSUPDT))
189 static void get_systime(void __iomem *ioaddr, u64 *systime)
194 	sec1 = readl_relaxed(ioaddr + PTP_STSR);
198 		ns = readl_relaxed(ioaddr + PTP_STNSR);
200 		sec1 = readl_relaxed(ioaddr + PTP_STSR);
230 	tsync_int = readl(priv->ioaddr + GMAC_INT_STATUS) & GMAC_INT_TSIE;
238 	ts_status = readl(priv->ioaddr + GMAC_TIMESTAMP_STATUS);