stmicro/stmmac/dwmac4_lib.c

16 int dwmac4_dma_reset(void __iomem *ioaddr)
18 	u32 value = readl(ioaddr + DMA_BUS_MODE);
22 	writel(value, ioaddr + DMA_BUS_MODE);
24 	return readl_poll_timeout(ioaddr + DMA_BUS_MODE, value,
29 void dwmac4_set_rx_tail_ptr(struct stmmac_priv *priv, void __iomem *ioaddr,
34 	writel(tail_ptr, ioaddr + DMA_CHAN_RX_END_ADDR(dwmac4_addrs, chan));
37 void dwmac4_set_tx_tail_ptr(struct stmmac_priv *priv, void __iomem *ioaddr,
42 	writel(tail_ptr, ioaddr + DMA_CHAN_TX_END_ADDR(dwmac4_addrs, chan));
45 void dwmac4_dma_start_tx(struct stmmac_priv *priv, void __iomem *ioaddr,
49 	u32 value = readl(ioaddr + DMA_CHAN_TX_CONTROL(dwmac4_addrs, chan));
52 	writel(value, ioaddr + DMA_CHAN_TX_CONTROL(dwmac4_addrs, chan));
54 	value = readl(ioaddr + GMAC_CONFIG);
56 	writel(value, ioaddr + GMAC_CONFIG);
59 void dwmac4_dma_stop_tx(struct stmmac_priv *priv, void __iomem *ioaddr,
64 	u32 value = readl(ioaddr + DMA_CHAN_TX_CONTROL(dwmac4_addrs, chan));
67 	writel(value, ioaddr + DMA_CHAN_TX_CONTROL(dwmac4_addrs, chan));
70 void dwmac4_dma_start_rx(struct stmmac_priv *priv, void __iomem *ioaddr,
75 	u32 value = readl(ioaddr + DMA_CHAN_RX_CONTROL(dwmac4_addrs, chan));
79 	writel(value, ioaddr + DMA_CHAN_RX_CONTROL(dwmac4_addrs, chan));
81 	value = readl(ioaddr + GMAC_CONFIG);
83 	writel(value, ioaddr + GMAC_CONFIG);
86 void dwmac4_dma_stop_rx(struct stmmac_priv *priv, void __iomem *ioaddr,
90 	u32 value = readl(ioaddr + DMA_CHAN_RX_CONTROL(dwmac4_addrs, chan));
93 	writel(value, ioaddr + DMA_CHAN_RX_CONTROL(dwmac4_addrs, chan));
96 void dwmac4_set_tx_ring_len(struct stmmac_priv *priv, void __iomem *ioaddr,
101 	writel(len, ioaddr + DMA_CHAN_TX_RING_LEN(dwmac4_addrs, chan));
104 void dwmac4_set_rx_ring_len(struct stmmac_priv *priv, void __iomem *ioaddr,
109 	writel(len, ioaddr + DMA_CHAN_RX_RING_LEN(dwmac4_addrs, chan));
112 void dwmac4_enable_dma_irq(struct stmmac_priv *priv, void __iomem *ioaddr,
116 	u32 value = readl(ioaddr + DMA_CHAN_INTR_ENA(dwmac4_addrs, chan));
123 	writel(value, ioaddr + DMA_CHAN_INTR_ENA(dwmac4_addrs, chan));
126 void dwmac410_enable_dma_irq(struct stmmac_priv *priv, void __iomem *ioaddr,
130 	u32 value = readl(ioaddr + DMA_CHAN_INTR_ENA(dwmac4_addrs, chan));
137 	writel(value, ioaddr + DMA_CHAN_INTR_ENA(dwmac4_addrs, chan));
140 void dwmac4_disable_dma_irq(struct stmmac_priv *priv, void __iomem *ioaddr,
144 	u32 value = readl(ioaddr + DMA_CHAN_INTR_ENA(dwmac4_addrs, chan));
151 	writel(value, ioaddr + DMA_CHAN_INTR_ENA(dwmac4_addrs, chan));
154 void dwmac410_disable_dma_irq(struct stmmac_priv *priv, void __iomem *ioaddr,
158 	u32 value = readl(ioaddr + DMA_CHAN_INTR_ENA(dwmac4_addrs, chan));
165 	writel(value, ioaddr + DMA_CHAN_INTR_ENA(dwmac4_addrs, chan));
168 int dwmac4_dma_interrupt(struct stmmac_priv *priv, void __iomem *ioaddr,
172 	u32 intr_status = readl(ioaddr + DMA_CHAN_STATUS(dwmac4_addrs, chan));
173 	u32 intr_en = readl(ioaddr + DMA_CHAN_INTR_ENA(dwmac4_addrs, chan));
221 	       ioaddr + DMA_CHAN_STATUS(dwmac4_addrs, chan));
225 void stmmac_dwmac4_set_mac_addr(void __iomem *ioaddr, const u8 addr[6],
236 	writel(data | GMAC_HI_REG_AE, ioaddr + high);
238 	writel(data, ioaddr + low);
242 void stmmac_dwmac4_set_mac(void __iomem *ioaddr, bool enable)
244 	u32 value = readl(ioaddr + GMAC_CONFIG);
253 		writel(value, ioaddr + GMAC_CONFIG);
256 void stmmac_dwmac4_get_mac_addr(void __iomem *ioaddr, unsigned char *addr,
262 	hi_addr = readl(ioaddr + high);
263 	lo_addr = readl(ioaddr + low);