/linux-master/drivers/gpu/drm/i915/display/ |
H A D | intel_display_wa.c | 14 intel_de_write(i915, ILK_DPFC_CHICKEN(INTEL_FBC_A), 24 intel_de_write(i915, ILK_DPFC_CHICKEN(INTEL_FBC_A),
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H A D | intel_vdsc.c | 423 intel_de_write(i915, dsc_reg[i], pps_val); 558 intel_de_write(dev_priv, DSCA_RC_BUF_THRESH_0, 560 intel_de_write(dev_priv, DSCA_RC_BUF_THRESH_0_UDW, 562 intel_de_write(dev_priv, DSCA_RC_BUF_THRESH_1, 564 intel_de_write(dev_priv, DSCA_RC_BUF_THRESH_1_UDW, 567 intel_de_write(dev_priv, DSCC_RC_BUF_THRESH_0, 569 intel_de_write(dev_priv, DSCC_RC_BUF_THRESH_0_UDW, 571 intel_de_write(dev_priv, DSCC_RC_BUF_THRESH_1, 573 intel_de_write(dev_priv, DSCC_RC_BUF_THRESH_1_UDW, 577 intel_de_write(dev_pri [all...] |
H A D | intel_fdi.c | 434 intel_de_write(dev_priv, SOUTH_CHICKEN1, temp); 480 intel_de_write(dev_priv, reg, temp); 491 intel_de_write(dev_priv, reg, temp | FDI_RX_ENHANCE_FRAME_ENABLE); 516 intel_de_write(dev_priv, FDI_RX_TUSIZE1(pipe), 528 intel_de_write(dev_priv, reg, temp); 539 intel_de_write(dev_priv, reg, temp | FDI_TX_ENABLE); 545 intel_de_write(dev_priv, reg, temp | FDI_RX_ENABLE); 551 intel_de_write(dev_priv, FDI_RX_CHICKEN(pipe), 553 intel_de_write(dev_priv, FDI_RX_CHICKEN(pipe), 563 intel_de_write(dev_pri [all...] |
H A D | vlv_dsi.c | 113 intel_de_write(dev_priv, reg, val); 174 intel_de_write(dev_priv, MIPI_INTR_STAT(port), 184 intel_de_write(dev_priv, ctrl_reg, 240 intel_de_write(dev_priv, MIPI_INTR_STAT(port), SPL_PKT_SENT_INTERRUPT); 247 intel_de_write(dev_priv, MIPI_DPI_CONTROL(port), cmd); 451 intel_de_write(dev_priv, MIPI_DEVICE_READY(port), val); 454 intel_de_write(dev_priv, MIPI_DEVICE_READY(port), val); 477 intel_de_write(dev_priv, MIPI_DEVICE_READY(port), 488 intel_de_write(dev_priv, MIPI_DEVICE_READY(port), 492 intel_de_write(dev_pri [all...] |
H A D | intel_vrr.c | 206 intel_de_write(dev_priv, TRANS_VRR_CTL(cpu_transcoder), 0); 210 intel_de_write(dev_priv, TRANS_VRR_VMIN(cpu_transcoder), crtc_state->vrr.vmin - 1); 211 intel_de_write(dev_priv, TRANS_VRR_VMAX(cpu_transcoder), crtc_state->vrr.vmax - 1); 212 intel_de_write(dev_priv, TRANS_VRR_CTL(cpu_transcoder), trans_vrr_ctl(crtc_state)); 213 intel_de_write(dev_priv, TRANS_VRR_FLIPLINE(cpu_transcoder), crtc_state->vrr.flipline - 1); 225 intel_de_write(dev_priv, TRANS_PUSH(cpu_transcoder), 249 intel_de_write(dev_priv, TRANS_PUSH(cpu_transcoder), TRANS_PUSH_EN); 250 intel_de_write(dev_priv, TRANS_VRR_CTL(cpu_transcoder), 263 intel_de_write(dev_priv, TRANS_VRR_CTL(cpu_transcoder), 267 intel_de_write(dev_pri [all...] |
H A D | intel_fifo_underrun.c | 106 intel_de_write(dev_priv, reg, enable_mask | PIPE_FIFO_UNDERRUN_STATUS); 125 intel_de_write(dev_priv, reg, 159 intel_de_write(dev_priv, GEN7_ERR_INT, ERR_INT_FIFO_UNDERRUN(pipe)); 172 intel_de_write(dev_priv, GEN7_ERR_INT, 212 intel_de_write(dev_priv, ICL_PIPESTATUS(pipe), 246 intel_de_write(dev_priv, SERR_INT, 262 intel_de_write(dev_priv, SERR_INT, 423 intel_de_write(dev_priv, ICL_PIPESTATUS(pipe), underruns);
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H A D | intel_dkl_phy.c | 30 intel_de_write(i915, 73 intel_de_write(i915, DKL_REG_MMIO(reg), val);
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H A D | intel_pch_display.c | 130 intel_de_write(dev_priv, hdmi_reg, val); 149 intel_de_write(dev_priv, dp_reg, val); 226 intel_de_write(dev_priv, PCH_TRANS_HTOTAL(pch_transcoder), 228 intel_de_write(dev_priv, PCH_TRANS_HBLANK(pch_transcoder), 230 intel_de_write(dev_priv, PCH_TRANS_HSYNC(pch_transcoder), 233 intel_de_write(dev_priv, PCH_TRANS_VTOTAL(pch_transcoder), 235 intel_de_write(dev_priv, PCH_TRANS_VBLANK(pch_transcoder), 237 intel_de_write(dev_priv, PCH_TRANS_VSYNC(pch_transcoder), 239 intel_de_write(dev_priv, PCH_TRANS_VSYNCSHIFT(pch_transcoder), 269 intel_de_write(dev_pri [all...] |
H A D | intel_tv.c | 1406 intel_de_write(dev_priv, TV_H_CTL_1, hctl1); 1407 intel_de_write(dev_priv, TV_H_CTL_2, hctl2); 1408 intel_de_write(dev_priv, TV_H_CTL_3, hctl3); 1409 intel_de_write(dev_priv, TV_V_CTL_1, vctl1); 1410 intel_de_write(dev_priv, TV_V_CTL_2, vctl2); 1411 intel_de_write(dev_priv, TV_V_CTL_3, vctl3); 1412 intel_de_write(dev_priv, TV_V_CTL_4, vctl4); 1413 intel_de_write(dev_priv, TV_V_CTL_5, vctl5); 1414 intel_de_write(dev_priv, TV_V_CTL_6, vctl6); 1415 intel_de_write(dev_pri [all...] |
H A D | g4x_hdmi.c | 61 intel_de_write(dev_priv, intel_hdmi->hdmi_reg, hdmi_val); 232 intel_de_write(dev_priv, intel_hdmi->hdmi_reg, temp); 296 intel_de_write(dev_priv, intel_hdmi->hdmi_reg, temp); 298 intel_de_write(dev_priv, intel_hdmi->hdmi_reg, temp); 310 intel_de_write(dev_priv, intel_hdmi->hdmi_reg, 318 intel_de_write(dev_priv, intel_hdmi->hdmi_reg, temp); 320 intel_de_write(dev_priv, intel_hdmi->hdmi_reg, temp); 359 intel_de_write(dev_priv, intel_hdmi->hdmi_reg, temp); 366 intel_de_write(dev_priv, intel_hdmi->hdmi_reg, temp); 397 intel_de_write(dev_pri [all...] |
H A D | icl_dsi.c | 165 intel_de_write(i915, DSI_CMD_TXPYLD(dsi_trans), tmp); 202 intel_de_write(dev_priv, DSI_CMD_TXHDR(dsi_trans), tmp); 250 intel_de_write(dev_priv, ICL_PORT_TX_DW5_GRP(phy), tmp); 260 intel_de_write(dev_priv, ICL_PORT_TX_DW2_GRP(phy), tmp); 322 intel_de_write(dev_priv, dss_ctl1_reg, dss_ctl1); 362 intel_de_write(dev_priv, ICL_DSI_ESC_CLK_DIV(port), 368 intel_de_write(dev_priv, ICL_DPHY_ESC_CLK_DIV(port), 375 intel_de_write(dev_priv, ADL_MIPIO_DW(port, 8), 444 intel_de_write(dev_priv, ICL_PORT_TX_DW2_GRP(phy), tmp); 456 intel_de_write(dev_pri [all...] |
H A D | intel_crt.c | 196 intel_de_write(dev_priv, BCLRPAT(crtc->pipe), 0); 213 intel_de_write(dev_priv, crt->adpa_reg, adpa); 497 intel_de_write(dev_priv, crt->adpa_reg, adpa); 507 intel_de_write(dev_priv, crt->adpa_reg, save_adpa); 554 intel_de_write(dev_priv, crt->adpa_reg, adpa); 560 intel_de_write(dev_priv, crt->adpa_reg, save_adpa); 620 intel_de_write(dev_priv, PORT_HOTPLUG_STAT, CRT_HOTPLUG_INT_STATUS); 724 intel_de_write(dev_priv, BCLRPAT(cpu_transcoder), 0x500050); 729 intel_de_write(dev_priv, TRANSCONF(cpu_transcoder), 740 intel_de_write(dev_pri [all...] |
H A D | intel_backlight.c | 212 intel_de_write(i915, BLC_PWM_PCH_CTL2, val | level); 222 intel_de_write(i915, BLC_PWM_CPU_CTL, tmp | level); 250 intel_de_write(i915, BLC_PWM_CTL, tmp | level); 261 intel_de_write(i915, VLV_BLC_PWM_CTL(pipe), tmp | level); 270 intel_de_write(i915, BXT_BLC_PWM_DUTY(panel->backlight.controller), level); 353 intel_de_write(i915, BLC_PWM_CPU_CTL2, tmp & ~BLM_PWM_ENABLE); 478 intel_de_write(i915, BLC_PWM_PCH_CTL1, pch_ctl1); 491 intel_de_write(i915, BLC_PWM_PCH_CTL2, pch_ctl2); 501 intel_de_write(i915, BLC_PWM_PCH_CTL1, pch_ctl1); 503 intel_de_write(i91 [all...] |
H A D | intel_combo_phy.c | 87 intel_de_write(dev_priv, ICL_PORT_COMP_DW9(phy), procmon->dw9); 88 intel_de_write(dev_priv, ICL_PORT_COMP_DW10(phy), procmon->dw10); 344 intel_de_write(dev_priv, ICL_PHY_MISC(phy), val); 352 intel_de_write(dev_priv, ICL_PORT_TX_DW8_GRP(phy), val); 357 intel_de_write(dev_priv, ICL_PORT_PCS_DW1_GRP(phy), val);
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H A D | intel_hdmi.c | 219 intel_de_write(dev_priv, VIDEO_DIP_CTL, val); 222 intel_de_write(dev_priv, VIDEO_DIP_DATA, *data); 227 intel_de_write(dev_priv, VIDEO_DIP_DATA, 0); 233 intel_de_write(dev_priv, VIDEO_DIP_CTL, val); 289 intel_de_write(dev_priv, reg, val); 292 intel_de_write(dev_priv, TVIDEO_DIP_DATA(crtc->pipe), 298 intel_de_write(dev_priv, TVIDEO_DIP_DATA(crtc->pipe), 0); 304 intel_de_write(dev_priv, reg, val); 367 intel_de_write(dev_priv, reg, val); 370 intel_de_write(dev_pri [all...] |
H A D | intel_vga.c | 44 intel_de_write(dev_priv, vga_reg, VGA_DISP_DISABLE);
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H A D | intel_hdcp.c | 329 intel_de_write(i915, HDCP_KEY_CONF, HDCP_CLEAR_KEYS_TRIGGER); 330 intel_de_write(i915, HDCP_KEY_STATUS, 368 intel_de_write(i915, HDCP_KEY_CONF, HDCP_KEY_LOAD_TRIGGER); 381 intel_de_write(i915, HDCP_KEY_CONF, HDCP_AKSV_SEND_TRIGGER); 389 intel_de_write(i915, HDCP_SHA_TEXT, sha_text); 456 intel_de_write(i915, HDCP_SHA_V_PRIME(i), vprime); 473 intel_de_write(i915, HDCP_REP_CTL, rep_ctl | HDCP_SHA1_TEXT_32); 492 intel_de_write(i915, HDCP_REP_CTL, 525 intel_de_write(i915, HDCP_REP_CTL, 534 intel_de_write(i91 [all...] |
H A D | intel_lpe_audio.c | 241 intel_de_write(dev_priv, VLV_AUD_CHICKEN_BIT_REG, 352 intel_de_write(dev_priv, VLV_AUD_PORT_EN_DBG(port), 361 intel_de_write(dev_priv, VLV_AUD_PORT_EN_DBG(port),
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H A D | intel_fbc.c | 280 intel_de_write(i915, FBC_CONTROL, fbc_ctl); 298 intel_de_write(i915, FBC_TAG(i), 0); 301 intel_de_write(i915, FBC_CONTROL2, 303 intel_de_write(i915, FBC_FENCE_OFF, 307 intel_de_write(i915, FBC_CONTROL, 344 intel_de_write(i915, FBC_CFB_BASE, 346 intel_de_write(i915, FBC_LL_BASE, 420 intel_de_write(i915, DPFC_FENCE_YOFF, 423 intel_de_write(i915, DPFC_CONTROL, 436 intel_de_write(i91 [all...] |
H A D | g4x_dp.c | 210 intel_de_write(dev_priv, DP_A, intel_dp->DP); 225 intel_de_write(dev_priv, DP_A, intel_dp->DP); 244 intel_de_write(dev_priv, DP_A, intel_dp->DP); 432 intel_de_write(dev_priv, intel_dp->output_reg, intel_dp->DP); 436 intel_de_write(dev_priv, intel_dp->output_reg, intel_dp->DP); 456 intel_de_write(dev_priv, intel_dp->output_reg, intel_dp->DP); 460 intel_de_write(dev_priv, intel_dp->output_reg, intel_dp->DP); 490 intel_de_write(i915, intel_dp->output_reg, intel_dp->DP); 509 intel_de_write(i915, intel_dp->output_reg, intel_dp->DP); 617 intel_de_write(dev_pri [all...] |
H A D | intel_pipe_crc.c | 186 intel_de_write(dev_priv, PORT_DFT2_G4X, tmp); 249 intel_de_write(dev_priv, PORT_DFT2_G4X, tmp); 611 intel_de_write(dev_priv, PIPE_CRC_CTL(pipe), val); 646 intel_de_write(dev_priv, PIPE_CRC_CTL(pipe), val); 661 intel_de_write(dev_priv, PIPE_CRC_CTL(pipe), 0);
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H A D | vlv_dsi_pll.c | 374 intel_de_write(dev_priv, MIPI_CTRL(port), 418 intel_de_write(dev_priv, MIPIO_TXESC_CLK_DIV1, 420 intel_de_write(dev_priv, MIPIO_TXESC_CLK_DIV2, 475 intel_de_write(dev_priv, BXT_MIPI_CLOCK_CTL, tmp); 546 intel_de_write(dev_priv, BXT_DSI_PLL_CTL, config->dsi_pll.ctrl); 584 intel_de_write(dev_priv, BXT_MIPI_CLOCK_CTL, tmp); 590 intel_de_write(dev_priv, MIPI_EOT_DISABLE(port), CLOCKSTOP);
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H A D | intel_pps.c | 146 intel_de_write(dev_priv, intel_dp->output_reg, DP); 149 intel_de_write(dev_priv, intel_dp->output_reg, DP | DP_PORT_EN); 152 intel_de_write(dev_priv, intel_dp->output_reg, DP & ~DP_PORT_EN); 751 intel_de_write(dev_priv, pp_ctrl_reg, pp); 821 intel_de_write(dev_priv, pp_ctrl_reg, pp); 948 intel_de_write(dev_priv, pp_ctrl_reg, pp); 956 intel_de_write(dev_priv, pp_ctrl_reg, pp); 964 intel_de_write(dev_priv, pp_ctrl_reg, pp); 1011 intel_de_write(dev_priv, pp_ctrl_reg, pp); 1055 intel_de_write(dev_pri [all...] |
H A D | intel_pch_refclk.c | 109 intel_de_write(dev_priv, PIXCLK_GATE, PIXCLK_GATE_GATE); 226 intel_de_write(dev_priv, PIXCLK_GATE, PIXCLK_GATE_UNGATE); 615 intel_de_write(dev_priv, PCH_DREF_CONTROL, val); 634 intel_de_write(dev_priv, PCH_DREF_CONTROL, val); 645 intel_de_write(dev_priv, PCH_DREF_CONTROL, val); 659 intel_de_write(dev_priv, PCH_DREF_CONTROL, val);
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/linux-master/drivers/gpu/drm/i915/ |
H A D | i915_suspend.c | 68 intel_de_write(dev_priv, SWF0(i), dev_priv->regfile.saveSWF0[i]); 69 intel_de_write(dev_priv, SWF1(i), dev_priv->regfile.saveSWF1[i]); 72 intel_de_write(dev_priv, SWF3(i), dev_priv->regfile.saveSWF3[i]); 75 intel_de_write(dev_priv, SWF1(i), dev_priv->regfile.saveSWF1[i]); 78 intel_de_write(dev_priv, SWF0(i), dev_priv->regfile.saveSWF0[i]); 79 intel_de_write(dev_priv, SWF1(i), dev_priv->regfile.saveSWF1[i]); 82 intel_de_write(dev_priv, SWF3(i), dev_priv->regfile.saveSWF3[i]); 119 intel_de_write(dev_priv, DSPARB, dev_priv->regfile.saveDSPARB);
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