| /linux-master/drivers/gpu/drm/i915/display/ |
| H A D | intel_de.h | 82 intel_de_wait_for_clear(struct drm_i915_private *i915, i915_reg_t reg, function
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| H A D | hsw_ips.c | 78 if (intel_de_wait_for_clear(i915, IPS_CTL, IPS_ENABLE, 100))
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| H A D | vlv_dsi.c | 164 if (intel_de_wait_for_clear(dev_priv, MIPI_GEN_FIFO_STAT(port),
178 if (intel_de_wait_for_clear(dev_priv, MIPI_GEN_FIFO_STAT(port),
398 if (intel_de_wait_for_clear(dev_priv, MIPI_CTRL(port),
523 if (intel_de_wait_for_clear(dev_priv, MIPI_CTRL(port),
530 if (intel_de_wait_for_clear(dev_priv, MIPI_CTRL(port),
548 if (intel_de_wait_for_clear(dev_priv, MIPI_CTRL(port),
599 intel_de_wait_for_clear(dev_priv, port_ctrl,
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| H A D | intel_pmdemand.c | 375 return !(intel_de_wait_for_clear(i915,
378 intel_de_wait_for_clear(i915,
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| H A D | intel_pch_display.c | 326 if (intel_de_wait_for_clear(dev_priv, reg, TRANS_STATE_ENABLE, 50))
577 if (intel_de_wait_for_clear(dev_priv, LPT_TRANSCONF,
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| H A D | intel_vrr.c | 265 intel_de_wait_for_clear(dev_priv, TRANS_VRR_STATUS(cpu_transcoder),
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| H A D | intel_crt.c | 499 if (intel_de_wait_for_clear(dev_priv,
556 if (intel_de_wait_for_clear(dev_priv, crt->adpa_reg,
609 if (intel_de_wait_for_clear(dev_priv, PORT_HOTPLUG_EN,
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| H A D | intel_lvds.c | 343 if (intel_de_wait_for_clear(dev_priv, PP_STATUS(0), PP_ON, 1000))
382 if (intel_de_wait_for_clear(dev_priv, PP_STATUS(0), PP_CYCLE_DELAY_ACTIVE, 5000))
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| H A D | vlv_dsi_pll.c | 314 if (intel_de_wait_for_clear(dev_priv, BXT_DSI_PLL_ENABLE,
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| H A D | intel_psr.c | 1804 if (intel_de_wait_for_clear(dev_priv, psr_status,
2492 return intel_de_wait_for_clear(dev_priv,
2508 return intel_de_wait_for_clear(dev_priv,
2569 err = intel_de_wait_for_clear(dev_priv, reg, mask, 50);
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| H A D | intel_cx0_phy.c | 131 if (intel_de_wait_for_clear(i915, XELPDP_PORT_M2P_MSGBUS_CTL(i915, port, lane),
189 if (intel_de_wait_for_clear(i915, XELPDP_PORT_M2P_MSGBUS_CTL(i915, port, lane),
256 if (intel_de_wait_for_clear(i915, XELPDP_PORT_M2P_MSGBUS_CTL(i915, port, lane),
272 if (intel_de_wait_for_clear(i915, XELPDP_PORT_M2P_MSGBUS_CTL(i915, port, lane),
2525 if (intel_de_wait_for_clear(i915, XELPDP_PORT_M2P_MSGBUS_CTL(i915, port, lane),
2629 if (intel_de_wait_for_clear(i915, XELPDP_PORT_BUF_CTL2(i915, port),
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| H A D | intel_snps_phy.c | 41 if (intel_de_wait_for_clear(i915, DG2_PHY_MISC(phy),
1907 if (intel_de_wait_for_clear(i915, enable_reg, PLL_LOCK, 5))
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| H A D | intel_hdcp.c | 972 if (intel_de_wait_for_clear(i915,
1885 ret = intel_de_wait_for_clear(i915,
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| H A D | intel_cdclk.c | 1053 if (intel_de_wait_for_clear(dev_priv, LCPLL1_CTL, LCPLL_PLL_LOCK, 1))
1672 if (intel_de_wait_for_clear(dev_priv,
1702 if (intel_de_wait_for_clear(dev_priv, BXT_DE_PLL_ENABLE, BXT_DE_PLL_LOCK, 1))
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| H A D | intel_display_power.c | 1297 if (intel_de_wait_for_clear(dev_priv, LCPLL_CTL, LCPLL_PLL_LOCK, 1))
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| H A D | intel_display_power_well.c | 1861 if (intel_de_wait_for_clear(dev_priv, XE2LPD_PICA_PW_CTL,
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| H A D | intel_fbc.c | 283 if (intel_de_wait_for_clear(i915, FBC_STATUS,
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| H A D | icl_dsi.c | 1281 if (intel_de_wait_for_clear(dev_priv, TRANSCONF(dsi_trans),
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| H A D | intel_dpll_mgr.c | 3985 if (intel_de_wait_for_clear(i915, enable_reg, PLL_LOCK, 1))
3996 if (intel_de_wait_for_clear(i915, enable_reg, PLL_POWER_STATE, 1))
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| H A D | intel_ddi.c | 2284 ret = intel_de_wait_for_clear(i915, dp_tp_status_reg(encoder, crtc_state),
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| H A D | intel_display.c | 298 if (intel_de_wait_for_clear(dev_priv, TRANSCONF(cpu_transcoder),
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