| /linux-master/drivers/clk/imx/ |
| H A D | clk-composite-7ulp.c | 90 mux->lock = &imx_ccm_lock;
107 fd->lock = &imx_ccm_lock;
121 gate->lock = &imx_ccm_lock;
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| H A D | clk.c | 17 DEFINE_SPINLOCK(imx_ccm_lock); variable
18 EXPORT_SYMBOL_GPL(imx_ccm_lock); variable
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| H A D | clk-gate-exclusive.c | 83 gate->lock = &imx_ccm_lock;
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| H A D | clk-composite-93.c | 204 mux->lock = &imx_ccm_lock;
214 div->lock = &imx_ccm_lock;
233 gate->lock = &imx_ccm_lock;
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| H A D | clk-composite-8m.c | 229 mux->lock = &imx_ccm_lock;
256 div->lock = &imx_ccm_lock;
268 gate->lock = &imx_ccm_lock;
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| H A D | clk-imx7ulp.c | 102 hws[IMX7ULP_CLK_SPLL_BUS_CLK] = imx_clk_hw_divider_gate("spll_bus_clk", "spll_sel", CLK_SET_RATE_GATE, base + 0x604, 8, 3, 0, ulp_div_table, &imx_ccm_lock);
116 0, ulp_div_table, &imx_ccm_lock);
125 CLK_DIVIDER_READ_ONLY, ulp_div_table, &imx_ccm_lock);
127 CLK_DIVIDER_READ_ONLY, ulp_div_table, &imx_ccm_lock);
205 base + 0xac, 30, 0, &imx_ccm_lock);
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| H A D | clk.h | 9 extern spinlock_t imx_ccm_lock;
362 reg, shift, width, CLK_DIVIDER_ROUND_CLOSEST, &imx_ccm_lock);
371 reg, shift, width, 0, &imx_ccm_lock);
380 shift, clk_gate_flags, &imx_ccm_lock);
389 shift, cgr_val, 0x3, 0, &imx_ccm_lock, share_count);
398 width, clk_mux_flags, &imx_ccm_lock);
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| H A D | clk-fixup-div.c | 113 fixup_div->divider.lock = &imx_ccm_lock;
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| H A D | clk-fixup-mux.c | 93 fixup_mux->mux.lock = &imx_ccm_lock;
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| H A D | clk-busy.c | 95 busy->div.lock = &imx_ccm_lock;
175 busy->mux.lock = &imx_ccm_lock;
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| H A D | clk-imx6sll.c | 176 CLK_SET_RATE_PARENT | CLK_SET_RATE_GATE, base + 0x70, 19, 2, 0, post_div_table, &imx_ccm_lock);
178 CLK_SET_RATE_PARENT | CLK_SET_RATE_GATE, base + 0x170, 15, 1, 0, &imx_ccm_lock);
180 CLK_SET_RATE_PARENT | CLK_SET_RATE_GATE, base + 0xa0, 19, 2, 0, post_div_table, &imx_ccm_lock);
182 CLK_SET_RATE_PARENT | CLK_SET_RATE_GATE, base + 0x170, 30, 2, 0, video_div_table, &imx_ccm_lock);
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| H A D | clk-imx6ul.c | 223 base + 0xe0, 0, 2, 0, clk_enet_ref_table, &imx_ccm_lock);
225 base + 0xe0, 2, 2, 0, clk_enet_ref_table, &imx_ccm_lock);
233 CLK_SET_RATE_PARENT | CLK_SET_RATE_GATE, base + 0x70, 19, 2, 0, post_div_table, &imx_ccm_lock);
235 CLK_SET_RATE_PARENT | CLK_SET_RATE_GATE, base + 0x170, 15, 1, 0, &imx_ccm_lock);
237 CLK_SET_RATE_PARENT | CLK_SET_RATE_GATE, base + 0xa0, 19, 2, 0, post_div_table, &imx_ccm_lock);
239 CLK_SET_RATE_PARENT | CLK_SET_RATE_GATE, base + 0x170, 30, 2, 0, video_div_table, &imx_ccm_lock);
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| H A D | clk-imx6sx.c | 221 &imx_ccm_lock);
224 &imx_ccm_lock);
249 CLK_SET_RATE_PARENT, base + 0x70, 19, 2, 0, post_div_table, &imx_ccm_lock);
251 CLK_SET_RATE_PARENT, base + 0x170, 15, 1, 0, &imx_ccm_lock);
253 CLK_SET_RATE_PARENT, base + 0xa0, 19, 2, 0, post_div_table, &imx_ccm_lock);
255 CLK_SET_RATE_PARENT, base + 0x170, 30, 2, 0, video_div_table, &imx_ccm_lock);
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| H A D | clk-imx6sl.c | 267 hws[IMX6SL_CLK_PLL4_POST_DIV] = clk_hw_register_divider_table(NULL, "pll4_post_div", "pll4_audio", CLK_SET_RATE_PARENT, base + 0x70, 19, 2, 0, post_div_table, &imx_ccm_lock);
268 hws[IMX6SL_CLK_PLL4_AUDIO_DIV] = clk_hw_register_divider(NULL, "pll4_audio_div", "pll4_post_div", CLK_SET_RATE_PARENT, base + 0x170, 15, 1, 0, &imx_ccm_lock);
269 hws[IMX6SL_CLK_PLL5_POST_DIV] = clk_hw_register_divider_table(NULL, "pll5_post_div", "pll5_video", CLK_SET_RATE_PARENT, base + 0xa0, 19, 2, 0, post_div_table, &imx_ccm_lock);
270 hws[IMX6SL_CLK_PLL5_VIDEO_DIV] = clk_hw_register_divider_table(NULL, "pll5_video_div", "pll5_post_div", CLK_SET_RATE_PARENT, base + 0x170, 30, 2, 0, video_div_table, &imx_ccm_lock);
271 hws[IMX6SL_CLK_ENET_REF] = clk_hw_register_divider_table(NULL, "enet_ref", "pll6_enet", 0, base + 0xe0, 0, 2, 0, clk_enet_ref_table, &imx_ccm_lock);
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| H A D | clk-gate-93.c | 172 gate->lock = &imx_ccm_lock;
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| H A D | clk-imx7d.c | 430 CLK_SET_RATE_PARENT | CLK_SET_RATE_GATE, base + 0x70, 21, 2, 0, test_div_table, &imx_ccm_lock);
432 CLK_SET_RATE_PARENT | CLK_SET_RATE_GATE, base + 0xf0, 19, 2, 0, test_div_table, &imx_ccm_lock);
434 CLK_SET_RATE_PARENT | CLK_SET_RATE_GATE, base + 0xf0, 22, 2, 0, post_div_table, &imx_ccm_lock);
436 CLK_SET_RATE_PARENT | CLK_SET_RATE_GATE, base + 0x130, 19, 2, 0, test_div_table, &imx_ccm_lock);
438 CLK_SET_RATE_PARENT | CLK_SET_RATE_GATE, base + 0x130, 22, 2, 0, post_div_table, &imx_ccm_lock);
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| H A D | clk-imx6q.c | 547 &imx_ccm_lock);
598 hws[IMX6QDL_CLK_PLL4_POST_DIV] = clk_hw_register_divider_table(NULL, "pll4_post_div", "pll4_audio", CLK_SET_RATE_PARENT, base + 0x70, 19, 2, 0, post_div_table, &imx_ccm_lock);
602 hws[IMX6QDL_CLK_PLL4_AUDIO_DIV] = clk_hw_register_divider(NULL, "pll4_audio_div", "pll4_post_div", CLK_SET_RATE_PARENT, base + 0x170, 15, 1, 0, &imx_ccm_lock);
603 hws[IMX6QDL_CLK_PLL5_POST_DIV] = clk_hw_register_divider_table(NULL, "pll5_post_div", "pll5_video", CLK_SET_RATE_PARENT, base + 0xa0, 19, 2, 0, post_div_table, &imx_ccm_lock);
604 hws[IMX6QDL_CLK_PLL5_VIDEO_DIV] = clk_hw_register_divider_table(NULL, "pll5_video_div", "pll5_post_div", CLK_SET_RATE_PARENT, base + 0x170, 30, 2, 0, video_div_table, &imx_ccm_lock);
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| H A D | clk-vf610.c | 278 clk[VF610_CLK_PLL4_MAIN_DIV] = clk_register_divider_table(NULL, "pll4_audio_div", "pll4_audio", 0, CCM_CACRR, 6, 3, 0, pll4_audio_div_table, &imx_ccm_lock);
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| H A D | clk-imx8ulp.c | 56 /* Set to imx_ccm_lock to protect register access shared with clock control */
135 pcc_reset->lock = &imx_ccm_lock;
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