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0b805610 |
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17-Aug-2020 |
Krzysztof Kozlowski <krzk@kernel.org> |
clk: imx: vf610: Add CRC clock Add the clock for CRC block allowing it to be enabled by consumers. Signed-off-by: Krzysztof Kozlowski <krzk@kernel.org> Signed-off-by: Shawn Guo <shawnguo@kernel.org>
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7d6b5e4f |
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04-Aug-2020 |
Anson Huang <Anson.Huang@nxp.com> |
clk: imx: Explicitly include bits.h It is better to explicitly include the required header file rather then get it through some recursive include. Signed-off-by: Anson Huang <Anson.Huang@nxp.com> Acked-by: Stephen Boyd <sboyd@kernel.org> Signed-off-by: Shawn Guo <shawnguo@kernel.org>
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018e4308 |
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01-Jun-2020 |
Andrey Smirnov <andrew.smirnov@gmail.com> |
clk: imx: vf610: add CAAM clock According to Vybrid Security RM, CCM_CCGR11[CG176] can be used to gate CAAM ipg clock. Signed-off-by: Horia Geantă <horia.geanta@nxp.com> Signed-off-by: Andrey Smirnov <andrew.smirnov@gmail.com> Cc: Chris Healy <cphealy@gmail.com> Cc: Shawn Guo <shawnguo@kernel.org> Cc: Fabio Estevam <festevam@gmail.com> Cc: linux-arm-kernel@lists.infradead.org Cc: linux-kernel@vger.kernel.org Cc: linux-imx@nxp.com Tested-by: Chris Healy <cphealy@gmail.com> Signed-off-by: Shawn Guo <shawnguo@kernel.org>
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2874c5fd |
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27-May-2019 |
Thomas Gleixner <tglx@linutronix.de> |
treewide: Replace GPLv2 boilerplate/reference with SPDX - rule 152 Based on 1 normalized pattern(s): this program is free software you can redistribute it and or modify it under the terms of the gnu general public license as published by the free software foundation either version 2 of the license or at your option any later version extracted by the scancode license scanner the SPDX license identifier GPL-2.0-or-later has been chosen to replace the boilerplate/reference in 3029 file(s). Signed-off-by: Thomas Gleixner <tglx@linutronix.de> Reviewed-by: Allison Randal <allison@lohutok.net> Cc: linux-spdx@vger.kernel.org Link: https://lkml.kernel.org/r/20190527070032.746973796@linutronix.de Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
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56717702 |
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26-Dec-2018 |
Yangtao Li <tiny.windzz@gmail.com> |
clk: vf610: fix refcount leak in vf610_clocks_init() The of_find_compatible_node() returns a node pointer with refcount incremented, but there is the lack of use of the of_node_put() when done. Add the missing of_node_put() to release the refcount. Signed-off-by: Yangtao Li <tiny.windzz@gmail.com> Fixes: 1f2c5fd5f048 ("ARM: imx: add VF610 clock support") Signed-off-by: Stephen Boyd <sboyd@kernel.org>
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fdda6ee9 |
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27-Aug-2017 |
Arvind Yadav <arvind.yadav.cs@gmail.com> |
clk: imx: constify clk_div_table clk_div_table are not supposed to change at runtime. All functions working with clk_div_table provided by <linux/clk-provider.h> work with const clk_div_table. So mark the non-const structs as const. Signed-off-by: Arvind Yadav <arvind.yadav.cs@gmail.com> Acked-by: Shawn Guo <shawnguo@kernel.org> Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>
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#
c77cbdd1 |
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19-Dec-2016 |
Nikita Yushchenko <nikita.yoush@cogentembedded.com> |
clk: imx: pllv3: support fractional multiplier on vf610 PLL1/PLL2 On vf610, PLL1 and PLL2 have registers to configure fractional part of frequency multiplier. This patch adds support for these registers. This fixes "fast system clock" issue on boards where bootloader sets fractional multiplier for PLL1. Suggested-by: Andrey Smirnov <andrew.smirnov@gmail.com> CC: Chris Healy <cphealy@gmail.com> Signed-off-by: Nikita Yushchenko <nikita.yoush@cogentembedded.com> Tested-by: Andrey Smirnov <andrew.smirnov@gmail.com> Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>
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a0649829 |
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27-Jun-2016 |
Stefan Agner <stefan@agner.ch> |
clk: imx: vf610: Disable automatic clock gating for lpuart in LPSTOP mode In order to allow wake support in STOP sleep mode, clocks are needed. Use imx_clk_gate2_cgr to disable automatic clock gating in low power mode STOP. This allows to enable wake by UART using: echo enabled > /sys/class/tty/ttyLP0/power/wakeup However, if wake is not enabled, the driver should disable the clocks explicitly to save power. Signed-off-by: Stefan Agner <stefan@agner.ch> Signed-off-by: Bhuvanchandra DV <bhuvanchandra.dv@toradex.com> Signed-off-by: Michael Turquette <mturquette@baylibre.com> Link: lkml.kernel.org/r/20160628053235.5114-3-bhuvanchandra.dv@toradex.com
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afd7350a |
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11-Apr-2016 |
Stefan Agner <stefan@agner.ch> |
clk: imx: vf610: add TCON ipg clock Add the ipg (bus) clock for the TCON modules (Timing Controller). This module is required by the new DCU DRM driver, since the display signals pass through TCON. Signed-off-by: Stefan Agner <stefan@agner.ch> Signed-off-by: Shawn Guo <shawnguo@kernel.org>
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3218b21a |
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04-Apr-2016 |
Stefan Agner <stefan@agner.ch> |
clk: imx: vf610: fix DCU clock tree Similar to an earlier fix for the SAI clocks, the DCU clock hierarchy mixes the bus clock with the display controllers pixel clock. Tests have shown that the gates in CCM_CCGR3/9 registers do not control the DCU pixel clock, but only the register access clock (bus clock). Fix this by defining the parent clock of VF610_CLK_DCUx to be the bus clock (ipg_bus). Since the clock has not been used far, there are no further changes needed. Signed-off-by: Stefan Agner <stefan@agner.ch> Signed-off-by: Shawn Guo <shawnguo@kernel.org>
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4cfe6aeb |
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09-Mar-2016 |
Stefan Agner <stefan@agner.ch> |
clk: imx: vf610: add suspend/resume support The clock register are lost when enterying LPSTOPx, hence provide suspend/resume functions restoring them. The clock gates get restored by the individual driver, hence we do not need to restore them here. Signed-off-by: Stefan Agner <stefan@agner.ch> Signed-off-by: Shawn Guo <shawnguo@kernel.org>
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349efbee |
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09-Mar-2016 |
Stefan Agner <stefan@agner.ch> |
clk: imx: vf610: add WKPU unit Signed-off-by: Stefan Agner <stefan@agner.ch> Acked-by: Stephen Boyd <sboyd@codeaurora.org> Signed-off-by: Shawn Guo <shawnguo@kernel.org>
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0da15d36 |
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09-Mar-2016 |
Stefan Agner <stefan@agner.ch> |
clk: imx: vf610: leave DDR clock on To use STOP mode without putting DDR3 into self-refresh mode, we need to keep the DDR clock enabled. Use the new gate configuration with a value of 2 to make sure that the clock is enabled in RUN, WAIT and STOP mode. Signed-off-by: Stefan Agner <stefan@agner.ch> Signed-off-by: Shawn Guo <shawnguo@kernel.org>
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3b60a26f |
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17-Oct-2015 |
Stefan Agner <stefan@agner.ch> |
ARM: imx: clk-vf610: fix SAI clock tree The Synchronous Audio Interface (SAI) instances are clocked by independent clocks: The bus clock and the audio clock (as shown in Figure 51-1 in the Vybrid Reference Manual). The clock gates in CCGR0/CCGR1 for SAI0 through SAI3 are bus clock gates, as access tests to the registers with/without gating those clocks have shown. The audio clock is gated by the SAIx_EN gates in CCM_CSCDR1, followed by a clock divider (SAIx_DIV). Currently, the parent of the bus clock gates has been assigned to SAIx_DIV, which is not involved in the bus clock path for the SAI instances (see chapter 9.10.12, SAI clocking in the Vybrid Reference Manual). Fix this by define the parent clock of VF610_CLK_SAIx to be the bus clock. If the driver needs the audio clock (when used in master mode), a fixed device tree is required which assign the audio clock properly to VF610_CLK_SAIx_DIV. Signed-off-by: Stefan Agner <stefan@agner.ch> Acked-by: Stephen Boyd <sboyd@codeaurora.org> Signed-off-by: Shawn Guo <shawnguo@kernel.org>
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0753f56e |
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07-Sep-2015 |
Sanchayan Maity <maitysanchayan@gmail.com> |
clk: clk-vf610: Add clock for Vybrid OCOTP controller Add clock support for Vybrid On-Chip One Time Programmable (OCOTP) controller. While the OCOTP block does not require explicit clock gating, for programming the OCOTP timing register the clock rate of ipg clock is required for timing calculations related to fuse and shadow register read sequence. We explicitly specify the ipg clock for OCOTP as a result. Signed-off-by: Sanchayan Maity <maitysanchayan@gmail.com> Signed-off-by: Shawn Guo <shawnguo@kernel.org>
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fbfd617e |
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20-May-2015 |
Mirza Krak <mirza.krak@hostmobility.com> |
ARM: imx: clk-v610: Add clock for I2C2 and I2C3 Add support for clock gating of I2C2 and I2C3. We use I2C2 in a (not yet mainlined) device tree. Signed-off-by: Mirza Krak <mirza.krak@hostmobility.com> Signed-off-by: Shawn Guo <shawn.guo@linaro.org>
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d930d568 |
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17-May-2015 |
Stefan Agner <stefan@agner.ch> |
ARM: imx: clk-vf610: enable debug access port by default Enabled DAP (debug access port) by default. This enables the hw- breakpoint framework to make use of the breakpoints and watchpoints supported by hardware. [ 0.215805] hw-breakpoint: found 2 (+1 reserved) breakpoint and 1 watchpoint registers. [ 0.224624] hw-breakpoint: maximum watchpoint size is 4 bytes. Without this clock, the hw-breakpoint driver claims an undefined instruction during initialization: [ 0.227380] hw-breakpoint: Debug register access (0xee003e17) caused undefined instruction on CPU 0 [ 0.227519] hw-breakpoint: CPU 0 failed to disable vector catch Signed-off-by: Stefan Agner <stefan@agner.ch> Signed-off-by: Shawn Guo <shawn.guo@linaro.org>
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11f68120 |
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26-Apr-2015 |
Shawn Guo <shawn.guo@linaro.org> |
ARM: imx: move clock drivers into drivers/clk After the cleanup on clock drivers, they are now ready to be moved into drivers/clk. Let's move them into drivers/clk/imx folder. Signed-off-by: Shawn Guo <shawn.guo@linaro.org> Acked-by: Stephen Boyd <sboyd@codeaurora.org>
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