/linux-master/drivers/pwm/ |
H A D | pwm-vt8500.c | 108 writel(prescale, vt8500->base + REG_SCALAR(pwm->hwpwm)); 109 vt8500_pwm_busy_wait(chip, pwm->hwpwm, STATUS_SCALAR_UPDATE); 111 writel(pv, vt8500->base + REG_PERIOD(pwm->hwpwm)); 112 vt8500_pwm_busy_wait(chip, pwm->hwpwm, STATUS_PERIOD_UPDATE); 114 writel(dc, vt8500->base + REG_DUTY(pwm->hwpwm)); 115 vt8500_pwm_busy_wait(chip, pwm->hwpwm, STATUS_DUTY_UPDATE); 117 val = readl(vt8500->base + REG_CTRL(pwm->hwpwm)); 119 writel(val, vt8500->base + REG_CTRL(pwm->hwpwm)); 120 vt8500_pwm_busy_wait(chip, pwm->hwpwm, STATUS_CTRL_UPDATE); 138 val = readl(vt8500->base + REG_CTRL(pwm->hwpwm)); [all...] |
H A D | pwm-jz4740.c | 56 if (!jz4740_pwm_can_use_chn(chip, pwm->hwpwm)) 59 snprintf(name, sizeof(name), "timer%u", pwm->hwpwm); 74 jz->clk[pwm->hwpwm] = clk; 82 struct clk *clk = jz->clk[pwm->hwpwm]; 93 regmap_set_bits(jz->map, TCU_REG_TCSRc(pwm->hwpwm), TCU_TCSR_PWM_EN); 96 regmap_write(jz->map, TCU_REG_TESR, BIT(pwm->hwpwm)); 109 regmap_write(jz->map, TCU_REG_TDHRc(pwm->hwpwm), 0xffff); 110 regmap_write(jz->map, TCU_REG_TDFRc(pwm->hwpwm), 0x0); 117 regmap_clear_bits(jz->map, TCU_REG_TCSRc(pwm->hwpwm), TCU_TCSR_PWM_EN); 120 regmap_write(jz->map, TCU_REG_TECR, BIT(pwm->hwpwm)); [all...] |
H A D | pwm-dwc-core.c | 70 __dwc_pwm_set_enable(dwc, pwm->hwpwm, false); 78 dwc_pwm_writel(dwc, low, DWC_TIM_LD_CNT(pwm->hwpwm)); 79 dwc_pwm_writel(dwc, high, DWC_TIM_LD_CNT2(pwm->hwpwm)); 88 dwc_pwm_writel(dwc, ctrl, DWC_TIM_CTRL(pwm->hwpwm)); 93 __dwc_pwm_set_enable(dwc, pwm->hwpwm, state->enabled); 112 __dwc_pwm_set_enable(dwc, pwm->hwpwm, false); 129 ctrl = dwc_pwm_readl(dwc, DWC_TIM_CTRL(pwm->hwpwm)); 130 ld = dwc_pwm_readl(dwc, DWC_TIM_LD_CNT(pwm->hwpwm)); 131 ld2 = dwc_pwm_readl(dwc, DWC_TIM_LD_CNT2(pwm->hwpwm));
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H A D | pwm-sprd.c | 75 struct sprd_pwm_chn *chn = &spc->chn[pwm->hwpwm]; 87 pwm->hwpwm); 91 val = sprd_pwm_read(spc, pwm->hwpwm, SPRD_PWM_ENABLE); 105 val = sprd_pwm_read(spc, pwm->hwpwm, SPRD_PWM_PRESCALE); 110 val = sprd_pwm_read(spc, pwm->hwpwm, SPRD_PWM_DUTY); 126 struct sprd_pwm_chn *chn = &spc->chn[pwm->hwpwm]; 156 sprd_pwm_write(spc, pwm->hwpwm, SPRD_PWM_PRESCALE, prescale); 157 sprd_pwm_write(spc, pwm->hwpwm, SPRD_PWM_MOD, SPRD_PWM_MOD_MAX); 158 sprd_pwm_write(spc, pwm->hwpwm, SPRD_PWM_DUTY, duty); 167 struct sprd_pwm_chn *chn = &spc->chn[pwm->hwpwm]; [all...] |
H A D | pwm-sunplus.c | 68 mode0 &= ~SP7021_PWM_MODE0_PWMEN(pwm->hwpwm); 72 mode1 &= ~SP7021_PWM_MODE1_CNT_EN(pwm->hwpwm); 100 writel(dd_freq, priv->base + SP7021_PWM_FREQ(pwm->hwpwm)); 104 mode0 |= SP7021_PWM_MODE0_PWMEN(pwm->hwpwm); 106 mode1 |= SP7021_PWM_MODE1_CNT_EN(pwm->hwpwm); 109 mode0 |= SP7021_PWM_MODE0_BYPASS(pwm->hwpwm); 110 duty = SP7021_PWM_DUTY_DD_SEL(pwm->hwpwm) | SP7021_PWM_DUTY_MAX; 112 mode0 &= ~SP7021_PWM_MODE0_BYPASS(pwm->hwpwm); 118 duty = SP7021_PWM_DUTY_DD_SEL(pwm->hwpwm) | duty; 120 writel(duty, priv->base + SP7021_PWM_DUTY(pwm->hwpwm)); [all...] |
H A D | pwm-bcm-iproc.c | 79 if (value & BIT(IPROC_PWM_CTRL_EN_SHIFT(pwm->hwpwm))) 84 if (value & BIT(IPROC_PWM_CTRL_POLARITY_SHIFT(pwm->hwpwm))) 97 prescale = value >> IPROC_PWM_PRESCALE_SHIFT(pwm->hwpwm); 102 value = readl(ip->base + IPROC_PWM_PERIOD_OFFSET(pwm->hwpwm)); 106 value = readl(ip->base + IPROC_PWM_DUTY_CYCLE_OFFSET(pwm->hwpwm)); 154 iproc_pwmc_disable(ip, pwm->hwpwm); 158 value &= ~IPROC_PWM_PRESCALE_MASK(pwm->hwpwm); 159 value |= prescale << IPROC_PWM_PRESCALE_SHIFT(pwm->hwpwm); 163 writel(period, ip->base + IPROC_PWM_PERIOD_OFFSET(pwm->hwpwm)); 164 writel(duty, ip->base + IPROC_PWM_DUTY_CYCLE_OFFSET(pwm->hwpwm)); [all...] |
H A D | pwm-stmpe.c | 47 pwm->hwpwm); 51 value = ret | BIT(pwm->hwpwm); 56 pwm->hwpwm); 73 pwm->hwpwm); 77 value = ret & ~BIT(pwm->hwpwm); 82 pwm->hwpwm); 117 pin = pwm->hwpwm; 128 pwm->hwpwm); 134 switch (pwm->hwpwm) { 153 pwm->hwpwm, duty_n [all...] |
H A D | pwm-sun4i.c | 129 if ((val & BIT_CH(PWM_BYPASS, pwm->hwpwm)) && 138 if ((PWM_REG_PRESCAL(val, pwm->hwpwm) == PWM_PRESCAL_MASK) && 142 prescaler = prescaler_table[PWM_REG_PRESCAL(val, pwm->hwpwm)]; 147 if (val & BIT_CH(PWM_ACT_STATE, pwm->hwpwm)) 152 if ((val & BIT_CH(PWM_CLK_GATING | PWM_EN, pwm->hwpwm)) == 153 BIT_CH(PWM_CLK_GATING | PWM_EN, pwm->hwpwm)) 158 val = sun4i_pwm_readl(sun4ichip, PWM_CH_PRD(pwm->hwpwm)); 266 ctrl |= BIT_CH(PWM_BYPASS, pwm->hwpwm); 273 ctrl &= ~BIT_CH(PWM_BYPASS, pwm->hwpwm); 276 if (PWM_REG_PRESCAL(ctrl, pwm->hwpwm) ! [all...] |
H A D | pwm-visconti.c | 52 writel(0, priv->base + PIPGM_PCSR(pwm->hwpwm)); 98 writel(pwmc0, priv->base + PIPGM_PWMC(pwm->hwpwm)); 99 writel(duty_cycle, priv->base + PIPGM_PDUT(pwm->hwpwm)); 100 writel(period, priv->base + PIPGM_PCSR(pwm->hwpwm)); 111 period = readl(priv->base + PIPGM_PCSR(pwm->hwpwm)); 112 duty = readl(priv->base + PIPGM_PDUT(pwm->hwpwm)); 113 pwmc0 = readl(priv->base + PIPGM_PWMC(pwm->hwpwm));
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H A D | pwm-atmel.c | 246 val = atmel_pwm_ch_readl(atmel_pwm, pwm->hwpwm, PWM_CMR); 248 atmel_pwm_ch_writel(atmel_pwm, pwm->hwpwm, PWM_CMR, val); 251 atmel_pwm_ch_writel(atmel_pwm, pwm->hwpwm, 253 atmel_pwm_set_pending(atmel_pwm, pwm->hwpwm); 262 atmel_pwm_ch_writel(atmel_pwm, pwm->hwpwm, 264 atmel_pwm_ch_writel(atmel_pwm, pwm->hwpwm, 274 atmel_pwm_wait_nonpending(atmel_pwm, pwm->hwpwm); 276 atmel_pwm_writel(atmel_pwm, PWM_DIS, 1 << pwm->hwpwm); 284 while ((atmel_pwm_readl(atmel_pwm, PWM_SR) & (1 << pwm->hwpwm)) && 306 u32 cmr = atmel_pwm_ch_readl(atmel_pwm, pwm->hwpwm, PWM_CM [all...] |
H A D | pwm-berlin.c | 100 value = berlin_pwm_readl(bpc, pwm->hwpwm, BERLIN_PWM_CONTROL); 105 berlin_pwm_writel(bpc, pwm->hwpwm, value, BERLIN_PWM_CONTROL); 107 berlin_pwm_writel(bpc, pwm->hwpwm, duty, BERLIN_PWM_DUTY); 108 berlin_pwm_writel(bpc, pwm->hwpwm, period, BERLIN_PWM_TCNT); 120 value = berlin_pwm_readl(bpc, pwm->hwpwm, BERLIN_PWM_CONTROL); 127 berlin_pwm_writel(bpc, pwm->hwpwm, value, BERLIN_PWM_CONTROL); 137 value = berlin_pwm_readl(bpc, pwm->hwpwm, BERLIN_PWM_EN); 139 berlin_pwm_writel(bpc, pwm->hwpwm, value, BERLIN_PWM_EN); 150 value = berlin_pwm_readl(bpc, pwm->hwpwm, BERLIN_PWM_EN); 152 berlin_pwm_writel(bpc, pwm->hwpwm, valu [all...] |
H A D | pwm-lp3943.c | 34 lp3943_pwm_request_map(struct lp3943_pwm *lp3943_pwm, int hwpwm) argument 38 struct lp3943_pwm_map *pwm_map = &lp3943_pwm->pwm_map[hwpwm]; 41 pwm_map->output = pdata->pwms[hwpwm]->output; 42 pwm_map->num_outputs = pdata->pwms[hwpwm]->num_outputs; 60 pwm_map = lp3943_pwm_request_map(lp3943_pwm, pwm->hwpwm); 82 struct lp3943_pwm_map *pwm_map = &lp3943_pwm->pwm_map[pwm->hwpwm]; 105 if (pwm->hwpwm == 0) { 154 struct lp3943_pwm_map *pwm_map = &lp3943_pwm->pwm_map[pwm->hwpwm]; 157 if (pwm->hwpwm == 0) 173 struct lp3943_pwm_map *pwm_map = &lp3943_pwm->pwm_map[pwm->hwpwm]; [all...] |
H A D | pwm-microchip-core.c | 81 reg_offset = MCHPCOREPWM_EN(pwm->hwpwm >> 3); 82 shift = pwm->hwpwm & 7; 89 mchp_core_pwm->channel_enabled &= ~BIT(pwm->hwpwm); 90 mchp_core_pwm->channel_enabled |= enable << pwm->hwpwm; 97 if (mchp_core_pwm->sync_update_mask & (1 << pwm->hwpwm)) 180 writel_relaxed(posedge, mchp_core_pwm->base + MCHPCOREPWM_POSEDGE(pwm->hwpwm)); 181 writel_relaxed(negedge, mchp_core_pwm->base + MCHPCOREPWM_NEGEDGE(pwm->hwpwm)); 310 period_locked = mchp_core_pwm->channel_enabled & ~(1 << pwm->hwpwm); 367 mchp_core_pwm_wait_for_sync_update(mchp_core_pwm, pwm->hwpwm); 386 mchp_core_pwm_wait_for_sync_update(mchp_core_pwm, pwm->hwpwm); [all...] |
H A D | pwm-twl.c | 82 base = pwm->hwpwm * 3; 106 val |= TWL4030_PWM_TOGGLE(pwm->hwpwm, TWL4030_PWMXCLK_ENABLE); 112 val |= TWL4030_PWM_TOGGLE(pwm->hwpwm, TWL4030_PWMX_ENABLE); 136 val &= ~TWL4030_PWM_TOGGLE(pwm->hwpwm, TWL4030_PWMX_ENABLE); 142 val &= ~TWL4030_PWM_TOGGLE(pwm->hwpwm, TWL4030_PWMXCLK_ENABLE); 158 if (pwm->hwpwm == 1) { 196 if (pwm->hwpwm == 1) 228 val |= TWL6030_PWM_TOGGLE(pwm->hwpwm, TWL6030_PWMXS | TWL6030_PWMXEN); 229 val &= ~TWL6030_PWM_TOGGLE(pwm->hwpwm, TWL6030_PWMXR); 251 val |= TWL6030_PWM_TOGGLE(pwm->hwpwm, TWL6030_PWMX [all...] |
H A D | pwm-rz-mtu3.c | 132 rz_mtu3_get_channel(struct rz_mtu3_pwm_chip *rz_mtu3_pwm, u32 hwpwm) argument 138 if (priv->map->base_pwm_number + priv->map->num_channel_ios > hwpwm) 146 u32 hwpwm) 152 priv = rz_mtu3_get_channel(rz_mtu3_pwm, hwpwm); 157 if (priv->map->base_pwm_number == hwpwm) 172 priv = rz_mtu3_get_channel(rz_mtu3_pwm, pwm->hwpwm); 201 priv = rz_mtu3_get_channel(rz_mtu3_pwm, pwm->hwpwm); 224 priv = rz_mtu3_get_channel(rz_mtu3_pwm, pwm->hwpwm); 229 if (priv->map->base_pwm_number == pwm->hwpwm) 250 priv = rz_mtu3_get_channel(rz_mtu3_pwm, pwm->hwpwm); 145 rz_mtu3_pwm_is_ch_enabled(struct rz_mtu3_pwm_chip *rz_mtu3_pwm, u32 hwpwm) argument [all...] |
H A D | pwm-bcm2835.c | 43 value &= ~(PWM_CONTROL_MASK << PWM_CONTROL_SHIFT(pwm->hwpwm)); 44 value |= (PWM_MODE << PWM_CONTROL_SHIFT(pwm->hwpwm)); 56 value &= ~(PWM_CONTROL_MASK << PWM_CONTROL_SHIFT(pwm->hwpwm)); 96 writel(period_cycles, pc->base + PERIOD(pwm->hwpwm)); 100 writel(val, pc->base + DUTY(pwm->hwpwm)); 106 val &= ~(PWM_POLARITY << PWM_CONTROL_SHIFT(pwm->hwpwm)); 108 val |= PWM_POLARITY << PWM_CONTROL_SHIFT(pwm->hwpwm); 112 val |= PWM_ENABLE << PWM_CONTROL_SHIFT(pwm->hwpwm); 114 val &= ~(PWM_ENABLE << PWM_CONTROL_SHIFT(pwm->hwpwm));
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H A D | pwm-spear.c | 126 spear_pwm_writel(pc, pwm->hwpwm, PWMCR, 128 spear_pwm_writel(pc, pwm->hwpwm, PWMDCR, dc); 129 spear_pwm_writel(pc, pwm->hwpwm, PWMPCR, pv); 145 val = spear_pwm_readl(pc, pwm->hwpwm, PWMCR); 147 spear_pwm_writel(pc, pwm->hwpwm, PWMCR, val); 157 val = spear_pwm_readl(pc, pwm->hwpwm, PWMCR); 159 spear_pwm_writel(pc, pwm->hwpwm, PWMCR, val);
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H A D | pwm-mediatek.c | 87 ret = clk_prepare_enable(pc->clk_pwms[pwm->hwpwm]); 106 clk_disable_unprepare(pc->clk_pwms[pwm->hwpwm]); 138 do_div(resolution, clk_get_rate(pc->clk_pwms[pwm->hwpwm])); 154 if (pc->soc->pwm45_fixup && pwm->hwpwm > 2) { 164 pwm_mediatek_writel(pc, pwm->hwpwm, PWMCON, BIT(15) | clkdiv); 165 pwm_mediatek_writel(pc, pwm->hwpwm, reg_width, cnt_period); 166 pwm_mediatek_writel(pc, pwm->hwpwm, reg_thres, cnt_duty); 184 value |= BIT(pwm->hwpwm); 196 value &= ~BIT(pwm->hwpwm);
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H A D | pwm-hibvt.c | 86 hibvt_pwm_set_bits(hi_pwm_chip->base, PWM_CTRL_ADDR(pwm->hwpwm), 94 hibvt_pwm_set_bits(hi_pwm_chip->base, PWM_CTRL_ADDR(pwm->hwpwm), 109 hibvt_pwm_set_bits(hi_pwm_chip->base, PWM_CFG0_ADDR(pwm->hwpwm), 112 hibvt_pwm_set_bits(hi_pwm_chip->base, PWM_CFG1_ADDR(pwm->hwpwm), 123 hibvt_pwm_set_bits(hi_pwm_chip->base, PWM_CTRL_ADDR(pwm->hwpwm), 126 hibvt_pwm_set_bits(hi_pwm_chip->base, PWM_CTRL_ADDR(pwm->hwpwm), 140 value = readl(base + PWM_CFG0_ADDR(pwm->hwpwm)); 143 value = readl(base + PWM_CFG1_ADDR(pwm->hwpwm)); 146 value = readl(base + PWM_CTRL_ADDR(pwm->hwpwm));
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H A D | pwm-lpc18xx-sct.c | 140 val &= ~LPC18XX_PWM_RES_MASK(pwm->hwpwm); 141 val |= LPC18XX_PWM_RES(pwm->hwpwm, action); 173 struct lpc18xx_pwm_data *lpc18xx_data = &lpc18xx_pwm->channeldata[pwm->hwpwm]; 216 pwm->hwpwm); 237 struct lpc18xx_pwm_data *lpc18xx_data = &lpc18xx_pwm->channeldata[pwm->hwpwm]; 260 lpc18xx_pwm_writel(lpc18xx_pwm, LPC18XX_PWM_OUTPUTSET(pwm->hwpwm), 262 lpc18xx_pwm_writel(lpc18xx_pwm, LPC18XX_PWM_OUTPUTCL(pwm->hwpwm), 272 struct lpc18xx_pwm_data *lpc18xx_data = &lpc18xx_pwm->channeldata[pwm->hwpwm]; 276 lpc18xx_pwm_writel(lpc18xx_pwm, LPC18XX_PWM_OUTPUTSET(pwm->hwpwm), 0); 277 lpc18xx_pwm_writel(lpc18xx_pwm, LPC18XX_PWM_OUTPUTCL(pwm->hwpwm), [all...] |
H A D | pwm-samsung.c | 123 unsigned int tcon_chan = to_tcon_channel(pwm->hwpwm); 233 if (!(our_chip->variant.output_mask & BIT(pwm->hwpwm))) { 236 pwm->hwpwm); 240 memset(&our_chip->channel[pwm->hwpwm], 0, sizeof(our_chip->channel[pwm->hwpwm])); 248 unsigned int tcon_chan = to_tcon_channel(pwm->hwpwm); 264 our_chip->disabled_mask &= ~BIT(pwm->hwpwm); 274 unsigned int tcon_chan = to_tcon_channel(pwm->hwpwm); 288 if (readl(our_chip->base + REG_TCMPB(pwm->hwpwm)) == (u32)-1U) 291 our_chip->disabled_mask |= BIT(pwm->hwpwm); [all...] |
H A D | pwm-sti.c | 191 ((ncfg == 1) && (pwm->hwpwm == cur->hwpwm)) || 192 ((ncfg == 1) && (pwm->hwpwm != cur->hwpwm) && period_same) || 229 ret = regmap_write(pc->regmap, PWM_OUT_VAL(pwm->hwpwm), value); 235 set_bit(pwm->hwpwm, &pc->configured); 274 pwm->hwpwm, ret); 309 clear_bit(pwm->hwpwm, &pc->configured); 317 struct sti_cpt_ddata *ddata = &cdata->ddata[pwm->hwpwm]; 323 if (pwm->hwpwm > [all...] |
H A D | pwm-mxs.c | 71 writel(1 << pwm->hwpwm, mxs->base + PWM_CTRL + CLR); 100 mxs->base + PWM_ACTIVE0 + pwm->hwpwm * 0x20); 102 mxs->base + PWM_PERIOD0 + pwm->hwpwm * 0x20); 110 writel(1 << pwm->hwpwm, mxs->base + PWM_CTRL + SET);
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H A D | sysfs.c | 263 dev_set_name(&export->child, "pwm%u", pwm->hwpwm); 272 pwm_prop[0] = kasprintf(GFP_KERNEL, "EXPORT=pwm%u", pwm->hwpwm); 297 pwm_prop[0] = kasprintf(GFP_KERNEL, "UNEXPORT=pwm%u", pwm->hwpwm); 316 unsigned int hwpwm; local 319 ret = kstrtouint(buf, 0, &hwpwm); 323 if (hwpwm >= chip->npwm) 326 pwm = pwm_request_from_chip(chip, hwpwm, "sysfs"); 343 unsigned int hwpwm; local 346 ret = kstrtouint(buf, 0, &hwpwm); 350 if (hwpwm > [all...] |
/linux-master/drivers/staging/greybus/ |
H A D | pwm.c | 179 return gb_pwm_activate_operation(chip, pwm->hwpwm); 187 gb_pwm_deactivate_operation(chip, pwm->hwpwm); 201 gb_pwm_disable_operation(chip, pwm->hwpwm); 204 err = gb_pwm_set_polarity_operation(chip, pwm->hwpwm, state->polarity); 211 gb_pwm_disable_operation(chip, pwm->hwpwm); 227 err = gb_pwm_config_operation(chip, pwm->hwpwm, duty_cycle, period); 233 return gb_pwm_enable_operation(chip, pwm->hwpwm);
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