/linux-master/drivers/gpu/drm/amd/amdgpu/ |
H A D | sdma_v4_4_2.c | 2235 .hwip = ACA_HWIP_TYPE_SMU,
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H A D | gfx_v9_0.c | 4927 reg = adev->reg_offset[entry->hwip][entry->instance][entry->segment] + entry->reg;
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H A D | gfx_v10_0.c | 7976 reg = adev->reg_offset[entry->hwip][entry->instance][entry->segment] + entry->reg;
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H A D | soc21.c | 317 if (!adev->reg_offset[en->hwip][en->inst]) 319 else if (reg_offset != (adev->reg_offset[en->hwip][en->inst][en->seg]
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H A D | umc_v12_0.c | 536 .hwip = ACA_HWIP_TYPE_UMC,
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H A D | soc15.c | 421 if (!adev->reg_offset[en->hwip][en->inst]) 423 else if (reg_offset != (adev->reg_offset[en->hwip][en->inst][en->seg] 457 reg = adev->reg_offset[entry->hwip][entry->instance][entry->segment] + entry->reg; 462 tmp = (entry->hwip == GC_HWIP) ? 475 (entry->hwip == GC_HWIP) ?
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H A D | mmhub_v1_8.c | 768 .hwip = ACA_HWIP_TYPE_SMU,
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H A D | imu_v11_0.c | 328 reg = adev->reg_offset[entry->hwip][entry->instance][entry->segment] + entry->reg;
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H A D | gfx_v9_4_3.c | 738 .hwip = ACA_HWIP_TYPE_SMU, 1427 adev, entry->hwip, entry->instance) : 1429 reg = adev->reg_offset[entry->hwip][inst][entry->segment] +
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H A D | amdgpu_xgmi.c | 1070 .hwip = ACA_HWIP_TYPE_PCS_XGMI,
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H A D | amdgpu_virt.h | 361 u32 acc_flags, u32 hwip, u32 xcc_id); 363 u32 offset, u32 acc_flags, u32 hwip, u32 xcc_id); 369 u32 acc_flags, u32 hwip,
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H A D | amdgpu_virt.c | 904 u32 acc_flags, u32 hwip, 909 switch (hwip) { 1025 u32 acc_flags, u32 hwip, u32 xcc_id) 1030 amdgpu_virt_get_rlcg_reg_access_flag(adev, acc_flags, hwip, true, &rlcg_flag)) { 1042 u32 offset, u32 acc_flags, u32 hwip, u32 xcc_id) 1047 amdgpu_virt_get_rlcg_reg_access_flag(adev, acc_flags, hwip, false, &rlcg_flag)) 903 amdgpu_virt_get_rlcg_reg_access_flag(struct amdgpu_device *adev, u32 acc_flags, u32 hwip, bool write, u32 *rlcg_flag) argument 1023 amdgpu_sriov_wreg(struct amdgpu_device *adev, u32 offset, u32 value, u32 acc_flags, u32 hwip, u32 xcc_id) argument 1041 amdgpu_sriov_rreg(struct amdgpu_device *adev, u32 offset, u32 acc_flags, u32 hwip, u32 xcc_id) argument
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H A D | amdgpu_ras.h | 369 #define AMDGPU_RAS_REG_ENTRY_OFFSET(hwip, ip_inst, segment, reg) \ 370 (adev->reg_offset[hwip][ip_inst][segment] + (reg)) 380 uint32_t hwip; member in struct:amdgpu_ras_err_status_reg_entry
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H A D | amdgpu_ras.c | 3788 AMDGPU_RAS_REG_ENTRY_OFFSET(reg_entry->hwip, instance, 3812 AMDGPU_RAS_REG_ENTRY_OFFSET(reg_entry->hwip, instance, 3889 AMDGPU_RAS_REG_ENTRY_OFFSET(reg_list[i].hwip, instance, 3892 AMDGPU_RAS_REG_ENTRY_OFFSET(reg_list[i].hwip, instance,
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H A D | amdgpu_aca.h | 147 enum aca_hwip_type hwip; member in struct:aca_handle 181 enum aca_hwip_type hwip; member in struct:aca_info
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H A D | amdgpu_aca.c | 180 struct aca_hwip *hwip; local 187 hwip = &aca_hwid_mcatypes[type]; 188 if (!hwip->hwid) 195 return hwip->hwid == hwid && hwip->mcatype == mcatype; 202 if (!aca_bank_hwip_is_matched(bank, handle->hwip)) 562 handle->hwip = ras_info->hwip;
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H A D | soc15.h | 38 u32 hwip; member in struct:soc15_reg_golden 47 u32 hwip; member in struct:soc15_reg_rlcg 54 uint32_t hwip; member in struct:soc15_reg 61 uint32_t hwip; member in struct:soc15_reg_entry 71 uint32_t hwip; member in struct:soc15_allowed_register_entry 80 uint32_t hwip; member in struct:soc15_ras_field_entry 92 #define SOC15_REG_ENTRY_OFFSET(entry) (adev->reg_offset[entry.hwip][entry.inst][entry.seg] + entry.reg_offset)
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H A D | soc15_common.h | 40 #define __WREG32_SOC15_RLC__(reg, value, flag, hwip, inst) \ 42 amdgpu_sriov_wreg(adev, reg, value, flag, hwip, inst) : \ 45 #define __RREG32_SOC15_RLC__(reg, flag, hwip, inst) \ 47 amdgpu_sriov_rreg(adev, reg, flag, hwip, inst) : \ 145 #define WREG32_RLC_NO_KIQ(reg, value, hwip) \ 146 __WREG32_SOC15_RLC__(reg, value, AMDGPU_REGS_NO_KIQ | AMDGPU_REGS_RLC, hwip, 0) 148 #define RREG32_RLC_NO_KIQ(reg, hwip) \ 149 __RREG32_SOC15_RLC__(reg, AMDGPU_REGS_NO_KIQ | AMDGPU_REGS_RLC, hwip, 0)
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H A D | nv.c | 397 if (!adev->reg_offset[en->hwip][en->inst]) 399 else if (reg_offset != (adev->reg_offset[en->hwip][en->inst][en->seg]
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H A D | imu_v11_0_3.c | 117 reg = adev->reg_offset[entry->hwip][entry->instance][entry->segment] + entry->reg;
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H A D | amdgpu_imu.h | 42 u32 hwip; member in struct:imu_rlc_ram_golden
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/linux-master/drivers/gpu/drm/amd/pm/powerplay/hwmgr/ |
H A D | common_baco.c | 112 reg = adev->reg_offset[entry[i].hwip][entry[i].inst][entry[i].seg]
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H A D | common_baco.h | 47 uint32_t hwip; member in struct:soc15_baco_cmd_entry
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