Searched refs:features (Results 1 - 25 of 1426) sorted by relevance

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/linux-master/arch/arm/include/asm/hardware/
H A Dcache-tauros2.h11 extern void __init tauros2_init(unsigned int features);
/linux-master/arch/mips/include/asm/
H A Dcachetype.h5 #include <asm/cpu-features.h>
/linux-master/fs/btrfs/
H A Dfs.c12 u64 features; local
15 features = btrfs_super_incompat_flags(disk_super);
16 if (!(features & flag)) {
18 features = btrfs_super_incompat_flags(disk_super);
19 if (!(features & flag)) {
20 features |= flag;
21 btrfs_set_super_incompat_flags(disk_super, features);
35 u64 features; local
38 features = btrfs_super_incompat_flags(disk_super);
39 if (features
58 u64 features; local
81 u64 features; local
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/linux-master/arch/arm/mach-omap2/
H A Dclock.c78 * ti_clk_init_features - init clock features struct for the SoC
80 * Initializes the clock features struct based on the SoC type.
84 struct ti_clk_features features = { 0 }; local
87 features.fint_min = OMAP3430_DPLL_FINT_BAND1_MIN;
88 features.fint_max = OMAP3430_DPLL_FINT_BAND2_MAX;
89 features.fint_band1_max = OMAP3430_DPLL_FINT_BAND1_MAX;
90 features.fint_band2_min = OMAP3430_DPLL_FINT_BAND2_MIN;
92 features.fint_min = OMAP3PLUS_DPLL_FINT_MIN;
93 features.fint_max = OMAP3PLUS_DPLL_FINT_MAX;
98 features
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/linux-master/include/xen/
H A Dfeatures.h3 * features.h
5 * Query the features reported by Xen.
13 #include <xen/interface/features.h>
/linux-master/drivers/gpu/drm/msm/disp/dpu1/catalog/
H A Ddpu_10_0_sm8650.h24 .features = BIT(DPU_MDP_PERIPH_0_REMOVED),
35 .features = CTL_SM8550_MASK | BIT(DPU_CTL_SPLIT_DISPLAY),
40 .features = CTL_SM8550_MASK | BIT(DPU_CTL_SPLIT_DISPLAY),
45 .features = CTL_SM8550_MASK,
50 .features = CTL_SM8550_MASK,
55 .features = CTL_SM8550_MASK,
60 .features = CTL_SM8550_MASK,
69 .features = VIG_SDM845_MASK_SDMA,
76 .features = VIG_SDM845_MASK_SDMA,
83 .features
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H A Ddpu_8_0_sc8280xp.h24 .features = BIT(DPU_MDP_PERIPH_0_REMOVED),
43 .features = BIT(DPU_CTL_SPLIT_DISPLAY) | CTL_SC7280_MASK,
48 .features = BIT(DPU_CTL_SPLIT_DISPLAY) | CTL_SC7280_MASK,
53 .features = CTL_SC7280_MASK,
58 .features = CTL_SC7280_MASK,
63 .features = CTL_SC7280_MASK,
68 .features = CTL_SC7280_MASK,
77 .features = VIG_SDM845_MASK,
85 .features = VIG_SDM845_MASK,
93 .features
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H A Ddpu_9_0_sm8550.h24 .features = BIT(DPU_MDP_PERIPH_0_REMOVED),
35 .features = CTL_SM8550_MASK | BIT(DPU_CTL_SPLIT_DISPLAY),
40 .features = CTL_SM8550_MASK | BIT(DPU_CTL_SPLIT_DISPLAY),
45 .features = CTL_SM8550_MASK,
50 .features = CTL_SM8550_MASK,
55 .features = CTL_SM8550_MASK,
60 .features = CTL_SM8550_MASK,
69 .features = VIG_SDM845_MASK,
76 .features = VIG_SDM845_MASK,
83 .features
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H A Ddpu_5_1_sc8180x.h26 .features = BIT(DPU_MDP_AUDIO_SELECT),
43 .features = BIT(DPU_CTL_ACTIVE_CFG) | BIT(DPU_CTL_SPLIT_DISPLAY),
48 .features = BIT(DPU_CTL_ACTIVE_CFG) | BIT(DPU_CTL_SPLIT_DISPLAY),
53 .features = BIT(DPU_CTL_ACTIVE_CFG),
58 .features = BIT(DPU_CTL_ACTIVE_CFG),
63 .features = BIT(DPU_CTL_ACTIVE_CFG),
68 .features = BIT(DPU_CTL_ACTIVE_CFG),
77 .features = VIG_SDM845_MASK,
85 .features = VIG_SDM845_MASK,
93 .features
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H A Ddpu_8_1_sm8450.h24 .features = BIT(DPU_MDP_PERIPH_0_REMOVED),
44 .features = BIT(DPU_CTL_SPLIT_DISPLAY) | CTL_SC7280_MASK,
49 .features = BIT(DPU_CTL_SPLIT_DISPLAY) | CTL_SC7280_MASK,
54 .features = CTL_SC7280_MASK,
59 .features = CTL_SC7280_MASK,
64 .features = CTL_SC7280_MASK,
69 .features = CTL_SC7280_MASK,
78 .features = VIG_SDM845_MASK_SDMA,
86 .features = VIG_SDM845_MASK_SDMA,
94 .features
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H A Ddpu_6_0_sm8250.h43 .features = BIT(DPU_CTL_ACTIVE_CFG) | BIT(DPU_CTL_SPLIT_DISPLAY),
48 .features = BIT(DPU_CTL_ACTIVE_CFG) | BIT(DPU_CTL_SPLIT_DISPLAY),
53 .features = BIT(DPU_CTL_ACTIVE_CFG),
58 .features = BIT(DPU_CTL_ACTIVE_CFG),
63 .features = BIT(DPU_CTL_ACTIVE_CFG),
68 .features = BIT(DPU_CTL_ACTIVE_CFG),
77 .features = VIG_SDM845_MASK_SDMA,
85 .features = VIG_SDM845_MASK_SDMA,
93 .features = VIG_SDM845_MASK_SDMA,
101 .features
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H A Ddpu_5_0_sm8150.h26 .features = BIT(DPU_MDP_AUDIO_SELECT),
44 .features = BIT(DPU_CTL_ACTIVE_CFG) | BIT(DPU_CTL_SPLIT_DISPLAY),
49 .features = BIT(DPU_CTL_ACTIVE_CFG) | BIT(DPU_CTL_SPLIT_DISPLAY),
54 .features = BIT(DPU_CTL_ACTIVE_CFG),
59 .features = BIT(DPU_CTL_ACTIVE_CFG),
64 .features = BIT(DPU_CTL_ACTIVE_CFG),
69 .features = BIT(DPU_CTL_ACTIVE_CFG),
78 .features = VIG_SDM845_MASK,
86 .features = VIG_SDM845_MASK,
94 .features
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H A Ddpu_7_0_sm8350.h43 .features = BIT(DPU_CTL_SPLIT_DISPLAY) | CTL_SC7280_MASK,
48 .features = BIT(DPU_CTL_SPLIT_DISPLAY) | CTL_SC7280_MASK,
53 .features = CTL_SC7280_MASK,
58 .features = CTL_SC7280_MASK,
63 .features = CTL_SC7280_MASK,
68 .features = CTL_SC7280_MASK,
77 .features = VIG_SDM845_MASK_SDMA,
85 .features = VIG_SDM845_MASK_SDMA,
93 .features = VIG_SDM845_MASK_SDMA,
101 .features
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H A Ddpu_7_2_sc7280.h35 .features = CTL_SC7280_MASK,
40 .features = CTL_SC7280_MASK,
45 .features = CTL_SC7280_MASK,
50 .features = CTL_SC7280_MASK,
59 .features = VIG_SC7280_MASK_SDMA,
67 .features = DMA_SDM845_MASK_SDMA,
75 .features = DMA_CURSOR_SDM845_MASK_SDMA,
83 .features = DMA_CURSOR_SDM845_MASK_SDMA,
95 .features = MIXER_SDM845_MASK,
102 .features
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H A Ddpu_9_2_x1e80100.h23 .features = BIT(DPU_MDP_PERIPH_0_REMOVED),
34 .features = CTL_SM8550_MASK | BIT(DPU_CTL_SPLIT_DISPLAY),
39 .features = CTL_SM8550_MASK | BIT(DPU_CTL_SPLIT_DISPLAY),
44 .features = CTL_SM8550_MASK,
49 .features = CTL_SM8550_MASK,
54 .features = CTL_SM8550_MASK,
59 .features = CTL_SM8550_MASK,
68 .features = VIG_SDM845_MASK_SDMA,
75 .features = VIG_SDM845_MASK_SDMA,
82 .features
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H A Ddpu_3_0_msm8998.h26 .features = BIT(DPU_MDP_VSYNC_SEL),
45 .features = BIT(DPU_CTL_SPLIT_DISPLAY),
54 .features = BIT(DPU_CTL_SPLIT_DISPLAY),
71 .features = VIG_MSM8998_MASK,
79 .features = VIG_MSM8998_MASK,
87 .features = VIG_MSM8998_MASK,
95 .features = VIG_MSM8998_MASK,
103 .features = DMA_MSM8998_MASK,
111 .features = DMA_MSM8998_MASK,
119 .features
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H A Ddpu_5_4_sm6125.h25 .features = 0,
37 .features = BIT(DPU_CTL_ACTIVE_CFG),
42 .features = BIT(DPU_CTL_ACTIVE_CFG),
47 .features = BIT(DPU_CTL_ACTIVE_CFG),
52 .features = BIT(DPU_CTL_ACTIVE_CFG),
57 .features = BIT(DPU_CTL_ACTIVE_CFG),
62 .features = BIT(DPU_CTL_ACTIVE_CFG),
71 .features = VIG_SDM845_MASK,
79 .features = DMA_SDM845_MASK,
87 .features
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/linux-master/drivers/gpu/drm/panfrost/
H A Dpanfrost_gpu.c157 pfdev->features.revision >= 0x2000)
160 pfdev->features.coherency_features == COHERENCY_ACE)
181 u64 features; member in struct:panfrost_model
193 .features = hw_features_##_name, \
251 pfdev->features.l2_features = gpu_read(pfdev, GPU_L2_FEATURES);
252 pfdev->features.core_features = gpu_read(pfdev, GPU_CORE_FEATURES);
253 pfdev->features.tiler_features = gpu_read(pfdev, GPU_TILER_FEATURES);
254 pfdev->features.mem_features = gpu_read(pfdev, GPU_MEM_FEATURES);
255 pfdev->features.mmu_features = gpu_read(pfdev, GPU_MMU_FEATURES);
256 pfdev->features
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/linux-master/include/xen/arm/
H A Dswiotlb-xen.h5 #include <xen/features.h>
/linux-master/net/netfilter/
H A Dnft_set_pipapo_avx2.h8 bool nft_pipapo_avx2_estimate(const struct nft_set_desc *desc, u32 features,
/linux-master/tools/testing/selftests/rseq/
H A Drseq-x86-thread-pointer.h11 #include <features.h>
/linux-master/arch/loongarch/include/asm/
H A Dtimex.h13 #include <asm/cpu-features.h>
/linux-master/tools/perf/ui/
H A Dlibslang.h7 * has on features.h.
9 #include <features.h>
/linux-master/arch/x86/xen/
H A Dsuspend_hvm.c6 #include <xen/features.h>
7 #include <xen/interface/features.h>
/linux-master/arch/arm/mm/
H A Dcache-tauros2.c180 static void enable_extra_feature(unsigned int features) argument
186 if (features & CACHE_TAUROS2_PREFETCH_ON)
191 (features & CACHE_TAUROS2_PREFETCH_ON)
194 if (features & CACHE_TAUROS2_LINEFILL_BURST8)
199 (features & CACHE_TAUROS2_LINEFILL_BURST8)
205 static void __init tauros2_internal_init(unsigned int features) argument
209 enable_extra_feature(features);
282 void __init tauros2_init(unsigned int features) argument
293 ret = of_property_read_u32(node, "marvell,tauros2-cache-features", &f);
295 pr_info("Not found marvell,tauros-cache-features propert
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