1/* SPDX-License-Identifier: GPL-2.0-only */ 2/* 3 * Copyright (c) 2022. Qualcomm Innovation Center, Inc. All rights reserved. 4 * Copyright (c) 2015-2018, 2020 The Linux Foundation. All rights reserved. 5 */ 6 7#ifndef _DPU_7_2_SC7280_H 8#define _DPU_7_2_SC7280_H 9 10static const struct dpu_caps sc7280_dpu_caps = { 11 .max_mixer_width = DEFAULT_DPU_OUTPUT_LINE_WIDTH, 12 .max_mixer_blendstages = 0x7, 13 .has_dim_layer = true, 14 .has_idle_pc = true, 15 .max_linewidth = 2400, 16 .pixel_ram_size = DEFAULT_PIXEL_RAM_SIZE, 17}; 18 19static const struct dpu_mdp_cfg sc7280_mdp = { 20 .name = "top_0", 21 .base = 0x0, .len = 0x2014, 22 .clk_ctrls = { 23 [DPU_CLK_CTRL_VIG0] = { .reg_off = 0x2ac, .bit_off = 0 }, 24 [DPU_CLK_CTRL_DMA0] = { .reg_off = 0x2ac, .bit_off = 8 }, 25 [DPU_CLK_CTRL_DMA1] = { .reg_off = 0x2b4, .bit_off = 8 }, 26 [DPU_CLK_CTRL_DMA2] = { .reg_off = 0x2c4, .bit_off = 8 }, 27 [DPU_CLK_CTRL_WB2] = { .reg_off = 0x2bc, .bit_off = 16 }, 28 }, 29}; 30 31static const struct dpu_ctl_cfg sc7280_ctl[] = { 32 { 33 .name = "ctl_0", .id = CTL_0, 34 .base = 0x15000, .len = 0x1e8, 35 .features = CTL_SC7280_MASK, 36 .intr_start = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR2, 9), 37 }, { 38 .name = "ctl_1", .id = CTL_1, 39 .base = 0x16000, .len = 0x1e8, 40 .features = CTL_SC7280_MASK, 41 .intr_start = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR2, 10), 42 }, { 43 .name = "ctl_2", .id = CTL_2, 44 .base = 0x17000, .len = 0x1e8, 45 .features = CTL_SC7280_MASK, 46 .intr_start = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR2, 11), 47 }, { 48 .name = "ctl_3", .id = CTL_3, 49 .base = 0x18000, .len = 0x1e8, 50 .features = CTL_SC7280_MASK, 51 .intr_start = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR2, 12), 52 }, 53}; 54 55static const struct dpu_sspp_cfg sc7280_sspp[] = { 56 { 57 .name = "sspp_0", .id = SSPP_VIG0, 58 .base = 0x4000, .len = 0x1f8, 59 .features = VIG_SC7280_MASK_SDMA, 60 .sblk = &dpu_vig_sblk_qseed3_3_0_rot_v2, 61 .xin_id = 0, 62 .type = SSPP_TYPE_VIG, 63 .clk_ctrl = DPU_CLK_CTRL_VIG0, 64 }, { 65 .name = "sspp_8", .id = SSPP_DMA0, 66 .base = 0x24000, .len = 0x1f8, 67 .features = DMA_SDM845_MASK_SDMA, 68 .sblk = &dpu_dma_sblk, 69 .xin_id = 1, 70 .type = SSPP_TYPE_DMA, 71 .clk_ctrl = DPU_CLK_CTRL_DMA0, 72 }, { 73 .name = "sspp_9", .id = SSPP_DMA1, 74 .base = 0x26000, .len = 0x1f8, 75 .features = DMA_CURSOR_SDM845_MASK_SDMA, 76 .sblk = &dpu_dma_sblk, 77 .xin_id = 5, 78 .type = SSPP_TYPE_DMA, 79 .clk_ctrl = DPU_CLK_CTRL_DMA1, 80 }, { 81 .name = "sspp_10", .id = SSPP_DMA2, 82 .base = 0x28000, .len = 0x1f8, 83 .features = DMA_CURSOR_SDM845_MASK_SDMA, 84 .sblk = &dpu_dma_sblk, 85 .xin_id = 9, 86 .type = SSPP_TYPE_DMA, 87 .clk_ctrl = DPU_CLK_CTRL_DMA2, 88 }, 89}; 90 91static const struct dpu_lm_cfg sc7280_lm[] = { 92 { 93 .name = "lm_0", .id = LM_0, 94 .base = 0x44000, .len = 0x320, 95 .features = MIXER_SDM845_MASK, 96 .sblk = &sc7180_lm_sblk, 97 .pingpong = PINGPONG_0, 98 .dspp = DSPP_0, 99 }, { 100 .name = "lm_2", .id = LM_2, 101 .base = 0x46000, .len = 0x320, 102 .features = MIXER_SDM845_MASK, 103 .sblk = &sc7180_lm_sblk, 104 .lm_pair = LM_3, 105 .pingpong = PINGPONG_2, 106 }, { 107 .name = "lm_3", .id = LM_3, 108 .base = 0x47000, .len = 0x320, 109 .features = MIXER_SDM845_MASK, 110 .sblk = &sc7180_lm_sblk, 111 .lm_pair = LM_2, 112 .pingpong = PINGPONG_3, 113 }, 114}; 115 116static const struct dpu_dspp_cfg sc7280_dspp[] = { 117 { 118 .name = "dspp_0", .id = DSPP_0, 119 .base = 0x54000, .len = 0x1800, 120 .features = DSPP_SC7180_MASK, 121 .sblk = &sdm845_dspp_sblk, 122 }, 123}; 124 125static const struct dpu_pingpong_cfg sc7280_pp[] = { 126 { 127 .name = "pingpong_0", .id = PINGPONG_0, 128 .base = 0x69000, .len = 0, 129 .features = BIT(DPU_PINGPONG_DITHER), 130 .sblk = &sc7280_pp_sblk, 131 .merge_3d = 0, 132 .intr_done = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 8), 133 }, { 134 .name = "pingpong_1", .id = PINGPONG_1, 135 .base = 0x6a000, .len = 0, 136 .features = BIT(DPU_PINGPONG_DITHER), 137 .sblk = &sc7280_pp_sblk, 138 .merge_3d = 0, 139 .intr_done = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 9), 140 }, { 141 .name = "pingpong_2", .id = PINGPONG_2, 142 .base = 0x6b000, .len = 0, 143 .features = BIT(DPU_PINGPONG_DITHER), 144 .sblk = &sc7280_pp_sblk, 145 .merge_3d = 0, 146 .intr_done = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 10), 147 }, { 148 .name = "pingpong_3", .id = PINGPONG_3, 149 .base = 0x6c000, .len = 0, 150 .features = BIT(DPU_PINGPONG_DITHER), 151 .sblk = &sc7280_pp_sblk, 152 .merge_3d = 0, 153 .intr_done = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 11), 154 }, 155}; 156 157/* NOTE: sc7280 only has one DSC hard slice encoder */ 158static const struct dpu_dsc_cfg sc7280_dsc[] = { 159 { 160 .name = "dce_0_0", .id = DSC_0, 161 .base = 0x80000, .len = 0x4, 162 .features = BIT(DPU_DSC_HW_REV_1_2) | BIT(DPU_DSC_NATIVE_42x_EN), 163 .sblk = &dsc_sblk_0, 164 }, 165}; 166 167static const struct dpu_wb_cfg sc7280_wb[] = { 168 { 169 .name = "wb_2", .id = WB_2, 170 .base = 0x65000, .len = 0x2c8, 171 .features = WB_SM8250_MASK, 172 .format_list = wb2_formats_rgb_yuv, 173 .num_formats = ARRAY_SIZE(wb2_formats_rgb_yuv), 174 .clk_ctrl = DPU_CLK_CTRL_WB2, 175 .xin_id = 6, 176 .vbif_idx = VBIF_RT, 177 .maxlinewidth = 4096, 178 .intr_wb_done = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 4), 179 }, 180}; 181 182static const struct dpu_intf_cfg sc7280_intf[] = { 183 { 184 .name = "intf_0", .id = INTF_0, 185 .base = 0x34000, .len = 0x280, 186 .features = INTF_SC7280_MASK, 187 .type = INTF_DP, 188 .controller_id = MSM_DP_CONTROLLER_0, 189 .prog_fetch_lines_worst_case = 24, 190 .intr_underrun = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 24), 191 .intr_vsync = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 25), 192 }, { 193 .name = "intf_1", .id = INTF_1, 194 .base = 0x35000, .len = 0x2c4, 195 .features = INTF_SC7280_MASK, 196 .type = INTF_DSI, 197 .controller_id = MSM_DSI_CONTROLLER_0, 198 .prog_fetch_lines_worst_case = 24, 199 .intr_underrun = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 26), 200 .intr_vsync = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 27), 201 .intr_tear_rd_ptr = DPU_IRQ_IDX(MDP_INTF1_TEAR_INTR, 2), 202 }, { 203 .name = "intf_5", .id = INTF_5, 204 .base = 0x39000, .len = 0x280, 205 .features = INTF_SC7280_MASK, 206 .type = INTF_DP, 207 .controller_id = MSM_DP_CONTROLLER_1, 208 .prog_fetch_lines_worst_case = 24, 209 .intr_underrun = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 22), 210 .intr_vsync = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 23), 211 }, 212}; 213 214static const struct dpu_perf_cfg sc7280_perf_data = { 215 .max_bw_low = 4700000, 216 .max_bw_high = 8800000, 217 .min_core_ib = 2500000, 218 .min_llcc_ib = 0, 219 .min_dram_ib = 1600000, 220 .min_prefill_lines = 24, 221 .danger_lut_tbl = {0xffff, 0xffff, 0x0}, 222 .safe_lut_tbl = {0xff00, 0xff00, 0xffff}, 223 .qos_lut_tbl = { 224 {.nentry = ARRAY_SIZE(sc7180_qos_macrotile), 225 .entries = sc7180_qos_macrotile 226 }, 227 {.nentry = ARRAY_SIZE(sc7180_qos_macrotile), 228 .entries = sc7180_qos_macrotile 229 }, 230 {.nentry = ARRAY_SIZE(sc7180_qos_nrt), 231 .entries = sc7180_qos_nrt 232 }, 233 }, 234 .cdp_cfg = { 235 {.rd_enable = 1, .wr_enable = 1}, 236 {.rd_enable = 1, .wr_enable = 0} 237 }, 238 .clk_inefficiency_factor = 105, 239 .bw_inefficiency_factor = 120, 240}; 241 242static const struct dpu_mdss_version sc7280_mdss_ver = { 243 .core_major_ver = 7, 244 .core_minor_ver = 2, 245}; 246 247const struct dpu_mdss_cfg dpu_sc7280_cfg = { 248 .mdss_ver = &sc7280_mdss_ver, 249 .caps = &sc7280_dpu_caps, 250 .mdp = &sc7280_mdp, 251 .cdm = &sc7280_cdm, 252 .ctl_count = ARRAY_SIZE(sc7280_ctl), 253 .ctl = sc7280_ctl, 254 .sspp_count = ARRAY_SIZE(sc7280_sspp), 255 .sspp = sc7280_sspp, 256 .dspp_count = ARRAY_SIZE(sc7280_dspp), 257 .dspp = sc7280_dspp, 258 .mixer_count = ARRAY_SIZE(sc7280_lm), 259 .mixer = sc7280_lm, 260 .pingpong_count = ARRAY_SIZE(sc7280_pp), 261 .pingpong = sc7280_pp, 262 .dsc_count = ARRAY_SIZE(sc7280_dsc), 263 .dsc = sc7280_dsc, 264 .wb_count = ARRAY_SIZE(sc7280_wb), 265 .wb = sc7280_wb, 266 .intf_count = ARRAY_SIZE(sc7280_intf), 267 .intf = sc7280_intf, 268 .vbif_count = ARRAY_SIZE(sdm845_vbif), 269 .vbif = sdm845_vbif, 270 .perf = &sc7280_perf_data, 271}; 272 273#endif 274