/linux-master/drivers/gpu/drm/radeon/ |
H A D | rv770_dpm.h | 181 u32 engine_clock, 184 u32 engine_clock, u32 memory_clock, 202 int rv740_populate_sclk_value(struct radeon_device *rdev, u32 engine_clock, 205 u32 engine_clock, u32 memory_clock, 227 u32 engine_clock);
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H A D | rv740_dpm.c | 119 int rv740_populate_sclk_value(struct radeon_device *rdev, u32 engine_clock, argument 136 engine_clock, false, ÷rs); 142 tmp = (u64) engine_clock * reference_divider * dividers.post_div * 16384; 159 u32 vco_freq = engine_clock * dividers.post_div; 175 sclk->sclk_value = cpu_to_be32(engine_clock); 186 u32 engine_clock, u32 memory_clock, 185 rv740_populate_mclk_value(struct radeon_device *rdev, u32 engine_clock, u32 memory_clock, RV7XX_SMC_MCLK_VALUE *mclk) argument
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H A D | rv730_dpm.c | 38 u32 engine_clock, 55 engine_clock, false, ÷rs); 67 tmp = (u64) engine_clock * reference_divider * post_divider * 16384; 90 u32 vco_freq = engine_clock * post_divider; 106 sclk->sclk_value = cpu_to_be32(engine_clock); 117 u32 engine_clock, u32 memory_clock, 37 rv730_populate_sclk_value(struct radeon_device *rdev, u32 engine_clock, RV770_SMC_SCLK_VALUE *sclk) argument 116 rv730_populate_mclk_value(struct radeon_device *rdev, u32 engine_clock, u32 memory_clock, LPRV7XX_SMC_MCLK_VALUE mclk) argument
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H A D | cypress_dpm.h | 125 u32 engine_clock, u32 memory_clock);
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H A D | rv770_dpm.c | 388 u32 engine_clock, u32 memory_clock, 486 u32 engine_clock, 508 engine_clock, false, ÷rs); 519 tmp = (u64) engine_clock * reference_divider * post_divider * 16384; 541 u32 vco_freq = engine_clock * post_divider; 557 sclk->sclk_value = cpu_to_be32(engine_clock); 724 u32 engine_clock) 735 mc_arb_rfsh_rate = ((engine_clock * 10) * dram_refresh_rate / dram_rows - 32) / 64; 387 rv770_populate_mclk_value(struct radeon_device *rdev, u32 engine_clock, u32 memory_clock, RV7XX_SMC_MCLK_VALUE *mclk) argument 485 rv770_populate_sclk_value(struct radeon_device *rdev, u32 engine_clock, RV770_SMC_SCLK_VALUE *sclk) argument 723 rv770_calculate_memory_refresh_rate(struct radeon_device *rdev, u32 engine_clock) argument
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H A D | ci_dpm.c | 2452 const u32 engine_clock, 2466 tmp2 = (((0x31 * engine_clock) / 125000) - 1) & 0xff; 2470 tmp2 = (((0x36 * engine_clock) / 137500) - 1) & 0xff; 3116 u32 engine_clock, 3132 engine_clock, false, ÷rs); 3145 u32 vco_freq = engine_clock * dividers.post_div; 3161 sclk->SclkFrequency = engine_clock; 3172 u32 engine_clock, 3179 ret = ci_calculate_sclk_params(rdev, engine_clock, graphic_level); 3185 engine_clock, 2451 ci_register_patching_mc_arb(struct radeon_device *rdev, const u32 engine_clock, const u32 memory_clock, u32 *dram_timimg2) argument 3115 ci_calculate_sclk_params(struct radeon_device *rdev, u32 engine_clock, SMU7_Discrete_GraphicsLevel *sclk) argument 3171 ci_populate_single_graphic_level(struct radeon_device *rdev, u32 engine_clock, u16 sclk_activity_level_t, SMU7_Discrete_GraphicsLevel *graphic_level) argument [all...] |
H A D | ni_dpm.c | 1999 u32 engine_clock, 2018 engine_clock, false, ÷rs); 2025 tmp = (u64) engine_clock * reference_divider * dividers.post_div * 16834; 2042 u32 vco_freq = engine_clock * dividers.post_div; 2058 sclk->sclk_value = engine_clock; 2070 u32 engine_clock, 2076 ret = ni_calculate_sclk_params(rdev, engine_clock, &sclk_tmp); 2161 u32 engine_clock, 1998 ni_calculate_sclk_params(struct radeon_device *rdev, u32 engine_clock, NISLANDS_SMC_SCLK_VALUE *sclk) argument 2069 ni_populate_sclk_value(struct radeon_device *rdev, u32 engine_clock, NISLANDS_SMC_SCLK_VALUE *sclk) argument 2160 ni_populate_mclk_value(struct radeon_device *rdev, u32 engine_clock, u32 memory_clock, NISLANDS_SMC_MCLK_VALUE *mclk, bool strobe_mode, bool dll_state_on) argument
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H A D | cypress_dpm.c | 473 u32 engine_clock, u32 memory_clock, 907 u32 engine_clock, u32 memory_clock) 911 u32 result = (4 * multiplier * engine_clock) / (memory_clock / 2); 472 cypress_populate_mclk_value(struct radeon_device *rdev, u32 engine_clock, u32 memory_clock, RV7XX_SMC_MCLK_VALUE *mclk, bool strobe_mode, bool dll_state_on) argument 906 cypress_calculate_burst_time(struct radeon_device *rdev, u32 engine_clock, u32 memory_clock) argument
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H A D | si_dpm.c | 1693 u32 engine_clock, 4210 u32 engine_clock) 4223 mc_arb_rfsh_rate = ((engine_clock * 10) * dram_refresh_rate / dram_rows - 32) / 64; 4720 u32 engine_clock, 4739 engine_clock, false, ÷rs); 4745 tmp = (u64) engine_clock * reference_divider * dividers.post_div * 16384; 4762 u32 vco_freq = engine_clock * dividers.post_div; 4778 sclk->sclk_value = engine_clock; 4790 u32 engine_clock, 4796 ret = si_calculate_sclk_params(rdev, engine_clock, 4209 si_calculate_memory_refresh_rate(struct radeon_device *rdev, u32 engine_clock) argument 4719 si_calculate_sclk_params(struct radeon_device *rdev, u32 engine_clock, SISLANDS_SMC_SCLK_VALUE *sclk) argument 4789 si_populate_sclk_value(struct radeon_device *rdev, u32 engine_clock, SISLANDS_SMC_SCLK_VALUE *sclk) argument 4810 si_populate_mclk_value(struct radeon_device *rdev, u32 engine_clock, u32 memory_clock, SISLANDS_SMC_MCLK_VALUE *mclk, bool strobe_mode, bool dll_state_on) argument [all...] |
H A D | rv6xx_dpm.c | 782 u32 engine_clock) 791 return ((engine_clock * 10) * dram_refresh_rate / dram_rows - 32) / 64; 781 calculate_memory_refresh_rate(struct radeon_device *rdev, u32 engine_clock) argument
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/linux-master/drivers/gpu/drm/amd/pm/powerplay/hwmgr/ |
H A D | ppatomctrl.h | 300 extern int atomctrl_get_engine_clock_spread_spectrum(struct pp_hwmgr *hwmgr, const uint32_t engine_clock, pp_atomctrl_internal_ss_info *ssInfo); 303 extern int atomctrl_set_engine_dram_timings_rv770(struct pp_hwmgr *hwmgr, uint32_t engine_clock, uint32_t memory_clock);
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H A D | smu7_hwmgr.c | 3350 if (smu7_ps->performance_levels[i].engine_clock > max_limits->sclk) 3351 smu7_ps->performance_levels[i].engine_clock = max_limits->sclk; 3401 sclk = smu7_ps->performance_levels[0].engine_clock; 3418 smu7_ps->performance_levels[0].engine_clock = sclk; 3421 smu7_ps->performance_levels[1].engine_clock = 3422 (smu7_ps->performance_levels[1].engine_clock >= 3423 smu7_ps->performance_levels[0].engine_clock) ? 3424 smu7_ps->performance_levels[1].engine_clock : 3425 smu7_ps->performance_levels[0].engine_clock; 3476 smu7_ps->performance_levels[i].engine_clock 3798 uint32_t engine_clock, memory_clock; local [all...] |
H A D | smu7_hwmgr.h | 56 uint32_t engine_clock; member in struct:smu7_performance_level
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H A D | smu10_hwmgr.h | 76 uint32_t engine_clock; member in struct:smu10_power_level
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H A D | smu10_hwmgr.c | 897 smu10_ps->levels[index].engine_clock = 0; 1137 clock_info->min_eng_clk = ps->levels[0].engine_clock / (1 << (ps->levels[0].ss_divider_index)); 1138 clock_info->max_eng_clk = ps->levels[ps->level - 1].engine_clock / (1 << (ps->levels[ps->level - 1].ss_divider_index));
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H A D | ppatomctrl.c | 211 uint32_t engine_clock, 220 cpu_to_le32((engine_clock & SET_CLOCK_FREQ_MASK) | 1334 const uint32_t engine_clock, 1338 ASIC_INTERNAL_ENGINE_SS, engine_clock, ssInfo); 209 atomctrl_set_engine_dram_timings_rv770( struct pp_hwmgr *hwmgr, uint32_t engine_clock, uint32_t memory_clock) argument 1332 atomctrl_get_engine_clock_spread_spectrum( struct pp_hwmgr *hwmgr, const uint32_t engine_clock, pp_atomctrl_internal_ss_info *ssInfo) argument
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/linux-master/drivers/gpu/drm/amd/pm/powerplay/smumgr/ |
H A D | iceland_smumgr.c | 796 uint32_t engine_clock, SMU71_Discrete_GraphicsLevel *sclk) 811 result = atomctrl_get_engine_pll_dividers_vi(hwmgr, engine_clock, ÷rs); 842 uint32_t vcoFreq = engine_clock * dividers.uc_pll_post_div; 863 sclk->SclkFrequency = engine_clock; 892 uint32_t engine_clock, 898 result = iceland_calculate_sclk_params(hwmgr, engine_clock, graphic_level); 902 hwmgr->dyn_state.vddc_dependency_on_sclk, engine_clock, 908 graphic_level->SclkFrequency = engine_clock; 914 engine_clock, 937 smu7_get_sleep_divider_id_from_clock(engine_clock, 795 iceland_calculate_sclk_params(struct pp_hwmgr *hwmgr, uint32_t engine_clock, SMU71_Discrete_GraphicsLevel *sclk) argument 891 iceland_populate_single_graphic_level(struct pp_hwmgr *hwmgr, uint32_t engine_clock, SMU71_Discrete_GraphicsLevel *graphic_level) argument 1582 iceland_populate_memory_timing_parameters( struct pp_hwmgr *hwmgr, uint32_t engine_clock, uint32_t memory_clock, struct SMU71_Discrete_MCArbDramTimingTableEntry *arb_regs ) argument [all...] |
H A D | tonga_smumgr.c | 539 uint32_t engine_clock, SMU72_Discrete_GraphicsLevel *sclk) 554 result = atomctrl_get_engine_pll_dividers_vi(hwmgr, engine_clock, ÷rs); 585 uint32_t vcoFreq = engine_clock * dividers.uc_pll_post_div; 606 sclk->SclkFrequency = engine_clock; 617 uint32_t engine_clock, 627 result = tonga_calculate_sclk_params(hwmgr, engine_clock, graphic_level); 636 vdd_dep_table, engine_clock, 643 graphic_level->SclkFrequency = engine_clock; 664 smu7_get_sleep_divider_id_from_clock(engine_clock, 1459 uint32_t engine_clock, 538 tonga_calculate_sclk_params(struct pp_hwmgr *hwmgr, uint32_t engine_clock, SMU72_Discrete_GraphicsLevel *sclk) argument 616 tonga_populate_single_graphic_level(struct pp_hwmgr *hwmgr, uint32_t engine_clock, SMU72_Discrete_GraphicsLevel *graphic_level) argument 1457 tonga_populate_memory_timing_parameters( struct pp_hwmgr *hwmgr, uint32_t engine_clock, uint32_t memory_clock, struct SMU72_Discrete_MCArbDramTimingTableEntry *arb_regs ) argument [all...] |
H A D | ci_smumgr.c | 1623 uint32_t engine_clock, 1634 engine_clock, memory_clock); 1621 ci_populate_memory_timing_parameters( struct pp_hwmgr *hwmgr, uint32_t engine_clock, uint32_t memory_clock, struct SMU7_Discrete_MCArbDramTimingTableEntry *arb_regs ) argument
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/linux-master/drivers/gpu/drm/amd/pm/legacy-dpm/ |
H A D | si_dpm.c | 1845 u32 engine_clock, 4733 u32 engine_clock) 4746 mc_arb_rfsh_rate = ((engine_clock * 10) * dram_refresh_rate / dram_rows - 32) / 64; 5266 u32 engine_clock, 5285 engine_clock, false, ÷rs); 5291 tmp = (u64) engine_clock * reference_divider * dividers.post_div * 16384; 5308 u32 vco_freq = engine_clock * dividers.post_div; 5324 sclk->sclk_value = engine_clock; 5336 u32 engine_clock, 5342 ret = si_calculate_sclk_params(adev, engine_clock, 4732 si_calculate_memory_refresh_rate(struct amdgpu_device *adev, u32 engine_clock) argument 5265 si_calculate_sclk_params(struct amdgpu_device *adev, u32 engine_clock, SISLANDS_SMC_SCLK_VALUE *sclk) argument 5335 si_populate_sclk_value(struct amdgpu_device *adev, u32 engine_clock, SISLANDS_SMC_SCLK_VALUE *sclk) argument 5356 si_populate_mclk_value(struct amdgpu_device *adev, u32 engine_clock, u32 memory_clock, SISLANDS_SMC_MCLK_VALUE *mclk, bool strobe_mode, bool dll_state_on) argument [all...] |
/linux-master/drivers/gpu/drm/amd/pm/swsmu/inc/ |
H A D | amdgpu_smu.h | 400 uint32_t engine_clock; member in struct:smu_clocks
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