Searched refs:dividers (Results 1 - 25 of 47) sorted by relevance

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/linux-master/drivers/gpu/drm/radeon/
H A Drv740_dpm.c123 struct atom_clock_dividers dividers; local
136 engine_clock, false, &dividers);
140 reference_divider = 1 + dividers.ref_div;
142 tmp = (u64) engine_clock * reference_divider * dividers.post_div * 16384;
147 spll_func_cntl |= SPLL_REF_DIV(dividers.ref_div);
148 spll_func_cntl |= SPLL_PDIV_A(dividers.post_div);
159 u32 vco_freq = engine_clock * dividers.post_div;
198 struct atom_clock_dividers dividers; local
204 memory_clock, false, &dividers);
208 ibias = rv770_map_clkf_to_ibias(rdev, dividers
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H A Drv730_dpm.c42 struct atom_clock_dividers dividers; local
55 engine_clock, false, &dividers);
59 reference_divider = 1 + dividers.ref_div;
61 if (dividers.enable_post_div)
62 post_divider = ((dividers.post_div >> 4) & 0xf) +
63 (dividers.post_div & 0xf) + 2;
72 if (dividers.enable_post_div)
77 spll_func_cntl |= SPLL_REF_DIV(dividers.ref_div);
78 spll_func_cntl |= SPLL_HILEN((dividers.post_div >> 4) & 0xf);
79 spll_func_cntl |= SPLL_LOLEN(dividers
128 struct atom_clock_dividers dividers; local
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H A Drv6xx_dpm.c142 struct atom_clock_dividers dividers; local
145 clock, false, &dividers);
149 if (dividers.enable_post_div)
150 step->post_divider = 2 + (dividers.post_div & 0xF) + (dividers.post_div >> 4);
526 struct atom_clock_dividers *dividers,
529 return ref_clock * ((dividers->fb_div & ~1) << fb_divider_scale) /
530 (dividers->ref_div + 1);
553 struct atom_clock_dividers dividers; local
560 if (radeon_atom_get_clock_dividers(rdev, COMPUTE_ENGINE_PLL_PARAM, clock, false, &dividers)
525 rv6xx_calculate_vco_frequency(u32 ref_clock, struct atom_clock_dividers *dividers, u32 fb_divider_scale) argument
600 struct atom_clock_dividers dividers; local
630 rv6xx_find_memory_clock_with_highest_vco(struct radeon_device *rdev, u32 requested_memory_clock, u32 ref_clk, struct atom_clock_dividers *dividers, u32 *vco_freq) argument
656 struct atom_clock_dividers dividers; local
1935 struct atom_clock_dividers dividers; local
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H A Drs780_dpm.c78 struct atom_clock_dividers dividers; local
83 default_state->sclk_low, false, &dividers);
87 r600_engine_clock_entry_set_reference_divider(rdev, 0, dividers.ref_div);
88 r600_engine_clock_entry_set_feedback_divider(rdev, 0, dividers.fb_div);
89 r600_engine_clock_entry_set_post_divider(rdev, 0, dividers.post_div);
91 if (dividers.enable_post_div)
1033 struct atom_clock_dividers dividers; local
1044 ps->sclk_high, false, &dividers);
1048 rs780_force_fbdiv(rdev, dividers.fb_div);
1051 ps->sclk_low, false, &dividers);
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H A Drv770_dpm.c322 struct atom_clock_dividers *dividers,
334 post_divider = dividers->post_div;
335 reference_divider = dividers->ref_div;
404 struct atom_clock_dividers dividers; local
412 memory_clock, false, &dividers);
416 if ((dividers.ref_div < 1) || (dividers.ref_div > 5))
421 &dividers, &clkf, &clkfrac);
423 ret = rv770_encode_yclk_post_div(dividers.post_div, &postdiv_yclk);
434 mpll_ad_func_cntl |= CLKR(encoded_reference_dividers[dividers
319 rv770_calculate_fractional_mpll_feedback_divider(u32 memory_clock, u32 reference_clock, bool gddr5, struct atom_clock_dividers *dividers, u32 *clkf, u32 *clkfrac) argument
490 struct atom_clock_dividers dividers; local
2348 struct atom_clock_dividers dividers; local
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H A Dcypress_dpm.c493 struct atom_clock_dividers dividers; local
500 memory_clock, strobe_mode, &dividers);
508 dividers.post_div = 1;
511 ibias = cypress_map_clkf_to_ibias(rdev, dividers.whole_fb_div);
518 mpll_ad_func_cntl |= CLKR(dividers.ref_div);
519 mpll_ad_func_cntl |= YCLK_POST_DIV(dividers.post_div);
520 mpll_ad_func_cntl |= CLKF(dividers.whole_fb_div);
521 mpll_ad_func_cntl |= CLKFRAC(dividers.frac_fb_div);
524 if (dividers.vco_mode)
535 mpll_dq_func_cntl |= CLKR(dividers
2028 struct atom_clock_dividers dividers; local
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H A Dradeon_atombios.c2841 struct atom_clock_dividers *dividers)
2848 memset(dividers, 0, sizeof(struct atom_clock_dividers));
2861 dividers->post_div = args.v1.ucPostDiv;
2862 dividers->fb_div = args.v1.ucFbDiv;
2863 dividers->enable_post_div = true;
2875 dividers->post_div = args.v2.ucPostDiv;
2876 dividers->fb_div = le16_to_cpu(args.v2.usFbDiv);
2877 dividers->ref_div = args.v2.ucAction;
2879 dividers->enable_post_div = (le32_to_cpu(args.v2.ulClock) & (1 << 24)) ?
2881 dividers
2837 radeon_atom_get_clock_dividers(struct radeon_device *rdev, u8 clock_type, u32 clock, bool strobe_mode, struct atom_clock_dividers *dividers) argument
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H A Dni_dpm.c2004 struct atom_clock_dividers dividers; local
2018 engine_clock, false, &dividers);
2022 reference_divider = 1 + dividers.ref_div;
2025 tmp = (u64) engine_clock * reference_divider * dividers.post_div * 16834;
2030 spll_func_cntl |= SPLL_REF_DIV(dividers.ref_div);
2031 spll_func_cntl |= SPLL_PDIV_A(dividers.post_div);
2042 u32 vco_freq = engine_clock * dividers.post_div;
2177 struct atom_clock_dividers dividers; local
2184 memory_clock, strobe_mode, &dividers);
2192 dividers
4051 struct atom_clock_dividers dividers; local
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/linux-master/drivers/gpu/drm/amd/display/modules/color/
H A Dcolor_gamma.c390 struct dividers { struct
1277 struct dividers dividers)
1313 dividers.divider1);
1315 dividers.divider1);
1317 dividers.divider1);
1322 dividers.divider2);
1324 dividers.divider2);
1326 dividers.divider2);
1331 dividers
1275 scale_gamma(struct pwl_float_data *pwl_rgb, const struct dc_gamma *ramp, struct dividers dividers) argument
1338 scale_gamma_dx(struct pwl_float_data *pwl_rgb, const struct dc_gamma *ramp, struct dividers dividers) argument
1406 scale_user_regamma_ramp(struct pwl_float_data *pwl_rgb, const struct regamma_ramp *ramp, struct dividers dividers) argument
1561 build_evenly_distributed_points( struct gamma_pixel *points, uint32_t numberof_points, struct dividers dividers) argument
1918 struct dividers dividers; local
1982 struct dividers dividers; local
2223 struct dividers dividers; local
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/linux-master/drivers/gpu/drm/amd/pm/powerplay/hwmgr/
H A Dppatomctrl.c389 pp_atomctrl_clock_dividers_kong *dividers)
402 dividers->pll_post_divider = pll_parameters.ucPostDiv;
403 dividers->real_clock = le32_to_cpu(pll_parameters.ulClock);
412 pp_atomctrl_clock_dividers_vi *dividers)
426 dividers->pll_post_divider =
428 dividers->real_clock =
431 dividers->ul_fb_div.ul_fb_div_frac =
433 dividers->ul_fb_div.ul_fb_div =
436 dividers->uc_pll_ref_div =
438 dividers
387 atomctrl_get_engine_pll_dividers_kong(struct pp_hwmgr *hwmgr, uint32_t clock_value, pp_atomctrl_clock_dividers_kong *dividers) argument
409 atomctrl_get_engine_pll_dividers_vi( struct pp_hwmgr *hwmgr, uint32_t clock_value, pp_atomctrl_clock_dividers_vi *dividers) argument
447 atomctrl_get_engine_pll_dividers_ai(struct pp_hwmgr *hwmgr, uint32_t clock_value, pp_atomctrl_clock_dividers_ai *dividers) argument
478 atomctrl_get_dfs_pll_dividers_vi( struct pp_hwmgr *hwmgr, uint32_t clock_value, pp_atomctrl_clock_dividers_vi *dividers) argument
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H A Dppatomctrl.h306 extern int atomctrl_get_engine_pll_dividers_vi(struct pp_hwmgr *hwmgr, uint32_t clock_value, pp_atomctrl_clock_dividers_vi *dividers);
307 extern int atomctrl_get_dfs_pll_dividers_vi(struct pp_hwmgr *hwmgr, uint32_t clock_value, pp_atomctrl_clock_dividers_vi *dividers);
316 pp_atomctrl_clock_dividers_kong *dividers);
321 extern int atomctrl_get_engine_pll_dividers_ai(struct pp_hwmgr *hwmgr, uint32_t clock_value, pp_atomctrl_clock_dividers_ai *dividers);
H A Dppatomfwctrl.c244 * @param dividers output parameter:Clock dividers
248 struct pp_atomfwctrl_clock_dividers_soc15 *dividers)
266 dividers->ulClock = le32_to_cpu(pll_output->gpuclock_10khz);
267 dividers->ulDid = le32_to_cpu(pll_output->dfs_did);
268 dividers->ulPll_fb_mult = le32_to_cpu(pll_output->pll_fb_mult);
269 dividers->ulPll_ss_fbsmult = le32_to_cpu(pll_output->pll_ss_fbsmult);
270 dividers->usPll_ss_slew_frac = le16_to_cpu(pll_output->pll_ss_slew_frac);
271 dividers->ucPll_ss_enable = pll_output->pll_ss_enable;
246 pp_atomfwctrl_get_gpu_pll_dividers_vega10(struct pp_hwmgr *hwmgr, uint32_t clock_type, uint32_t clock_value, struct pp_atomfwctrl_clock_dividers_soc15 *dividers) argument
H A Dsmu8_hwmgr.c441 pp_atomctrl_clock_dividers_kong dividers; local
486 &dividers);
489 (uint8_t)dividers.pll_post_divider;
503 &dividers);
506 (uint8_t)dividers.pll_post_divider;
517 &dividers);
520 (uint8_t)dividers.pll_post_divider;
529 &dividers);
532 (uint8_t)dividers.pll_post_divider;
543 &dividers);
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H A Dvega10_hwmgr.c1492 struct pp_atomfwctrl_clock_dividers_soc15 dividers; local
1497 lclock, &dividers),
1501 *curr_lclk_did = dividers.ulDid;
1610 struct pp_atomfwctrl_clock_dividers_soc15 dividers; local
1639 gfx_clock, &dividers),
1645 cpu_to_le32(dividers.ulPll_fb_mult);
1647 current_gfxclk_level->SsOn = dividers.ucPll_ss_enable;
1649 cpu_to_le32(dividers.ulPll_ss_fbsmult);
1651 cpu_to_le16(dividers.usPll_ss_slew_frac);
1652 current_gfxclk_level->Did = (uint8_t)(dividers
1677 struct pp_atomfwctrl_clock_dividers_soc15 dividers; local
1814 struct pp_atomfwctrl_clock_dividers_soc15 dividers; local
1986 struct pp_atomfwctrl_clock_dividers_soc15 dividers; local
2039 struct pp_atomfwctrl_clock_dividers_soc15 dividers; local
2055 struct pp_atomfwctrl_clock_dividers_soc15 dividers; local
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/linux-master/drivers/gpu/drm/amd/amdgpu/
H A Damdgpu_atombios.c1000 struct atom_clock_dividers *dividers)
1007 memset(dividers, 0, sizeof(struct atom_clock_dividers));
1024 dividers->post_div = args.v3.ucPostDiv;
1025 dividers->enable_post_div = (args.v3.ucCntlFlag &
1027 dividers->enable_dithen = (args.v3.ucCntlFlag &
1029 dividers->whole_fb_div = le16_to_cpu(args.v3.ulFbDiv.usFbDiv);
1030 dividers->frac_fb_div = le16_to_cpu(args.v3.ulFbDiv.usFbDivFrac);
1031 dividers->ref_div = args.v3.ucRefDiv;
1032 dividers->vco_mode = (args.v3.ucCntlFlag &
1045 dividers
996 amdgpu_atombios_get_clock_dividers(struct amdgpu_device *adev, u8 clock_type, u32 clock, bool strobe_mode, struct atom_clock_dividers *dividers) argument
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H A Damdgpu_atombios.h158 struct atom_clock_dividers *dividers);
206 struct atom_clock_dividers *dividers);
/linux-master/drivers/gpu/drm/amd/pm/powerplay/smumgr/
H A Dvegam_smumgr.c724 struct pp_atomctrl_clock_dividers_ai dividers; local
732 /* get the engine clock dividers for this clock value */
733 result = atomctrl_get_engine_pll_dividers_ai(hwmgr, clock, &dividers);
735 sclk_setting->Fcw_int = dividers.usSclk_fcw_int;
736 sclk_setting->Fcw_frac = dividers.usSclk_fcw_frac;
737 sclk_setting->Pcc_fcw_int = dividers.usPcc_fcw_int;
738 sclk_setting->PllRange = dividers.ucSclkPllRange;
740 sclk_setting->Pcc_up_slew_rate = dividers.usPcc_fcw_slew_frac;
742 sclk_setting->SSc_En = dividers.ucSscEnable;
743 sclk_setting->Fcw1_int = dividers
1199 struct pp_atomctrl_clock_dividers_vi dividers; local
1312 struct pp_atomctrl_clock_dividers_vi dividers; local
1930 pp_atomctrl_clock_dividers_vi dividers; local
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H A Dfiji_smumgr.c859 struct pp_atomctrl_clock_dividers_vi dividers; local
870 /* get the engine clock dividers for this clock value */
871 result = atomctrl_get_engine_pll_dividers_vi(hwmgr, clock, &dividers);
874 "Error retrieving Engine Clock dividers from VBIOS.",
879 ref_divider = 1 + dividers.uc_pll_ref_div;
882 fbdiv = dividers.ul_fb_div.ul_fb_divider & 0x3FFFFFF;
886 SPLL_REF_DIV, dividers.uc_pll_ref_div);
888 SPLL_PDIV_A, dividers.uc_pll_post_div);
902 uint32_t vco_freq = clock * dividers.uc_pll_post_div;
931 sclk->SclkDid = (uint8_t)dividers
1303 struct pp_atomctrl_clock_dividers_vi dividers; local
1423 struct pp_atomctrl_clock_dividers_vi dividers; local
1462 struct pp_atomctrl_clock_dividers_vi dividers; local
1558 struct pp_atomctrl_clock_dividers_vi dividers; local
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H A Dpolaris10_smumgr.c895 struct pp_atomctrl_clock_dividers_ai dividers; local
903 /* get the engine clock dividers for this clock value */
904 result = atomctrl_get_engine_pll_dividers_ai(hwmgr, clock, &dividers);
906 sclk_setting->Fcw_int = dividers.usSclk_fcw_int;
907 sclk_setting->Fcw_frac = dividers.usSclk_fcw_frac;
908 sclk_setting->Pcc_fcw_int = dividers.usPcc_fcw_int;
909 sclk_setting->PllRange = dividers.ucSclkPllRange;
911 sclk_setting->Pcc_up_slew_rate = dividers.usPcc_fcw_slew_frac;
913 sclk_setting->SSc_En = dividers.ucSscEnable;
914 sclk_setting->Fcw1_int = dividers
1058 pp_atomctrl_clock_dividers_vi dividers; local
1370 struct pp_atomctrl_clock_dividers_vi dividers; local
1420 struct pp_atomctrl_clock_dividers_vi dividers; local
1525 struct pp_atomctrl_clock_dividers_vi dividers; local
1924 pp_atomctrl_clock_dividers_vi dividers; local
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H A Dtonga_smumgr.c542 pp_atomctrl_clock_dividers_vi dividers; local
553 /* get the engine clock dividers for this clock value*/
554 result = atomctrl_get_engine_pll_dividers_vi(hwmgr, engine_clock, &dividers);
557 "Error retrieving Engine Clock dividers from VBIOS.", return result);
562 reference_divider = 1 + dividers.uc_pll_ref_div;
565 fbdiv = dividers.ul_fb_div.ul_fb_divider & 0x3FFFFFF;
569 CG_SPLL_FUNC_CNTL, SPLL_REF_DIV, dividers.uc_pll_ref_div);
571 CG_SPLL_FUNC_CNTL, SPLL_PDIV_A, dividers.uc_pll_post_div);
585 uint32_t vcoFreq = engine_clock * dividers.uc_pll_post_div;
611 sclk->SclkDid = (uint8_t)dividers
1180 struct pp_atomctrl_clock_dividers_vi dividers; local
1313 pp_atomctrl_clock_dividers_vi dividers; local
1373 pp_atomctrl_clock_dividers_vi dividers; local
1418 pp_atomctrl_clock_dividers_vi dividers; local
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H A Dci_smumgr.c301 struct pp_atomctrl_clock_dividers_vi dividers; local
312 /* get the engine clock dividers for this clock value */
313 result = atomctrl_get_engine_pll_dividers_vi(hwmgr, clock, &dividers);
316 "Error retrieving Engine Clock dividers from VBIOS.",
321 ref_divider = 1 + dividers.uc_pll_ref_div;
324 fbdiv = dividers.ul_fb_div.ul_fb_divider & 0x3FFFFFF;
328 SPLL_REF_DIV, dividers.uc_pll_ref_div);
330 SPLL_PDIV_A, dividers.uc_pll_post_div);
343 uint32_t vco_freq = clock * dividers.uc_pll_post_div;
366 sclk->SclkDid = (uint8_t)dividers
1382 struct pp_atomctrl_clock_dividers_vi dividers; local
1523 struct pp_atomctrl_clock_dividers_vi dividers; local
1564 struct pp_atomctrl_clock_dividers_vi dividers; local
1596 struct pp_atomctrl_clock_dividers_vi dividers; local
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H A Diceland_smumgr.c799 pp_atomctrl_clock_dividers_vi dividers; local
810 /* get the engine clock dividers for this clock value*/
811 result = atomctrl_get_engine_pll_dividers_vi(hwmgr, engine_clock, &dividers);
814 "Error retrieving Engine Clock dividers from VBIOS.", return result);
819 reference_divider = 1 + dividers.uc_pll_ref_div;
822 fbdiv = dividers.ul_fb_div.ul_fb_divider & 0x3FFFFFF;
826 CG_SPLL_FUNC_CNTL, SPLL_REF_DIV, dividers.uc_pll_ref_div);
828 CG_SPLL_FUNC_CNTL, SPLL_PDIV_A, dividers.uc_pll_post_div);
842 uint32_t vcoFreq = engine_clock * dividers.uc_pll_post_div;
868 sclk->SclkDid = (uint8_t)dividers
1427 struct pp_atomctrl_clock_dividers_vi dividers; local
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/linux-master/drivers/clk/ti/
H A Dclock.h120 int *dividers; member in struct:ti_clk_divider
162 const int *dividers; member in struct:omap_clkctrl_div_data
/linux-master/drivers/clk/stm32/
H A Dclk-stm32-core.h63 const struct stm32_div_cfg *dividers; member in struct:clk_stm32_clock_data
H A Dclk-stm32-core.c213 const struct stm32_div_cfg *divider = &data->dividers[div_id];
236 const struct stm32_div_cfg *divider = &data->dividers[div_id];
364 divider = &div->clock_data->dividers[div->div_id];
442 divider = &composite->clock_data->dividers[composite->div_id];

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