| /linux-master/drivers/gpu/drm/amd/amdgpu/ |
| H A D | atombios_crtc.h | 39 u32 dispclk);
|
| H A D | atombios_crtc.c | 471 u32 dispclk)
492 args.v5.usPixelClock = cpu_to_le16(dispclk);
499 args.v6.ulDispEngClkFreq = cpu_to_le32(dispclk);
470 amdgpu_atombios_crtc_set_disp_eng_pll(struct amdgpu_device *adev, u32 dispclk) argument
|
| /linux-master/drivers/gpu/drm/amd/display/dc/inc/hw/ |
| H A D | clk_mgr.h | 49 uint32_t CLK1_CLK0_CURRENT_CNT; //dispclk
57 uint32_t CLK1_CLK0_BYPASS_CNTL; //dispclk bypass
67 uint32_t CLK1_CLK0_CURRENT_CNT; //dispclk
77 uint32_t CLK1_CLK0_BYPASS_CNTL; //dispclk bypass
86 uint32_t CLK1_CLK0_CURRENT_CNT; //dispclk
93 uint32_t CLK1_CLK0_BYPASS_CNTL; //dispclk bypass
178 uint32_t dispclk; member in struct:clk_state_registers_and_bypass
193 uint32_t CLK0_CLK11_CURRENT_CNT; //dispclk
197 uint32_t CLK0_CLK11_BYPASS_CNTL; //dispclk bypass
201 uint32_t CLK1_CLK0_CURRENT_CNT; //dispclk
[all...] |
| /linux-master/drivers/gpu/drm/amd/display/dc/inc/ |
| H A D | dce_calcs.h | 332 struct bw_fixed dispclk; member in struct:bw_calcs_data
|
| H A D | dcn_calcs.h | 435 float dispclk; member in struct:dcn_bw_internal_vars
|
| /linux-master/drivers/gpu/drm/amd/display/dc/basics/ |
| H A D | dce_calcs.c | 1077 /*the dispclk required is the maximum for all surfaces of the maximum of the source pixels for first output pixel times the throughput factor, divided by the pixels per dispclk, and divided by the minimum latency hiding minus the dram speed/p-state change latency minus the burst time, and the source pixels for last output pixel, times the throughput factor, divided by the pixels per dispclk, and divided by the minimum latency hiding minus the dram speed/p-state change latency minus the burst time, plus the active time.*/
1274 /*for cpu p-state change to be possible for a yclk(pclk) and sclk level the dispclk required has to be enough for the blackout duration*/
1275 /*for cpu c-state change to be possible for a yclk(pclk) and sclk level the dispclk required has to be enough for the blackout duration and recovery*/
1280 /* recovery time > (display bw * blackout duration + (2 * urgent latency + dmif burst time)*dispclk - dmif size )*/
1281 /* / (dispclk - display bw)*/
1368 /*for dram speed/p-state change to be possible for a yclk(pclk) and sclk level there has to be positive margin and the dispclk required has to be*/
1648 /*dispclk*/
1649 /*if dispclk i
[all...] |
| H A D | calcs_logger.h | 332 DC_LOG_BANDWIDTH_CALCS(" [bw_fixed] dispclk: %d", bw_fixed_to_int(data->dispclk));
|
| /linux-master/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn301/ |
| H A D | vg_clk_mgr.c | 251 regs_and_bypass->dispclk = internal.CLK1_CLK0_CURRENT_CNT / 10;
289 chars_printed = snprintf_count(log_info->pBuf, remaining_buffer, "dispclk,%d,N/A,N/A,%s\n",
290 regs_and_bypass->dispclk,
332 chars_printed = snprintf_count(log_info->pBuf, remaining_buffer, "CLK1_CLK0_CURRENT_CNT,%d,dispclk\n",
|
| /linux-master/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn21/ |
| H A D | rn_clk_mgr.c | 319 regs_and_bypass->dispclk = internal.CLK1_CLK0_CURRENT_CNT / 10;
357 chars_printed = snprintf_count(log_info->pBuf, remaining_buffer, "dispclk,%d,N/A,N/A,%s\n",
358 regs_and_bypass->dispclk,
400 chars_printed = snprintf_count(log_info->pBuf, remaining_buffer, "CLK1_CLK0_CURRENT_CNT,%d,dispclk\n",
730 * that needs to limit minimum dispclk */
|
| /linux-master/drivers/gpu/drm/radeon/ |
| H A D | atombios_crtc.c | 767 u32 dispclk)
788 args.v5.usPixelClock = cpu_to_le16(dispclk);
795 args.v6.ulDispEngClkFreq = cpu_to_le32(dispclk);
2032 /* XXX: DCE5, make sure voltage, dispclk is high enough */
766 atombios_crtc_set_disp_eng_pll(struct radeon_device *rdev, u32 dispclk) argument
|
| /linux-master/drivers/gpu/drm/amd/display/dc/dml/calcs/ |
| H A D | dcn_calc_auto.c | 320 /*maximum dispclk/dppclk support check*/
1179 /*dispclk and dppclk calculation*/
1215 v->dispclk = v->dispclk_without_ramping;
1218 v->dispclk = v->max_dispclk[number_of_states];
1221 v->dispclk = v->dispclk_with_ramping;
1223 v->dppclk = v->dispclk / v->dispclk_dppclk_ratio;
1643 v->dstx_after_scaler = 90.0 * v->pixel_clock[k] / v->dppclk + 42.0 * v->pixel_clock[k] / v->dispclk;
1654 v->total_repeater_delay_time = v->max_inter_dcn_tile_repeaters * (2.0 / v->dppclk + 3.0 / v->dispclk);
|
| H A D | dcn_calcs.c | 495 input->clks_cfg.dispclk_mhz = v->dispclk;
684 * disable optional pipe split by lower dispclk bounding box
1165 context->bw_ctx.bw.dcn.clk.dispclk_khz = (int)(v->dispclk * 1000);
|
| /linux-master/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn32/ |
| H A D | dcn32_clk_mgr.c | 403 * SMU uses discrete dispclk presets. We applied
406 * contract, we should use the preset dispclk
450 * SMU uses discrete dispclk presets. We applied
453 * contract, we should use the preset dispclk
640 * we bypass program dispclk and DPPCLK, but need set them for S3.
898 //Get dispclk in khz
899 regs_and_bypass->dispclk = (DENTIST_DIVIDER_RANGE_SCALE_FACTOR
|