Searched refs:config_base (Results 1 - 25 of 64) sorted by relevance

123

/linux-master/arch/arm/mach-bcm/
H A Dbcm63xx_smp.c37 unsigned long config_base; local
47 config_base = scu_a9_get_base();
48 if (!config_base) {
53 scu_base = ioremap((phys_addr_t)config_base, CORTEX_A9_SCU_SIZE);
56 config_base, CORTEX_A9_SCU_SIZE);
H A Dplatsmp.c49 unsigned long config_base; local
58 config_base = scu_a9_get_base();
59 if (!config_base) {
64 scu_base = ioremap((phys_addr_t)config_base, CORTEX_A9_SCU_SIZE);
67 config_base, CORTEX_A9_SCU_SIZE);
/linux-master/arch/arm/kernel/
H A Dperf_event_v7.c899 armv7_pmnc_write_evtsel(idx, hwc->config_base);
1018 unsigned long evtype = hwc->config_base & ARMV7_EVTYPE_EVENT;
1053 unsigned long config_base = 0; local
1060 config_base |= ARMV7_EXCLUDE_USER;
1062 config_base |= ARMV7_EXCLUDE_PL1;
1064 config_base |= ARMV7_INCLUDE_HYP;
1067 * Install the filter into config_base as this is used to
1070 event->config_base = config_base;
1285 * hwc->config_base
1397 krait_evt_setup(int idx, u32 config_base) argument
1454 krait_clearpmu(u32 config_base) argument
1732 scorpion_evt_setup(int idx, u32 config_base) argument
1775 scorpion_clearpmu(u32 config_base) argument
[all...]
H A Dperf_event_xscale.c217 evt = (hwc->config_base << XSCALE1_COUNT0_EVT_SHFT) |
222 evt = (hwc->config_base << XSCALE1_COUNT1_EVT_SHFT) |
271 if (XSCALE_PERFCTR_CCNT == hwc->config_base) {
552 evtsel |= hwc->config_base << XSCALE2_COUNT0_EVT_SHFT;
557 evtsel |= hwc->config_base << XSCALE2_COUNT1_EVT_SHFT;
562 evtsel |= hwc->config_base << XSCALE2_COUNT2_EVT_SHFT;
567 evtsel |= hwc->config_base << XSCALE2_COUNT3_EVT_SHFT;
H A Dperf_event_v6.c217 evt = (hwc->config_base << ARMV6_PMCR_EVT_COUNT0_SHIFT) |
221 evt = (hwc->config_base << ARMV6_PMCR_EVT_COUNT1_SHIFT) |
320 if (ARMV6_PERFCTR_CPU_CYCLES == hwc->config_base) {
/linux-master/drivers/pci/controller/dwc/
H A Dpcie-tegra194-acpi.c17 void __iomem *config_base; member in struct:tegra194_pcie_ecam
31 pcie_ecam->config_base = cfg->win;
99 return pcie_ecam->config_base + where;
/linux-master/drivers/perf/
H A Dapple_m1_cpu_pmu.c86 * but attributes that get stored in hw->config_base.
361 evt = event->hw.config_base & M1_PMU_CFG_EVENT;
362 user = event->hw.config_base & M1_PMU_CFG_COUNT_USER;
363 kernel = event->hw.config_base & M1_PMU_CFG_COUNT_KERNEL;
438 unsigned long evtype = event->hw.config_base & M1_PMU_CFG_EVENT;
525 unsigned long config_base = 0; local
532 config_base |= M1_PMU_CFG_COUNT_KERNEL;
534 config_base |= M1_PMU_CFG_COUNT_USER;
536 event->config_base = config_base;
[all...]
H A Darm_pmuv3.c655 armv8pmu_write_evtype(idx - 1, hwc->config_base);
659 write_pmccfiltr(hwc->config_base);
661 armv8pmu_write_evtype(idx, hwc->config_base);
941 unsigned long evtype = hwc->config_base & ARMV8_PMU_EVTYPE_EVENT;
994 unsigned long config_base = 0; local
1013 config_base |= ARMV8_PMU_INCLUDE_EL2;
1015 config_base |= ARMV8_PMU_EXCLUDE_EL1;
1017 config_base |= ARMV8_PMU_EXCLUDE_EL0;
1020 config_base |= ARMV8_PMU_INCLUDE_EL2;
1027 config_base |
[all...]
H A Dthunderx2_pmu.c332 hwc->config_base = (unsigned long)tx2_pmu->base
347 hwc->config_base = (unsigned long)tx2_pmu->base
362 hwc->config_base = (unsigned long)tx2_pmu->base
378 reg_writel(val, hwc->config_base);
385 reg_writel(0, event->hw.config_base);
405 val = reg_readl(hwc->config_base);
408 reg_writel(val, hwc->config_base);
425 val = reg_readl(hwc->config_base);
427 reg_writel(val, hwc->config_base);
445 GET_EVENTID(event, emask)), hwc->config_base);
[all...]
H A Dqcom_l2_pmu.c347 if (hwc->config_base == L2CYCLE_CTR_RAW_CODE) {
364 group = L2_EVT_GROUP(hwc->config_base);
381 if (hwc->config_base != L2CYCLE_CTR_RAW_CODE)
382 clear_bit(L2_EVT_GROUP(hwc->config_base), cluster->used_groups);
530 hwc->config_base = event->attr.config;
555 if (hwc->config_base == L2CYCLE_CTR_RAW_CODE) {
558 config = hwc->config_base;
H A Darm-ccn.c682 hw->config_base = bit;
703 clear_bit(hw->config_base, source->xp.dt_cmp_mask);
705 clear_bit(hw->config_base, source->pmu_events_mask);
949 unsigned long wp = hw->config_base;
999 hw->event_base = CCN_XP_DT_CONFIG__DT_CFG__XP_PMU_EVENT(hw->config_base);
1007 CCN_XP_PMU_EVENT_SEL__ID__SHIFT(hw->config_base));
1008 val |= id << CCN_XP_PMU_EVENT_SEL__ID__SHIFT(hw->config_base);
1023 hw->config_base);
1043 CCN_HNF_PMU_EVENT_SEL__ID__SHIFT(hw->config_base));
1045 CCN_HNF_PMU_EVENT_SEL__ID__SHIFT(hw->config_base);
[all...]
/linux-master/arch/x86/events/zhaoxin/
H A Dcore.c296 rdmsrl(hwc->config_base, ctrl_val);
298 wrmsrl(hwc->config_base, ctrl_val);
305 if (unlikely(hwc->config_base == MSR_ARCH_PERFMON_FIXED_CTR_CTRL)) {
332 rdmsrl(hwc->config_base, ctrl_val);
335 wrmsrl(hwc->config_base, ctrl_val);
342 if (unlikely(hwc->config_base == MSR_ARCH_PERFMON_FIXED_CTR_CTRL)) {
/linux-master/drivers/gpu/drm/amd/amdgpu/
H A Damdgpu_pmu.c219 hwc->config_base = AMDGPU_PMU_PERF_TYPE_NONE;
243 switch (hwc->config_base) {
281 switch (hwc->config_base) {
311 switch (hwc->config_base) {
346 hwc->config_base = AMDGPU_PMU_EVENT_CONFIG_TYPE_DF;
349 hwc->config_base = (hwc->config >>
357 switch (hwc->config_base) {
395 switch (hwc->config_base) {
/linux-master/arch/s390/include/asm/
H A Dperf_event.h71 #define SAMPL_FLAGS(hwc) ((hwc)->config_base)
/linux-master/arch/loongarch/kernel/
H A Dperf_event.c275 (evt->config_base & M_PERFCTL_CONFIG_MASK) | CSR_PERFCTRL_IE;
780 hwc->config_base = CSR_PERFCTRL_IE;
787 hwc->config_base |= CSR_PERFCTRL_PLV3;
788 hwc->config_base |= CSR_PERFCTRL_PLV2;
791 hwc->config_base |= CSR_PERFCTRL_PLV0;
794 hwc->config_base |= CSR_PERFCTRL_PLV1;
797 hwc->config_base &= M_PERFCTL_CONFIG_MASK;
/linux-master/arch/x86/events/intel/
H A Duncore_discovery.c389 wrmsrl(hwc->config_base, hwc->config);
397 wrmsrl(hwc->config_base, 0);
440 pci_write_config_dword(pdev, hwc->config_base, hwc->config);
449 pci_write_config_dword(pdev, hwc->config_base, 0);
534 writel(hwc->config, box->io_addr + hwc->config_base);
545 writel(0, box->io_addr + hwc->config_base);
H A Dknc.c185 (void)wrmsrl_safe(hwc->config_base + hwc->idx, val);
196 (void)wrmsrl_safe(hwc->config_base + hwc->idx, val);
H A Dp6.c164 (void)wrmsrl_safe(hwc->config_base, val);
181 (void)wrmsrl_safe(hwc->config_base, val);
H A Duncore_nhmex.c242 wrmsrl(event->hw.config_base, 0);
250 wrmsrl(hwc->config_base, NHMEX_PMON_CTL_EN_BIT0);
252 wrmsrl(hwc->config_base, hwc->config | NHMEX_PMON_CTL_EN_BIT22);
254 wrmsrl(hwc->config_base, hwc->config | NHMEX_PMON_CTL_EN_BIT0);
387 wrmsrl(hwc->config_base, NHMEX_PMON_CTL_EN_BIT0 |
474 wrmsrl(hwc->config_base, hwc->config | NHMEX_PMON_CTL_EN_BIT22);
862 wrmsrl(hwc->config_base, hwc->config | NHMEX_PMON_CTL_EN_BIT0);
1147 wrmsrl(hwc->config_base, NHMEX_PMON_CTL_EN_BIT0 |
/linux-master/arch/s390/kernel/
H A Dperf_cpum_cf.c801 * set number in the 'config_base' as bit mask.
805 hwc->config_base = cpumf_ctr_ctl[set];
823 if (!(hwc->config_base & cpumf_ctr_info.auth_ctl))
927 ctr_set_enable(&cpuhw->state, hwc->config_base);
928 ctr_set_start(&cpuhw->state, hwc->config_base);
938 hwc->config_base, true);
945 if ((hwc->config_base & cpumf_ctr_ctl[i]))
997 if (!(hwc->config_base & cpumf_ctr_ctl[i]))
1010 event->hw.config_base,
1012 if (cfdiag_diffctr(cpuhw, event->hw.config_base))
[all...]
/linux-master/include/pcmcia/
H A Dds.h111 unsigned int config_base; member in struct:pcmcia_device
/linux-master/arch/alpha/kernel/
H A Dperf_event.c200 event[0]->hw.config_base = config;
203 event[1]->hw.config_base = config;
424 cpuc->config = cpuc->event[0]->hw.config_base;
638 * PMU is put into config_base and the PMC to use is placed into
663 hwc->config_base = 0;
/linux-master/drivers/perf/hisilicon/
H A Dhisi_uncore_pmu.h46 #define HISI_GET_EVENTID(ev) (ev->hw.config_base & 0xff)
/linux-master/arch/powerpc/perf/
H A Dcore-fsl-emb.c327 write_pmlca(i, event->hw.config_base);
536 event->hw.config_base = PMLCA_CE | PMLCA_FCM1 |
540 event->hw.config_base |= PMLCA_FCU;
542 event->hw.config_base |= PMLCA_FCS;
/linux-master/arch/x86/events/amd/
H A Dibs.c328 hwc->config_base = perf_ibs->msr;
386 rdmsrl(event->hw.config_base, *config);
397 wrmsrl(hwc->config_base, tmp & ~perf_ibs->enable_mask);
399 wrmsrl(hwc->config_base, tmp | perf_ibs->enable_mask);
414 wrmsrl(hwc->config_base, config);
416 wrmsrl(hwc->config_base, config);
472 rdmsrl(hwc->config_base, config);
1053 msr = hwc->config_base;

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