Searched refs:clkrate (Results 1 - 25 of 26) sorted by relevance

12

/linux-master/arch/arm/mach-omap1/
H A Di2c.h18 extern int omap_register_i2c_bus(int bus_id, u32 clkrate,
23 static inline int omap_register_i2c_bus(int bus_id, u32 clkrate, argument
H A Di2c.c85 * Format: i2c_bus=bus_id,clkrate (in kHz)
97 i2c_pdata[ints[1] - 1].clkrate = ints[2];
98 i2c_pdata[ints[1] - 1].clkrate |= OMAP_I2C_CMDLINE_SETUP;
113 if (i2c_pdata[i].clkrate & OMAP_I2C_CMDLINE_SETUP) {
114 i2c_pdata[i].clkrate &= ~OMAP_I2C_CMDLINE_SETUP;
127 * @clkrate: clock rate of the bus in kHz
133 int __init omap_register_i2c_bus(int bus_id, u32 clkrate, argument
147 if (!i2c_pdata[bus_id - 1].clkrate)
148 i2c_pdata[bus_id - 1].clkrate = clkrate;
[all...]
/linux-master/drivers/w1/masters/
H A Dmxc_w1.c94 unsigned long clkrate; local
111 clkrate = clk_get_rate(mdev->clk);
112 if (clkrate < 10000000)
116 clkdiv = DIV_ROUND_CLOSEST(clkrate, 1000000);
117 clkrate /= clkdiv;
118 if ((clkrate < 980000) || (clkrate > 1020000))
120 "Incorrect time base frequency %lu Hz\n", clkrate);
/linux-master/include/linux/platform_data/
H A Di2c-omap.h33 u32 clkrate; member in struct:omap_i2c_bus_platform_data
/linux-master/drivers/pwm/
H A Dpwm-apple.c36 u64 clkrate; member in struct:apple_pwm
56 on_cycles = mul_u64_u64_div_u64(fpwm->clkrate,
61 off_cycles = mul_u64_u64_div_u64(fpwm->clkrate,
91 state->duty_cycle = DIV64_U64_ROUND_UP((u64)on_cycles * NSEC_PER_SEC, fpwm->clkrate);
93 NSEC_PER_SEC, fpwm->clkrate);
130 fpwm->clkrate = clk_get_rate(clk);
131 if (fpwm->clkrate > NSEC_PER_SEC)
H A Dpwm-atmel.c192 unsigned long clkrate,
201 cycles *= clkrate;
227 unsigned long clkrate, unsigned long cprd,
232 cycles *= clkrate;
301 unsigned long clkrate = clk_get_rate(atmel_pwm->clk); local
312 atmel_pwm_calculate_cdty(state, clkrate, cprd, pres, &cdty);
317 ret = atmel_pwm_calculate_cprd_and_pres(chip, clkrate, state, &cprd,
325 atmel_pwm_calculate_cdty(state, clkrate, cprd, pres, &cdty);
191 atmel_pwm_calculate_cprd_and_pres(struct pwm_chip *chip, unsigned long clkrate, const struct pwm_state *state, unsigned long *cprd, u32 *pres) argument
226 atmel_pwm_calculate_cdty(const struct pwm_state *state, unsigned long clkrate, unsigned long cprd, u32 pres, unsigned long *cdty) argument
H A Dpwm-imx27.c225 unsigned long long clkrate; local
229 clkrate = clk_get_rate(imx->clk_per);
230 c = clkrate * state->period;
238 c = clkrate * state->duty_cycle;
/linux-master/drivers/watchdog/
H A Dst_lpc_wdt.c46 unsigned long clkrate; member in struct:st_wdog
82 unsigned long clkrate = st_wdog->clkrate; local
84 writel_relaxed(timeout * clkrate, st_wdog->base + LPC_LPA_LSB_OFF);
197 st_wdog->clkrate = clk_get_rate(st_wdog->clk);
199 if (!st_wdog->clkrate) {
203 st_wdog_dev.max_timeout = 0xFFFFFFFF / st_wdog->clkrate;
/linux-master/drivers/rtc/
H A Drtc-st-lpc.c45 unsigned long clkrate; member in struct:st_rtc
96 do_div(lpt, rtc->clkrate);
110 lpt = (unsigned long long)secs * rtc->clkrate;
168 lpa = (unsigned long long)alarm_secs * rtc->clkrate;
236 rtc->clkrate = clk_get_rate(rtc->clk);
237 if (!rtc->clkrate) {
248 do_div(rtc->rtc_dev->range_max, rtc->clkrate);
/linux-master/drivers/i2c/busses/
H A Di2c-lpc2k.c350 u32 clkrate; local
390 clkrate = clk_get_rate(i2c->clk);
391 if (clkrate == 0) {
397 clkrate = clkrate / bus_clk_rate;
399 scl_high = (clkrate * I2C_STD_MODE_DUTY) / 100;
401 scl_high = (clkrate * I2C_FAST_MODE_DUTY) / 100;
403 scl_high = (clkrate * I2C_FAST_MODE_PLUS_DUTY) / 100;
406 writel(clkrate - scl_high, i2c->base + LPC24XX_I2SCLL);
H A Di2c-s3c2410.c109 unsigned long clkrate; member in struct:s3c24xx_i2c
850 i2c->clkrate = clkin;
/linux-master/drivers/ata/
H A Dpata_imx.c59 unsigned long clkrate; local
62 clkrate = clk_get_rate(priv->clk);
65 !clkrate)
68 T = 1000000000 / clkrate;
/linux-master/drivers/spi/
H A Dspi-npcm-fiu.c242 unsigned long clkrate; member in struct:npcm_fiu_chip
252 unsigned long clkrate; member in struct:npcm_fiu_spi
561 if (fiu->clkrate != chip->clkrate) {
562 ret = clk_set_rate(fiu->clk, chip->clkrate);
565 chip->clkrate, fiu->clkrate);
567 fiu->clkrate = chip->clkrate;
676 chip->clkrate
[all...]
H A Dspi-fsl-dspi.c597 unsigned long clkrate)
608 scale_needed = clkrate / speed_hz;
609 if (clkrate % speed_hz)
626 pr_warn("Can not find valid baud rate,speed_hz is %d,clkrate is %ld, we use the max prescaler value.\n",
627 speed_hz, clkrate);
634 unsigned long clkrate)
641 scale_needed = div_u64_rem((u64)delay_ns * clkrate, NSEC_PER_SEC,
660 pr_warn("Cannot find correct scale values for %dns delay at clkrate %ld, using max prescaler value",
661 delay_ns, clkrate);
1007 unsigned long clkrate; local
596 hz_to_spi_baud(char *pbr, char *br, int speed_hz, unsigned long clkrate) argument
633 ns_delay_scale(char *psc, char *sc, int delay_ns, unsigned long clkrate) argument
[all...]
/linux-master/drivers/mtd/nand/raw/
H A Dlpc32xx_mlc.c233 uint32_t clkrate, tmp; local
240 clkrate = clk_get_rate(host->clk);
241 if (clkrate == 0)
242 clkrate = 104000000;
258 tmp |= MLCTIMEREG_TCEA_DELAY(clkrate / host->ncfg->tcea_delay + 1);
259 tmp |= MLCTIMEREG_BUSY_DELAY(clkrate / host->ncfg->busy_delay + 1);
260 tmp |= MLCTIMEREG_NAND_TA(clkrate / host->ncfg->nand_ta + 1);
261 tmp |= MLCTIMEREG_RD_HIGH(clkrate / host->ncfg->rd_high + 1);
262 tmp |= MLCTIMEREG_RD_LOW(clkrate / host->ncfg->rd_low);
263 tmp |= MLCTIMEREG_WR_HIGH(clkrate / hos
[all...]
H A Dlpc32xx_slc.c238 uint32_t clkrate, tmp; local
251 clkrate = clk_get_rate(host->clk);
252 if (clkrate == 0)
253 clkrate = LPC32XX_DEF_BUS_RATE;
257 SLCTAC_WWIDTH(clkrate, host->ncfg->wwidth) |
258 SLCTAC_WHOLD(clkrate, host->ncfg->whold) |
259 SLCTAC_WSETUP(clkrate, host->ncfg->wsetup) |
261 SLCTAC_RWIDTH(clkrate, host->ncfg->rwidth) |
262 SLCTAC_RHOLD(clkrate, host->ncfg->rhold) |
263 SLCTAC_RSETUP(clkrate, hos
[all...]
H A Ds3c2410.c287 unsigned long clkrate = clk_get_rate(info->clk); local
293 info->clk_rate = clkrate;
294 clkrate /= 1000; /* turn clock into kHz for ease of use */
297 tacls = s3c_nand_calc_rate(plat->tacls, clkrate, tacls_max);
298 twrph0 = s3c_nand_calc_rate(plat->twrph0, clkrate, 8);
299 twrph1 = s3c_nand_calc_rate(plat->twrph1, clkrate, 8);
313 tacls, to_ns(tacls, clkrate), twrph0, to_ns(twrph0, clkrate),
314 twrph1, to_ns(twrph1, clkrate));
/linux-master/drivers/net/dsa/sja1105/
H A Dsja1105_ptp.c611 s64 clkrate; local
614 clkrate = (s64)scaled_ppm * SJA1105_CC_MULT_NUM;
615 clkrate = div_s64(clkrate, SJA1105_CC_MULT_DEM);
618 clkrate = SJA1105_CC_MULT + clkrate;
619 WARN_ON(abs(clkrate) >= GENMASK_ULL(31, 0));
620 clkrate32 = clkrate;
/linux-master/drivers/gpu/ipu-v3/
H A Dipu-di.c440 unsigned long rate, clkrate; local
443 clkrate = clk_get_rate(di->clk_ipu);
444 div = DIV_ROUND_CLOSEST(clkrate, sig->mode.pixelclock);
446 rate = clkrate / div;
/linux-master/drivers/gpu/drm/arm/
H A Dhdlcd_drv.c212 unsigned long clkrate = clk_get_rate(hdlcd->clk); local
215 seq_printf(m, "hw : %lu\n", clkrate);
/linux-master/drivers/mmc/host/
H A Dpxamci.c55 unsigned long clkrate; member in struct:pxamci_host
174 clks = (unsigned long long)data->timeout_ns * host->clkrate;
445 unsigned long rate = host->clkrate;
663 host->clkrate = clk_get_rate(host->clk);
668 mmc->f_min = (host->clkrate + 63) / 64;
669 mmc->f_max = (mmc_has_26MHz()) ? 26000000 : host->clkrate;
/linux-master/drivers/mtd/spi-nor/controllers/
H A Dhisi-sfc.c84 u32 clkrate; member in struct:hifmc_priv
155 ret = clk_set_rate(host->clk, priv->clkrate);
361 &priv->clkrate);
/linux-master/drivers/gpu/drm/tiny/
H A Darcpgu.c344 unsigned long clkrate = clk_get_rate(arcpgu->clk); local
347 seq_printf(m, "hw : %lu\n", clkrate);
/linux-master/sound/soc/fsl/
H A Dfsl_ssi.c687 unsigned long clkrate, baudrate, tmprate; local
735 clkrate = clk_get_rate(ssi->baudclk);
737 clkrate = clk_round_rate(ssi->baudclk, tmprate);
739 clkrate /= factor;
740 afreq = clkrate / (i + 1);
/linux-master/drivers/media/i2c/
H A Dgc0308.c1293 unsigned long clkrate; local
1363 clkrate = clk_get_rate(gc0308->clk);
1364 if (clkrate != 24000000)
1365 dev_warn(dev, "unexpected clock rate: %lu\n", clkrate);

Completed in 522 milliseconds

12