1// SPDX-License-Identifier: GPL-2.0 2/* 3 * Driver for the GalaxyCore GC0308 camera sensor. 4 * 5 * Copyright (c) 2023 Sebastian Reichel <sre@kernel.org> 6 */ 7 8#include <linux/clk.h> 9#include <linux/device.h> 10#include <linux/gpio/consumer.h> 11#include <linux/i2c.h> 12#include <linux/module.h> 13#include <linux/mod_devicetable.h> 14#include <linux/pm_runtime.h> 15#include <linux/regmap.h> 16#include <linux/regulator/consumer.h> 17 18#include <media/v4l2-cci.h> 19#include <media/v4l2-ctrls.h> 20#include <media/v4l2-device.h> 21#include <media/v4l2-event.h> 22#include <media/v4l2-fwnode.h> 23#include <media/v4l2-subdev.h> 24 25/* Analog & CISCTL*/ 26#define GC0308_CHIP_ID CCI_REG8(0x000) 27#define GC0308_HBLANK CCI_REG8(0x001) 28#define GC0308_VBLANK CCI_REG8(0x002) 29#define GC0308_EXP CCI_REG16(0x003) 30#define GC0308_ROW_START CCI_REG16(0x005) 31#define GC0308_COL_START CCI_REG16(0x007) 32#define GC0308_WIN_HEIGHT CCI_REG16(0x009) 33#define GC0308_WIN_WIDTH CCI_REG16(0x00b) 34#define GC0308_VS_START_TIME CCI_REG8(0x00d) /* in rows */ 35#define GC0308_VS_END_TIME CCI_REG8(0x00e) /* in rows */ 36#define GC0308_VB_HB CCI_REG8(0x00f) 37#define GC0308_RSH_WIDTH CCI_REG8(0x010) 38#define GC0308_TSP_WIDTH CCI_REG8(0x011) 39#define GC0308_SAMPLE_HOLD_DELAY CCI_REG8(0x012) 40#define GC0308_ROW_TAIL_WIDTH CCI_REG8(0x013) 41#define GC0308_CISCTL_MODE1 CCI_REG8(0x014) 42#define GC0308_CISCTL_MODE2 CCI_REG8(0x015) 43#define GC0308_CISCTL_MODE3 CCI_REG8(0x016) 44#define GC0308_CISCTL_MODE4 CCI_REG8(0x017) 45#define GC0308_ANALOG_MODE1 CCI_REG8(0x01a) 46#define GC0308_ANALOG_MODE2 CCI_REG8(0x01b) 47#define GC0308_HRST_RSG_V18 CCI_REG8(0x01c) 48#define GC0308_VREF_V25 CCI_REG8(0x01d) 49#define GC0308_ADC_R CCI_REG8(0x01e) 50#define GC0308_PAD_DRV CCI_REG8(0x01f) 51#define GC0308_SOFT_RESET CCI_REG8(0x0fe) 52 53/* ISP */ 54#define GC0308_BLOCK_EN1 CCI_REG8(0x020) 55#define GC0308_BLOCK_EN2 CCI_REG8(0x021) 56#define GC0308_AAAA_EN CCI_REG8(0x022) 57#define GC0308_SPECIAL_EFFECT CCI_REG8(0x023) 58#define GC0308_OUT_FORMAT CCI_REG8(0x024) 59#define GC0308_OUT_EN CCI_REG8(0x025) 60#define GC0308_SYNC_MODE CCI_REG8(0x026) 61#define GC0308_CLK_DIV_MODE CCI_REG8(0x028) 62#define GC0308_BYPASS_MODE CCI_REG8(0x029) 63#define GC0308_CLK_GATING CCI_REG8(0x02a) 64#define GC0308_DITHER_MODE CCI_REG8(0x02b) 65#define GC0308_DITHER_BIT CCI_REG8(0x02c) 66#define GC0308_DEBUG_MODE1 CCI_REG8(0x02d) 67#define GC0308_DEBUG_MODE2 CCI_REG8(0x02e) 68#define GC0308_DEBUG_MODE3 CCI_REG8(0x02f) 69#define GC0308_CROP_WIN_MODE CCI_REG8(0x046) 70#define GC0308_CROP_WIN_Y1 CCI_REG8(0x047) 71#define GC0308_CROP_WIN_X1 CCI_REG8(0x048) 72#define GC0308_CROP_WIN_HEIGHT CCI_REG16(0x049) 73#define GC0308_CROP_WIN_WIDTH CCI_REG16(0x04b) 74 75/* BLK */ 76#define GC0308_BLK_MODE CCI_REG8(0x030) 77#define GC0308_BLK_LIMIT_VAL CCI_REG8(0x031) 78#define GC0308_GLOBAL_OFF CCI_REG8(0x032) 79#define GC0308_CURRENT_R_OFF CCI_REG8(0x033) 80#define GC0308_CURRENT_G_OFF CCI_REG8(0x034) 81#define GC0308_CURRENT_B_OFF CCI_REG8(0x035) 82#define GC0308_CURRENT_R_DARK_CURRENT CCI_REG8(0x036) 83#define GC0308_CURRENT_G_DARK_CURRENT CCI_REG8(0x037) 84#define GC0308_CURRENT_B_DARK_CURRENT CCI_REG8(0x038) 85#define GC0308_EXP_RATE_DARKC CCI_REG8(0x039) 86#define GC0308_OFF_SUBMODE CCI_REG8(0x03a) 87#define GC0308_DARKC_SUBMODE CCI_REG8(0x03b) 88#define GC0308_MANUAL_G1_OFF CCI_REG8(0x03c) 89#define GC0308_MANUAL_R1_OFF CCI_REG8(0x03d) 90#define GC0308_MANUAL_B2_OFF CCI_REG8(0x03e) 91#define GC0308_MANUAL_G2_OFF CCI_REG8(0x03f) 92 93/* PREGAIN */ 94#define GC0308_GLOBAL_GAIN CCI_REG8(0x050) 95#define GC0308_AUTO_PREGAIN CCI_REG8(0x051) 96#define GC0308_AUTO_POSTGAIN CCI_REG8(0x052) 97#define GC0308_CHANNEL_GAIN_G1 CCI_REG8(0x053) 98#define GC0308_CHANNEL_GAIN_R CCI_REG8(0x054) 99#define GC0308_CHANNEL_GAIN_B CCI_REG8(0x055) 100#define GC0308_CHANNEL_GAIN_G2 CCI_REG8(0x056) 101#define GC0308_R_RATIO CCI_REG8(0x057) 102#define GC0308_G_RATIO CCI_REG8(0x058) 103#define GC0308_B_RATIO CCI_REG8(0x059) 104#define GC0308_AWB_R_GAIN CCI_REG8(0x05a) 105#define GC0308_AWB_G_GAIN CCI_REG8(0x05b) 106#define GC0308_AWB_B_GAIN CCI_REG8(0x05c) 107#define GC0308_LSC_DEC_LVL1 CCI_REG8(0x05d) 108#define GC0308_LSC_DEC_LVL2 CCI_REG8(0x05e) 109#define GC0308_LSC_DEC_LVL3 CCI_REG8(0x05f) 110 111/* DNDD */ 112#define GC0308_DN_MODE_EN CCI_REG8(0x060) 113#define GC0308_DN_MODE_RATIO CCI_REG8(0x061) 114#define GC0308_DN_BILAT_B_BASE CCI_REG8(0x062) 115#define GC0308_DN_B_INCR CCI_REG8(0x063) 116#define GC0308_DN_BILAT_N_BASE CCI_REG8(0x064) 117#define GC0308_DN_N_INCR CCI_REG8(0x065) 118#define GC0308_DD_DARK_BRIGHT_TH CCI_REG8(0x066) 119#define GC0308_DD_FLAT_TH CCI_REG8(0x067) 120#define GC0308_DD_LIMIT CCI_REG8(0x068) 121 122/* ASDE - Auto Saturation De-noise and Edge-Enhancement */ 123#define GC0308_ASDE_GAIN_TRESH CCI_REG8(0x069) 124#define GC0308_ASDE_GAIN_MODE CCI_REG8(0x06a) 125#define GC0308_ASDE_DN_SLOPE CCI_REG8(0x06b) 126#define GC0308_ASDE_DD_BRIGHT CCI_REG8(0x06c) 127#define GC0308_ASDE_DD_LIMIT CCI_REG8(0x06d) 128#define GC0308_ASDE_AUTO_EE1 CCI_REG8(0x06e) 129#define GC0308_ASDE_AUTO_EE2 CCI_REG8(0x06f) 130#define GC0308_ASDE_AUTO_SAT_DEC_SLOPE CCI_REG8(0x070) 131#define GC0308_ASDE_AUTO_SAT_LOW_LIMIT CCI_REG8(0x071) 132 133/* INTPEE - Interpolation and Edge-Enhancement */ 134#define GC0308_EEINTP_MODE_1 CCI_REG8(0x072) 135#define GC0308_EEINTP_MODE_2 CCI_REG8(0x073) 136#define GC0308_DIRECTION_TH1 CCI_REG8(0x074) 137#define GC0308_DIRECTION_TH2 CCI_REG8(0x075) 138#define GC0308_DIFF_HV_TI_TH CCI_REG8(0x076) 139#define GC0308_EDGE12_EFFECT CCI_REG8(0x077) 140#define GC0308_EDGE_POS_RATIO CCI_REG8(0x078) 141#define GC0308_EDGE1_MINMAX CCI_REG8(0x079) 142#define GC0308_EDGE2_MINMAX CCI_REG8(0x07a) 143#define GC0308_EDGE12_TH CCI_REG8(0x07b) 144#define GC0308_EDGE_MAX CCI_REG8(0x07c) 145 146/* ABB - Auto Black Balance */ 147#define GC0308_ABB_MODE CCI_REG8(0x080) 148#define GC0308_ABB_TARGET_AVGH CCI_REG8(0x081) 149#define GC0308_ABB_TARGET_AVGL CCI_REG8(0x082) 150#define GC0308_ABB_LIMIT_VAL CCI_REG8(0x083) 151#define GC0308_ABB_SPEED CCI_REG8(0x084) 152#define GC0308_CURR_R_BLACK_LVL CCI_REG8(0x085) 153#define GC0308_CURR_G_BLACK_LVL CCI_REG8(0x086) 154#define GC0308_CURR_B_BLACK_LVL CCI_REG8(0x087) 155#define GC0308_CURR_R_BLACK_FACTOR CCI_REG8(0x088) 156#define GC0308_CURR_G_BLACK_FACTOR CCI_REG8(0x089) 157#define GC0308_CURR_B_BLACK_FACTOR CCI_REG8(0x08a) 158 159/* LSC - Lens Shading Correction */ 160#define GC0308_LSC_RED_B2 CCI_REG8(0x08b) 161#define GC0308_LSC_GREEN_B2 CCI_REG8(0x08c) 162#define GC0308_LSC_BLUE_B2 CCI_REG8(0x08d) 163#define GC0308_LSC_RED_B4 CCI_REG8(0x08e) 164#define GC0308_LSC_GREEN_B4 CCI_REG8(0x08f) 165#define GC0308_LSC_BLUE_B4 CCI_REG8(0x090) 166#define GC0308_LSC_ROW_CENTER CCI_REG8(0x091) 167#define GC0308_LSC_COL_CENTER CCI_REG8(0x092) 168 169/* CC - Channel Coefficient */ 170#define GC0308_CC_MATRIX_C11 CCI_REG8(0x093) 171#define GC0308_CC_MATRIX_C12 CCI_REG8(0x094) 172#define GC0308_CC_MATRIX_C13 CCI_REG8(0x095) 173#define GC0308_CC_MATRIX_C21 CCI_REG8(0x096) 174#define GC0308_CC_MATRIX_C22 CCI_REG8(0x097) 175#define GC0308_CC_MATRIX_C23 CCI_REG8(0x098) 176#define GC0308_CC_MATRIX_C41 CCI_REG8(0x09c) 177#define GC0308_CC_MATRIX_C42 CCI_REG8(0x09d) 178#define GC0308_CC_MATRIX_C43 CCI_REG8(0x09e) 179 180/* GAMMA */ 181#define GC0308_GAMMA_OUT0 CCI_REG8(0x09f) 182#define GC0308_GAMMA_OUT1 CCI_REG8(0x0a0) 183#define GC0308_GAMMA_OUT2 CCI_REG8(0x0a1) 184#define GC0308_GAMMA_OUT3 CCI_REG8(0x0a2) 185#define GC0308_GAMMA_OUT4 CCI_REG8(0x0a3) 186#define GC0308_GAMMA_OUT5 CCI_REG8(0x0a4) 187#define GC0308_GAMMA_OUT6 CCI_REG8(0x0a5) 188#define GC0308_GAMMA_OUT7 CCI_REG8(0x0a6) 189#define GC0308_GAMMA_OUT8 CCI_REG8(0x0a7) 190#define GC0308_GAMMA_OUT9 CCI_REG8(0x0a8) 191#define GC0308_GAMMA_OUT10 CCI_REG8(0x0a9) 192#define GC0308_GAMMA_OUT11 CCI_REG8(0x0aa) 193#define GC0308_GAMMA_OUT12 CCI_REG8(0x0ab) 194#define GC0308_GAMMA_OUT13 CCI_REG8(0x0ac) 195#define GC0308_GAMMA_OUT14 CCI_REG8(0x0ad) 196#define GC0308_GAMMA_OUT15 CCI_REG8(0x0ae) 197#define GC0308_GAMMA_OUT16 CCI_REG8(0x0af) 198 199/* YCP */ 200#define GC0308_GLOBAL_SATURATION CCI_REG8(0x0b0) 201#define GC0308_SATURATION_CB CCI_REG8(0x0b1) 202#define GC0308_SATURATION_CR CCI_REG8(0x0b2) 203#define GC0308_LUMA_CONTRAST CCI_REG8(0x0b3) 204#define GC0308_CONTRAST_CENTER CCI_REG8(0x0b4) 205#define GC0308_LUMA_OFFSET CCI_REG8(0x0b5) 206#define GC0308_SKIN_CB_CENTER CCI_REG8(0x0b6) 207#define GC0308_SKIN_CR_CENTER CCI_REG8(0x0b7) 208#define GC0308_SKIN_RADIUS_SQUARE CCI_REG8(0x0b8) 209#define GC0308_SKIN_BRIGHTNESS CCI_REG8(0x0b9) 210#define GC0308_FIXED_CB CCI_REG8(0x0ba) 211#define GC0308_FIXED_CR CCI_REG8(0x0bb) 212#define GC0308_EDGE_DEC_SA CCI_REG8(0x0bd) 213#define GC0308_AUTO_GRAY_MODE CCI_REG8(0x0be) 214#define GC0308_SATURATION_SUB_STRENGTH CCI_REG8(0x0bf) 215#define GC0308_Y_GAMMA_OUT0 CCI_REG8(0x0c0) 216#define GC0308_Y_GAMMA_OUT1 CCI_REG8(0x0c1) 217#define GC0308_Y_GAMMA_OUT2 CCI_REG8(0x0c2) 218#define GC0308_Y_GAMMA_OUT3 CCI_REG8(0x0c3) 219#define GC0308_Y_GAMMA_OUT4 CCI_REG8(0x0c4) 220#define GC0308_Y_GAMMA_OUT5 CCI_REG8(0x0c5) 221#define GC0308_Y_GAMMA_OUT6 CCI_REG8(0x0c6) 222#define GC0308_Y_GAMMA_OUT7 CCI_REG8(0x0c7) 223#define GC0308_Y_GAMMA_OUT8 CCI_REG8(0x0c8) 224#define GC0308_Y_GAMMA_OUT9 CCI_REG8(0x0c9) 225#define GC0308_Y_GAMMA_OUT10 CCI_REG8(0x0ca) 226#define GC0308_Y_GAMMA_OUT11 CCI_REG8(0x0cb) 227#define GC0308_Y_GAMMA_OUT12 CCI_REG8(0x0cc) 228 229/* AEC - Automatic Exposure Control */ 230#define GC0308_AEC_MODE1 CCI_REG8(0x0d0) 231#define GC0308_AEC_MODE2 CCI_REG8(0x0d1) 232#define GC0308_AEC_MODE3 CCI_REG8(0x0d2) 233#define GC0308_AEC_TARGET_Y CCI_REG8(0x0d3) 234#define GC0308_Y_AVG CCI_REG8(0x0d4) 235#define GC0308_AEC_HIGH_LOW_RANGE CCI_REG8(0x0d5) 236#define GC0308_AEC_IGNORE CCI_REG8(0x0d6) 237#define GC0308_AEC_LIMIT_HIGH_RANGE CCI_REG8(0x0d7) 238#define GC0308_AEC_R_OFFSET CCI_REG8(0x0d9) 239#define GC0308_AEC_GB_OFFSET CCI_REG8(0x0da) 240#define GC0308_AEC_SLOW_MARGIN CCI_REG8(0x0db) 241#define GC0308_AEC_FAST_MARGIN CCI_REG8(0x0dc) 242#define GC0308_AEC_EXP_CHANGE_GAIN CCI_REG8(0x0dd) 243#define GC0308_AEC_STEP2_SUNLIGHT CCI_REG8(0x0de) 244#define GC0308_AEC_I_FRAMES CCI_REG8(0x0df) 245#define GC0308_AEC_I_STOP_L_MARGIN CCI_REG8(0x0e0) 246#define GC0308_AEC_I_STOP_MARGIN CCI_REG8(0x0e1) 247#define GC0308_ANTI_FLICKER_STEP CCI_REG16(0x0e2) 248#define GC0308_EXP_LVL_1 CCI_REG16(0x0e4) 249#define GC0308_EXP_LVL_2 CCI_REG16(0x0e6) 250#define GC0308_EXP_LVL_3 CCI_REG16(0x0e8) 251#define GC0308_EXP_LVL_4 CCI_REG16(0x0ea) 252#define GC0308_MAX_EXP_LVL CCI_REG8(0x0ec) 253#define GC0308_EXP_MIN_L CCI_REG8(0x0ed) 254#define GC0308_MAX_POST_DF_GAIN CCI_REG8(0x0ee) 255#define GC0308_MAX_PRE_DG_GAIN CCI_REG8(0x0ef) 256 257/* ABS */ 258#define GC0308_ABS_RANGE_COMP CCI_REG8(0x0f0) 259#define GC0308_ABS_STOP_MARGIN CCI_REG8(0x0f1) 260#define GC0308_Y_S_COMP CCI_REG8(0x0f2) 261#define GC0308_Y_STRETCH_LIMIT CCI_REG8(0x0f3) 262#define GC0308_Y_TILT CCI_REG8(0x0f4) 263#define GC0308_Y_STRETCH CCI_REG8(0x0f5) 264 265/* Measure Window */ 266#define GC0308_BIG_WIN_X0 CCI_REG8(0x0f7) 267#define GC0308_BIG_WIN_Y0 CCI_REG8(0x0f8) 268#define GC0308_BIG_WIN_X1 CCI_REG8(0x0f9) 269#define GC0308_BIG_WIN_Y1 CCI_REG8(0x0fa) 270#define GC0308_DIFF_Y_BIG_THD CCI_REG8(0x0fb) 271 272/* OUT Module (P1) */ 273#define GC0308_CLOSE_FRAME_EN CCI_REG8(0x150) 274#define GC0308_CLOSE_FRAME_NUM1 CCI_REG8(0x151) 275#define GC0308_CLOSE_FRAME_NUM2 CCI_REG8(0x152) 276#define GC0308_BAYER_MODE CCI_REG8(0x153) 277#define GC0308_SUBSAMPLE CCI_REG8(0x154) 278#define GC0308_SUBMODE CCI_REG8(0x155) 279#define GC0308_SUB_ROW_N1 CCI_REG8(0x156) 280#define GC0308_SUB_ROW_N2 CCI_REG8(0x157) 281#define GC0308_SUB_COL_N1 CCI_REG8(0x158) 282#define GC0308_SUB_COL_N2 CCI_REG8(0x159) 283 284/* AWB (P1) - Auto White Balance */ 285#define GC0308_AWB_RGB_HIGH_LOW CCI_REG8(0x100) 286#define GC0308_AWB_Y_TO_C_DIFF2 CCI_REG8(0x102) 287#define GC0308_AWB_C_MAX CCI_REG8(0x104) 288#define GC0308_AWB_C_INTER CCI_REG8(0x105) 289#define GC0308_AWB_C_INTER2 CCI_REG8(0x106) 290#define GC0308_AWB_C_MAX_BIG CCI_REG8(0x108) 291#define GC0308_AWB_Y_HIGH CCI_REG8(0x109) 292#define GC0308_AWB_NUMBER_LIMIT CCI_REG8(0x10a) 293#define GC0308_KWIN_RATIO CCI_REG8(0x10b) 294#define GC0308_KWIN_THD CCI_REG8(0x10c) 295#define GC0308_LIGHT_GAIN_RANGE CCI_REG8(0x10d) 296#define GC0308_SMALL_WIN_WIDTH_STEP CCI_REG8(0x10e) 297#define GC0308_SMALL_WIN_HEIGHT_STEP CCI_REG8(0x10f) 298#define GC0308_AWB_YELLOW_TH CCI_REG8(0x110) 299#define GC0308_AWB_MODE CCI_REG8(0x111) 300#define GC0308_AWB_ADJUST_SPEED CCI_REG8(0x112) 301#define GC0308_AWB_EVERY_N CCI_REG8(0x113) 302#define GC0308_R_AVG_USE CCI_REG8(0x1d0) 303#define GC0308_G_AVG_USE CCI_REG8(0x1d1) 304#define GC0308_B_AVG_USE CCI_REG8(0x1d2) 305 306#define GC0308_HBLANK_MIN 0x021 307#define GC0308_HBLANK_MAX 0xfff 308#define GC0308_HBLANK_DEF 0x040 309 310#define GC0308_VBLANK_MIN 0x000 311#define GC0308_VBLANK_MAX 0xfff 312#define GC0308_VBLANK_DEF 0x020 313 314#define GC0308_PIXEL_RATE 24000000 315 316/* 317 * frame_time = (BT + height + 8) * row_time 318 * width = 640 (driver does not change window size) 319 * height = 480 (driver does not change window size) 320 * row_time = HBLANK + SAMPLE_HOLD_DELAY + width + 8 + 4 321 * 322 * When EXP_TIME > (BT + height): 323 * BT = EXP_TIME - height - 8 - VS_START_TIME + VS_END_TIME 324 * else: 325 * BT = VBLANK + VS_START_TIME + VS_END_TIME 326 * 327 * max is 30 FPS 328 * 329 * In my tests frame rate mostly depends on exposure time. Unfortuantely 330 * it's unclear how this is calculated exactly. Also since we enable AEC, 331 * the frame times vary depending on ambient light conditions. 332 */ 333#define GC0308_FRAME_RATE_MAX 30 334 335enum gc0308_exp_val { 336 GC0308_EXP_M4 = 0, 337 GC0308_EXP_M3, 338 GC0308_EXP_M2, 339 GC0308_EXP_M1, 340 GC0308_EXP_0, 341 GC0308_EXP_P1, 342 GC0308_EXP_P2, 343 GC0308_EXP_P3, 344 GC0308_EXP_P4, 345}; 346 347static const s64 gc0308_exposure_menu[] = { 348 -4, -3, -2, -1, 0, 1, 2, 3, 4 349}; 350 351struct gc0308_exposure { 352 u8 luma_offset; 353 u8 aec_target_y; 354}; 355 356#define GC0308_EXPOSURE(luma_offset_reg, aec_target_y_reg) \ 357 { .luma_offset = luma_offset_reg, .aec_target_y = aec_target_y_reg } 358 359static const struct gc0308_exposure gc0308_exposure_values[] = { 360 [GC0308_EXP_M4] = GC0308_EXPOSURE(0xc0, 0x30), 361 [GC0308_EXP_M3] = GC0308_EXPOSURE(0xd0, 0x38), 362 [GC0308_EXP_M2] = GC0308_EXPOSURE(0xe0, 0x40), 363 [GC0308_EXP_M1] = GC0308_EXPOSURE(0xf0, 0x48), 364 [GC0308_EXP_0] = GC0308_EXPOSURE(0x08, 0x50), 365 [GC0308_EXP_P1] = GC0308_EXPOSURE(0x10, 0x5c), 366 [GC0308_EXP_P2] = GC0308_EXPOSURE(0x20, 0x60), 367 [GC0308_EXP_P3] = GC0308_EXPOSURE(0x30, 0x68), 368 [GC0308_EXP_P4] = GC0308_EXPOSURE(0x40, 0x70), 369}; 370 371struct gc0308_awb_gains { 372 u8 r; 373 u8 g; 374 u8 b; 375}; 376 377#define GC0308_AWB_GAINS(red, green, blue) \ 378 { .r = red, .g = green, .b = blue } 379 380static const struct gc0308_awb_gains gc0308_awb_gains[] = { 381 [V4L2_WHITE_BALANCE_AUTO] = GC0308_AWB_GAINS(0x56, 0x40, 0x4a), 382 [V4L2_WHITE_BALANCE_CLOUDY] = GC0308_AWB_GAINS(0x8c, 0x50, 0x40), 383 [V4L2_WHITE_BALANCE_DAYLIGHT] = GC0308_AWB_GAINS(0x74, 0x52, 0x40), 384 [V4L2_WHITE_BALANCE_INCANDESCENT] = GC0308_AWB_GAINS(0x48, 0x40, 0x5c), 385 [V4L2_WHITE_BALANCE_FLUORESCENT] = GC0308_AWB_GAINS(0x40, 0x42, 0x50), 386}; 387 388struct gc0308_format { 389 u32 code; 390 u8 regval; 391}; 392 393#define GC0308_FORMAT(v4l2_code, gc0308_regval) \ 394 { .code = v4l2_code, .regval = gc0308_regval } 395 396static const struct gc0308_format gc0308_formats[] = { 397 GC0308_FORMAT(MEDIA_BUS_FMT_UYVY8_2X8, 0x00), 398 GC0308_FORMAT(MEDIA_BUS_FMT_VYUY8_2X8, 0x01), 399 GC0308_FORMAT(MEDIA_BUS_FMT_YUYV8_2X8, 0x02), 400 GC0308_FORMAT(MEDIA_BUS_FMT_YVYU8_2X8, 0x03), 401 GC0308_FORMAT(MEDIA_BUS_FMT_RGB565_2X8_BE, 0x06), 402 GC0308_FORMAT(MEDIA_BUS_FMT_RGB555_2X8_PADHI_BE, 0x07), 403 GC0308_FORMAT(MEDIA_BUS_FMT_RGB444_2X8_PADHI_BE, 0x09), 404}; 405 406struct gc0308_frame_size { 407 u8 subsample; 408 u32 width; 409 u32 height; 410}; 411 412#define GC0308_FRAME_SIZE(s, w, h) \ 413 { .subsample = s, .width = w, .height = h } 414 415static const struct gc0308_frame_size gc0308_frame_sizes[] = { 416 GC0308_FRAME_SIZE(0x11, 640, 480), 417 GC0308_FRAME_SIZE(0x22, 320, 240), 418 GC0308_FRAME_SIZE(0x44, 160, 120), 419}; 420 421struct gc0308_mode_registers { 422 u8 out_format; 423 u8 subsample; 424 u16 width; 425 u16 height; 426}; 427 428struct gc0308 { 429 struct v4l2_subdev sd; 430 struct v4l2_ctrl_handler hdl; 431 struct media_pad pad; 432 struct device *dev; 433 struct clk *clk; 434 struct regmap *regmap; 435 struct regulator *vdd; 436 struct gpio_desc *pwdn_gpio; 437 struct gpio_desc *reset_gpio; 438 unsigned int mbus_config; 439 struct gc0308_mode_registers mode; 440 struct { 441 /* mirror cluster */ 442 struct v4l2_ctrl *hflip; 443 struct v4l2_ctrl *vflip; 444 }; 445 struct { 446 /* blanking cluster */ 447 struct v4l2_ctrl *hblank; 448 struct v4l2_ctrl *vblank; 449 }; 450}; 451 452static inline struct gc0308 *to_gc0308(struct v4l2_subdev *sd) 453{ 454 return container_of(sd, struct gc0308, sd); 455} 456 457static const struct regmap_range_cfg gc0308_ranges[] = { 458 { 459 .range_min = 0x0000, 460 .range_max = 0x01ff, 461 .selector_reg = 0xfe, 462 .selector_mask = 0x01, 463 .selector_shift = 0x00, 464 .window_start = 0x00, 465 .window_len = 0x100, 466 }, 467}; 468 469static const struct regmap_config gc0308_regmap_config = { 470 .reg_bits = 8, 471 .val_bits = 8, 472 .reg_format_endian = REGMAP_ENDIAN_BIG, 473 .max_register = 0x1ff, 474 .ranges = gc0308_ranges, 475 .num_ranges = ARRAY_SIZE(gc0308_ranges), 476 .disable_locking = true, 477}; 478 479static const struct cci_reg_sequence sensor_default_regs[] = { 480 {GC0308_VB_HB, 0x00}, 481 {GC0308_HBLANK, 0x40}, 482 {GC0308_VBLANK, 0x20}, 483 {GC0308_EXP, 0x0258}, 484 {GC0308_AWB_R_GAIN, 0x56}, 485 {GC0308_AWB_G_GAIN, 0x40}, 486 {GC0308_AWB_B_GAIN, 0x4a}, 487 {GC0308_ANTI_FLICKER_STEP, 0x0078}, 488 {GC0308_EXP_LVL_1, 0x0258}, 489 {GC0308_EXP_LVL_2, 0x0258}, 490 {GC0308_EXP_LVL_3, 0x0258}, 491 {GC0308_EXP_LVL_4, 0x0ea6}, 492 {GC0308_MAX_EXP_LVL, 0x20}, 493 {GC0308_ROW_START, 0x0000}, 494 {GC0308_COL_START, 0x0000}, 495 {GC0308_WIN_HEIGHT, 488}, 496 {GC0308_WIN_WIDTH, 648}, 497 {GC0308_VS_START_TIME, 0x02}, 498 {GC0308_VS_END_TIME, 0x02}, 499 {GC0308_RSH_WIDTH, 0x22}, 500 {GC0308_TSP_WIDTH, 0x0d}, 501 {GC0308_SAMPLE_HOLD_DELAY, 0x50}, 502 {GC0308_ROW_TAIL_WIDTH, 0x0f}, 503 {GC0308_CISCTL_MODE1, 0x10}, 504 {GC0308_CISCTL_MODE2, 0x0a}, 505 {GC0308_CISCTL_MODE3, 0x05}, 506 {GC0308_CISCTL_MODE4, 0x01}, 507 {CCI_REG8(0x018), 0x44}, /* undocumented */ 508 {CCI_REG8(0x019), 0x44}, /* undocumented */ 509 {GC0308_ANALOG_MODE1, 0x2a}, 510 {GC0308_ANALOG_MODE2, 0x00}, 511 {GC0308_HRST_RSG_V18, 0x49}, 512 {GC0308_VREF_V25, 0x9a}, 513 {GC0308_ADC_R, 0x61}, 514 {GC0308_PAD_DRV, 0x01}, /* drv strength: pclk=4mA */ 515 {GC0308_BLOCK_EN1, 0x7f}, 516 {GC0308_BLOCK_EN2, 0xfa}, 517 {GC0308_AAAA_EN, 0x57}, 518 {GC0308_OUT_FORMAT, 0xa2}, /* YCbYCr */ 519 {GC0308_OUT_EN, 0x0f}, 520 {GC0308_SYNC_MODE, 0x03}, 521 {GC0308_CLK_DIV_MODE, 0x00}, 522 {GC0308_DEBUG_MODE1, 0x0a}, 523 {GC0308_DEBUG_MODE2, 0x00}, 524 {GC0308_DEBUG_MODE3, 0x01}, 525 {GC0308_BLK_MODE, 0xf7}, 526 {GC0308_BLK_LIMIT_VAL, 0x50}, 527 {GC0308_GLOBAL_OFF, 0x00}, 528 {GC0308_CURRENT_R_OFF, 0x28}, 529 {GC0308_CURRENT_G_OFF, 0x2a}, 530 {GC0308_CURRENT_B_OFF, 0x28}, 531 {GC0308_EXP_RATE_DARKC, 0x04}, 532 {GC0308_OFF_SUBMODE, 0x20}, 533 {GC0308_DARKC_SUBMODE, 0x20}, 534 {GC0308_MANUAL_G1_OFF, 0x00}, 535 {GC0308_MANUAL_R1_OFF, 0x00}, 536 {GC0308_MANUAL_B2_OFF, 0x00}, 537 {GC0308_MANUAL_G2_OFF, 0x00}, 538 {GC0308_GLOBAL_GAIN, 0x14}, 539 {GC0308_AUTO_POSTGAIN, 0x41}, 540 {GC0308_CHANNEL_GAIN_G1, 0x80}, 541 {GC0308_CHANNEL_GAIN_R, 0x80}, 542 {GC0308_CHANNEL_GAIN_B, 0x80}, 543 {GC0308_CHANNEL_GAIN_G2, 0x80}, 544 {GC0308_LSC_RED_B2, 0x20}, 545 {GC0308_LSC_GREEN_B2, 0x20}, 546 {GC0308_LSC_BLUE_B2, 0x20}, 547 {GC0308_LSC_RED_B4, 0x14}, 548 {GC0308_LSC_GREEN_B4, 0x10}, 549 {GC0308_LSC_BLUE_B4, 0x14}, 550 {GC0308_LSC_ROW_CENTER, 0x3c}, 551 {GC0308_LSC_COL_CENTER, 0x50}, 552 {GC0308_LSC_DEC_LVL1, 0x12}, 553 {GC0308_LSC_DEC_LVL2, 0x1a}, 554 {GC0308_LSC_DEC_LVL3, 0x24}, 555 {GC0308_DN_MODE_EN, 0x07}, 556 {GC0308_DN_MODE_RATIO, 0x15}, 557 {GC0308_DN_BILAT_B_BASE, 0x08}, 558 {GC0308_DN_BILAT_N_BASE, 0x03}, 559 {GC0308_DD_DARK_BRIGHT_TH, 0xe8}, 560 {GC0308_DD_FLAT_TH, 0x86}, 561 {GC0308_DD_LIMIT, 0x82}, 562 {GC0308_ASDE_GAIN_TRESH, 0x18}, 563 {GC0308_ASDE_GAIN_MODE, 0x0f}, 564 {GC0308_ASDE_DN_SLOPE, 0x00}, 565 {GC0308_ASDE_DD_BRIGHT, 0x5f}, 566 {GC0308_ASDE_DD_LIMIT, 0x8f}, 567 {GC0308_ASDE_AUTO_EE1, 0x55}, 568 {GC0308_ASDE_AUTO_EE2, 0x38}, 569 {GC0308_ASDE_AUTO_SAT_DEC_SLOPE, 0x15}, 570 {GC0308_ASDE_AUTO_SAT_LOW_LIMIT, 0x33}, 571 {GC0308_EEINTP_MODE_1, 0xdc}, 572 {GC0308_EEINTP_MODE_2, 0x00}, 573 {GC0308_DIRECTION_TH1, 0x02}, 574 {GC0308_DIRECTION_TH2, 0x3f}, 575 {GC0308_DIFF_HV_TI_TH, 0x02}, 576 {GC0308_EDGE12_EFFECT, 0x38}, 577 {GC0308_EDGE_POS_RATIO, 0x88}, 578 {GC0308_EDGE1_MINMAX, 0x81}, 579 {GC0308_EDGE2_MINMAX, 0x81}, 580 {GC0308_EDGE12_TH, 0x22}, 581 {GC0308_EDGE_MAX, 0xff}, 582 {GC0308_CC_MATRIX_C11, 0x48}, 583 {GC0308_CC_MATRIX_C12, 0x02}, 584 {GC0308_CC_MATRIX_C13, 0x07}, 585 {GC0308_CC_MATRIX_C21, 0xe0}, 586 {GC0308_CC_MATRIX_C22, 0x40}, 587 {GC0308_CC_MATRIX_C23, 0xf0}, 588 {GC0308_SATURATION_CB, 0x40}, 589 {GC0308_SATURATION_CR, 0x40}, 590 {GC0308_LUMA_CONTRAST, 0x40}, 591 {GC0308_SKIN_CB_CENTER, 0xe0}, 592 {GC0308_EDGE_DEC_SA, 0x38}, 593 {GC0308_AUTO_GRAY_MODE, 0x36}, 594 {GC0308_AEC_MODE1, 0xcb}, 595 {GC0308_AEC_MODE2, 0x10}, 596 {GC0308_AEC_MODE3, 0x90}, 597 {GC0308_AEC_TARGET_Y, 0x48}, 598 {GC0308_AEC_HIGH_LOW_RANGE, 0xf2}, 599 {GC0308_AEC_IGNORE, 0x16}, 600 {GC0308_AEC_SLOW_MARGIN, 0x92}, 601 {GC0308_AEC_FAST_MARGIN, 0xa5}, 602 {GC0308_AEC_I_FRAMES, 0x23}, 603 {GC0308_AEC_R_OFFSET, 0x00}, 604 {GC0308_AEC_GB_OFFSET, 0x00}, 605 {GC0308_AEC_I_STOP_L_MARGIN, 0x09}, 606 {GC0308_EXP_MIN_L, 0x04}, 607 {GC0308_MAX_POST_DF_GAIN, 0xa0}, 608 {GC0308_MAX_PRE_DG_GAIN, 0x40}, 609 {GC0308_ABB_MODE, 0x03}, 610 {GC0308_GAMMA_OUT0, 0x10}, 611 {GC0308_GAMMA_OUT1, 0x20}, 612 {GC0308_GAMMA_OUT2, 0x38}, 613 {GC0308_GAMMA_OUT3, 0x4e}, 614 {GC0308_GAMMA_OUT4, 0x63}, 615 {GC0308_GAMMA_OUT5, 0x76}, 616 {GC0308_GAMMA_OUT6, 0x87}, 617 {GC0308_GAMMA_OUT7, 0xa2}, 618 {GC0308_GAMMA_OUT8, 0xb8}, 619 {GC0308_GAMMA_OUT9, 0xca}, 620 {GC0308_GAMMA_OUT10, 0xd8}, 621 {GC0308_GAMMA_OUT11, 0xe3}, 622 {GC0308_GAMMA_OUT12, 0xeb}, 623 {GC0308_GAMMA_OUT13, 0xf0}, 624 {GC0308_GAMMA_OUT14, 0xf8}, 625 {GC0308_GAMMA_OUT15, 0xfd}, 626 {GC0308_GAMMA_OUT16, 0xff}, 627 {GC0308_Y_GAMMA_OUT0, 0x00}, 628 {GC0308_Y_GAMMA_OUT1, 0x10}, 629 {GC0308_Y_GAMMA_OUT2, 0x1c}, 630 {GC0308_Y_GAMMA_OUT3, 0x30}, 631 {GC0308_Y_GAMMA_OUT4, 0x43}, 632 {GC0308_Y_GAMMA_OUT5, 0x54}, 633 {GC0308_Y_GAMMA_OUT6, 0x65}, 634 {GC0308_Y_GAMMA_OUT7, 0x75}, 635 {GC0308_Y_GAMMA_OUT8, 0x93}, 636 {GC0308_Y_GAMMA_OUT9, 0xb0}, 637 {GC0308_Y_GAMMA_OUT10, 0xcb}, 638 {GC0308_Y_GAMMA_OUT11, 0xe6}, 639 {GC0308_Y_GAMMA_OUT12, 0xff}, 640 {GC0308_ABS_RANGE_COMP, 0x02}, 641 {GC0308_ABS_STOP_MARGIN, 0x01}, 642 {GC0308_Y_S_COMP, 0x02}, 643 {GC0308_Y_STRETCH_LIMIT, 0x30}, 644 {GC0308_BIG_WIN_X0, 0x12}, 645 {GC0308_BIG_WIN_Y0, 0x0a}, 646 {GC0308_BIG_WIN_X1, 0x9f}, 647 {GC0308_BIG_WIN_Y1, 0x78}, 648 {GC0308_AWB_RGB_HIGH_LOW, 0xf5}, 649 {GC0308_AWB_Y_TO_C_DIFF2, 0x20}, 650 {GC0308_AWB_C_MAX, 0x10}, 651 {GC0308_AWB_C_INTER, 0x08}, 652 {GC0308_AWB_C_INTER2, 0x20}, 653 {GC0308_AWB_C_MAX_BIG, 0x0a}, 654 {GC0308_AWB_NUMBER_LIMIT, 0xa0}, 655 {GC0308_KWIN_RATIO, 0x60}, 656 {GC0308_KWIN_THD, 0x08}, 657 {GC0308_SMALL_WIN_WIDTH_STEP, 0x44}, 658 {GC0308_SMALL_WIN_HEIGHT_STEP, 0x32}, 659 {GC0308_AWB_YELLOW_TH, 0x41}, 660 {GC0308_AWB_MODE, 0x37}, 661 {GC0308_AWB_ADJUST_SPEED, 0x22}, 662 {GC0308_AWB_EVERY_N, 0x19}, 663 {CCI_REG8(0x114), 0x44}, /* AWB set1 */ 664 {CCI_REG8(0x115), 0x44}, /* AWB set1 */ 665 {CCI_REG8(0x116), 0xc2}, /* AWB set1 */ 666 {CCI_REG8(0x117), 0xa8}, /* AWB set1 */ 667 {CCI_REG8(0x118), 0x18}, /* AWB set1 */ 668 {CCI_REG8(0x119), 0x50}, /* AWB set1 */ 669 {CCI_REG8(0x11a), 0xd8}, /* AWB set1 */ 670 {CCI_REG8(0x11b), 0xf5}, /* AWB set1 */ 671 {CCI_REG8(0x170), 0x40}, /* AWB set2 */ 672 {CCI_REG8(0x171), 0x58}, /* AWB set2 */ 673 {CCI_REG8(0x172), 0x30}, /* AWB set2 */ 674 {CCI_REG8(0x173), 0x48}, /* AWB set2 */ 675 {CCI_REG8(0x174), 0x20}, /* AWB set2 */ 676 {CCI_REG8(0x175), 0x60}, /* AWB set2 */ 677 {CCI_REG8(0x177), 0x20}, /* AWB set2 */ 678 {CCI_REG8(0x178), 0x32}, /* AWB set2 */ 679 {CCI_REG8(0x130), 0x03}, /* undocumented */ 680 {CCI_REG8(0x131), 0x40}, /* undocumented */ 681 {CCI_REG8(0x132), 0x10}, /* undocumented */ 682 {CCI_REG8(0x133), 0xe0}, /* undocumented */ 683 {CCI_REG8(0x134), 0xe0}, /* undocumented */ 684 {CCI_REG8(0x135), 0x00}, /* undocumented */ 685 {CCI_REG8(0x136), 0x80}, /* undocumented */ 686 {CCI_REG8(0x137), 0x00}, /* undocumented */ 687 {CCI_REG8(0x138), 0x04}, /* undocumented */ 688 {CCI_REG8(0x139), 0x09}, /* undocumented */ 689 {CCI_REG8(0x13a), 0x12}, /* undocumented */ 690 {CCI_REG8(0x13b), 0x1c}, /* undocumented */ 691 {CCI_REG8(0x13c), 0x28}, /* undocumented */ 692 {CCI_REG8(0x13d), 0x31}, /* undocumented */ 693 {CCI_REG8(0x13e), 0x44}, /* undocumented */ 694 {CCI_REG8(0x13f), 0x57}, /* undocumented */ 695 {CCI_REG8(0x140), 0x6c}, /* undocumented */ 696 {CCI_REG8(0x141), 0x81}, /* undocumented */ 697 {CCI_REG8(0x142), 0x94}, /* undocumented */ 698 {CCI_REG8(0x143), 0xa7}, /* undocumented */ 699 {CCI_REG8(0x144), 0xb8}, /* undocumented */ 700 {CCI_REG8(0x145), 0xd6}, /* undocumented */ 701 {CCI_REG8(0x146), 0xee}, /* undocumented */ 702 {CCI_REG8(0x147), 0x0d}, /* undocumented */ 703 {CCI_REG8(0x162), 0xf7}, /* undocumented */ 704 {CCI_REG8(0x163), 0x68}, /* undocumented */ 705 {CCI_REG8(0x164), 0xd3}, /* undocumented */ 706 {CCI_REG8(0x165), 0xd3}, /* undocumented */ 707 {CCI_REG8(0x166), 0x60}, /* undocumented */ 708}; 709 710struct gc0308_colormode { 711 u8 special_effect; 712 u8 dbg_mode1; 713 u8 block_en1; 714 u8 aec_mode3; 715 u8 eeintp_mode_2; 716 u8 edge12_effect; 717 u8 luma_contrast; 718 u8 contrast_center; 719 u8 fixed_cb; 720 u8 fixed_cr; 721}; 722 723#define GC0308_COLOR_FX(reg_special_effect, reg_dbg_mode1, reg_block_en1, \ 724 reg_aec_mode3, reg_eeintp_mode_2, reg_edge12_effect, \ 725 reg_luma_contrast, reg_contrast_center, \ 726 reg_fixed_cb, reg_fixed_cr) \ 727 { \ 728 .special_effect = reg_special_effect, \ 729 .dbg_mode1 = reg_dbg_mode1, \ 730 .block_en1 = reg_block_en1, \ 731 .aec_mode3 = reg_aec_mode3, \ 732 .eeintp_mode_2 = reg_eeintp_mode_2, \ 733 .edge12_effect = reg_edge12_effect, \ 734 .luma_contrast = reg_luma_contrast, \ 735 .contrast_center = reg_contrast_center, \ 736 .fixed_cb = reg_fixed_cb, \ 737 .fixed_cr = reg_fixed_cr, \ 738 } 739 740static const struct gc0308_colormode gc0308_colormodes[] = { 741 [V4L2_COLORFX_NONE] = 742 GC0308_COLOR_FX(0x00, 0x0a, 0xff, 0x90, 0x00, 743 0x54, 0x3c, 0x80, 0x00, 0x00), 744 [V4L2_COLORFX_BW] = 745 GC0308_COLOR_FX(0x02, 0x0a, 0xff, 0x90, 0x00, 746 0x54, 0x40, 0x80, 0x00, 0x00), 747 [V4L2_COLORFX_SEPIA] = 748 GC0308_COLOR_FX(0x02, 0x0a, 0xff, 0x90, 0x00, 749 0x38, 0x40, 0x80, 0xd0, 0x28), 750 [V4L2_COLORFX_NEGATIVE] = 751 GC0308_COLOR_FX(0x01, 0x0a, 0xff, 0x90, 0x00, 752 0x38, 0x40, 0x80, 0x00, 0x00), 753 [V4L2_COLORFX_EMBOSS] = 754 GC0308_COLOR_FX(0x02, 0x0a, 0xbf, 0x10, 0x01, 755 0x38, 0x40, 0x80, 0x00, 0x00), 756 [V4L2_COLORFX_SKETCH] = 757 GC0308_COLOR_FX(0x02, 0x0a, 0xff, 0x10, 0x80, 758 0x38, 0x80, 0x90, 0x00, 0x00), 759 [V4L2_COLORFX_SKY_BLUE] = 760 GC0308_COLOR_FX(0x02, 0x0a, 0xff, 0x90, 0x00, 761 0x38, 0x40, 0x80, 0x50, 0xe0), 762 [V4L2_COLORFX_GRASS_GREEN] = 763 GC0308_COLOR_FX(0x02, 0x0a, 0xff, 0x90, 0x01, 764 0x38, 0x40, 0x80, 0xc0, 0xc0), 765 [V4L2_COLORFX_SKIN_WHITEN] = 766 GC0308_COLOR_FX(0x02, 0x0a, 0xbf, 0x10, 0x01, 767 0x38, 0x60, 0x40, 0x00, 0x00), 768}; 769 770static int gc0308_power_on(struct device *dev) 771{ 772 struct gc0308 *gc0308 = dev_get_drvdata(dev); 773 int ret; 774 775 ret = regulator_enable(gc0308->vdd); 776 if (ret) 777 return ret; 778 779 ret = clk_prepare_enable(gc0308->clk); 780 if (ret) 781 goto clk_fail; 782 783 gpiod_set_value_cansleep(gc0308->pwdn_gpio, 0); 784 usleep_range(10000, 20000); 785 786 gpiod_set_value_cansleep(gc0308->reset_gpio, 1); 787 usleep_range(10000, 20000); 788 gpiod_set_value_cansleep(gc0308->reset_gpio, 0); 789 msleep(30); 790 791 return 0; 792 793clk_fail: 794 regulator_disable(gc0308->vdd); 795 return ret; 796} 797 798static int gc0308_power_off(struct device *dev) 799{ 800 struct gc0308 *gc0308 = dev_get_drvdata(dev); 801 802 gpiod_set_value_cansleep(gc0308->pwdn_gpio, 1); 803 clk_disable_unprepare(gc0308->clk); 804 regulator_disable(gc0308->vdd); 805 806 return 0; 807} 808 809#ifdef CONFIG_VIDEO_ADV_DEBUG 810static int gc0308_g_register(struct v4l2_subdev *sd, 811 struct v4l2_dbg_register *reg) 812{ 813 struct gc0308 *gc0308 = to_gc0308(sd); 814 815 return cci_read(gc0308->regmap, CCI_REG8(reg->reg), ®->val, NULL); 816} 817 818static int gc0308_s_register(struct v4l2_subdev *sd, 819 const struct v4l2_dbg_register *reg) 820{ 821 struct gc0308 *gc0308 = to_gc0308(sd); 822 823 return cci_write(gc0308->regmap, CCI_REG8(reg->reg), reg->val, NULL); 824} 825#endif 826 827static int gc0308_set_exposure(struct gc0308 *gc0308, enum gc0308_exp_val exp) 828{ 829 const struct gc0308_exposure *regs = &gc0308_exposure_values[exp]; 830 struct cci_reg_sequence exposure_reg_seq[] = { 831 {GC0308_LUMA_OFFSET, regs->luma_offset}, 832 {GC0308_AEC_TARGET_Y, regs->aec_target_y}, 833 }; 834 835 return cci_multi_reg_write(gc0308->regmap, exposure_reg_seq, 836 ARRAY_SIZE(exposure_reg_seq), NULL); 837} 838 839static int gc0308_set_awb_mode(struct gc0308 *gc0308, 840 enum v4l2_auto_n_preset_white_balance val) 841{ 842 const struct gc0308_awb_gains *regs = &gc0308_awb_gains[val]; 843 struct cci_reg_sequence awb_reg_seq[] = { 844 {GC0308_AWB_R_GAIN, regs->r}, 845 {GC0308_AWB_G_GAIN, regs->g}, 846 {GC0308_AWB_B_GAIN, regs->b}, 847 }; 848 int ret; 849 850 ret = cci_update_bits(gc0308->regmap, GC0308_AAAA_EN, 851 BIT(1), val == V4L2_WHITE_BALANCE_AUTO, NULL); 852 ret = cci_multi_reg_write(gc0308->regmap, awb_reg_seq, 853 ARRAY_SIZE(awb_reg_seq), &ret); 854 855 return ret; 856} 857 858static int gc0308_set_colormode(struct gc0308 *gc0308, enum v4l2_colorfx mode) 859{ 860 const struct gc0308_colormode *regs = &gc0308_colormodes[mode]; 861 struct cci_reg_sequence colormode_reg_seq[] = { 862 {GC0308_SPECIAL_EFFECT, regs->special_effect}, 863 {GC0308_DEBUG_MODE1, regs->dbg_mode1}, 864 {GC0308_BLOCK_EN1, regs->block_en1}, 865 {GC0308_AEC_MODE3, regs->aec_mode3}, 866 {GC0308_EEINTP_MODE_2, regs->eeintp_mode_2}, 867 {GC0308_EDGE12_EFFECT, regs->edge12_effect}, 868 {GC0308_LUMA_CONTRAST, regs->luma_contrast}, 869 {GC0308_CONTRAST_CENTER, regs->contrast_center}, 870 {GC0308_FIXED_CB, regs->fixed_cb}, 871 {GC0308_FIXED_CR, regs->fixed_cr}, 872 }; 873 874 return cci_multi_reg_write(gc0308->regmap, colormode_reg_seq, 875 ARRAY_SIZE(colormode_reg_seq), NULL); 876} 877 878static int gc0308_set_power_line_freq(struct gc0308 *gc0308, int frequency) 879{ 880 static const struct cci_reg_sequence pwr_line_50hz[] = { 881 {GC0308_ANTI_FLICKER_STEP, 0x0078}, 882 {GC0308_EXP_LVL_1, 0x0258}, 883 {GC0308_EXP_LVL_2, 0x0348}, 884 {GC0308_EXP_LVL_3, 0x04b0}, 885 {GC0308_EXP_LVL_4, 0x05a0}, 886 }; 887 static const struct cci_reg_sequence pwr_line_60hz[] = { 888 {GC0308_ANTI_FLICKER_STEP, 0x0064}, 889 {GC0308_EXP_LVL_1, 0x0258}, 890 {GC0308_EXP_LVL_2, 0x0384}, 891 {GC0308_EXP_LVL_3, 0x04b0}, 892 {GC0308_EXP_LVL_4, 0x05dc}, 893 }; 894 895 switch (frequency) { 896 case V4L2_CID_POWER_LINE_FREQUENCY_60HZ: 897 return cci_multi_reg_write(gc0308->regmap, pwr_line_60hz, 898 ARRAY_SIZE(pwr_line_60hz), NULL); 899 case V4L2_CID_POWER_LINE_FREQUENCY_50HZ: 900 return cci_multi_reg_write(gc0308->regmap, pwr_line_50hz, 901 ARRAY_SIZE(pwr_line_50hz), NULL); 902 } 903 904 return -EINVAL; 905} 906 907static int gc0308_update_mirror(struct gc0308 *gc0308) 908{ 909 u8 regval = 0x00; 910 911 if (gc0308->vflip->val) 912 regval |= BIT(1); 913 914 if (gc0308->hflip->val) 915 regval |= BIT(0); 916 917 return cci_update_bits(gc0308->regmap, GC0308_CISCTL_MODE1, 918 GENMASK(1, 0), regval, NULL); 919} 920 921static int gc0308_update_blanking(struct gc0308 *gc0308) 922{ 923 u16 vblank = gc0308->vblank->val; 924 u16 hblank = gc0308->hblank->val; 925 u8 vbhb = ((vblank >> 4) & 0xf0) | ((hblank >> 8) & 0x0f); 926 int ret = 0; 927 928 cci_write(gc0308->regmap, GC0308_VB_HB, vbhb, &ret); 929 cci_write(gc0308->regmap, GC0308_HBLANK, hblank & 0xff, &ret); 930 cci_write(gc0308->regmap, GC0308_VBLANK, vblank & 0xff, &ret); 931 932 return ret; 933} 934 935static int _gc0308_s_ctrl(struct v4l2_ctrl *ctrl) 936{ 937 struct gc0308 *gc0308 = container_of(ctrl->handler, struct gc0308, hdl); 938 u8 flipval = ctrl->val ? 0xff : 0x00; 939 940 switch (ctrl->id) { 941 case V4L2_CID_HBLANK: 942 case V4L2_CID_VBLANK: 943 return gc0308_update_blanking(gc0308); 944 case V4L2_CID_VFLIP: 945 case V4L2_CID_HFLIP: 946 return gc0308_update_mirror(gc0308); 947 case V4L2_CID_AUTO_WHITE_BALANCE: 948 return cci_update_bits(gc0308->regmap, GC0308_AAAA_EN, 949 BIT(1), flipval, NULL); 950 case V4L2_CID_AUTO_N_PRESET_WHITE_BALANCE: 951 return gc0308_set_awb_mode(gc0308, ctrl->val); 952 case V4L2_CID_POWER_LINE_FREQUENCY: 953 return gc0308_set_power_line_freq(gc0308, ctrl->val); 954 case V4L2_CID_COLORFX: 955 return gc0308_set_colormode(gc0308, ctrl->val); 956 case V4L2_CID_TEST_PATTERN: 957 return cci_update_bits(gc0308->regmap, GC0308_DEBUG_MODE2, 958 GENMASK(1, 0), ctrl->val, NULL); 959 case V4L2_CID_AUTO_EXPOSURE_BIAS: 960 return gc0308_set_exposure(gc0308, ctrl->val); 961 } 962 963 return -EINVAL; 964} 965 966static int gc0308_s_ctrl(struct v4l2_ctrl *ctrl) 967{ 968 struct gc0308 *gc0308 = container_of(ctrl->handler, struct gc0308, hdl); 969 int ret; 970 971 if (!pm_runtime_get_if_in_use(gc0308->dev)) 972 return 0; 973 974 ret = _gc0308_s_ctrl(ctrl); 975 if (ret) 976 dev_err(gc0308->dev, "failed to set control: %d\n", ret); 977 978 pm_runtime_mark_last_busy(gc0308->dev); 979 pm_runtime_put_autosuspend(gc0308->dev); 980 981 return ret; 982} 983 984static const struct v4l2_ctrl_ops gc0308_ctrl_ops = { 985 .s_ctrl = gc0308_s_ctrl, 986}; 987 988static const struct v4l2_subdev_core_ops gc0308_core_ops = { 989 .log_status = v4l2_ctrl_subdev_log_status, 990 .subscribe_event = v4l2_ctrl_subdev_subscribe_event, 991 .unsubscribe_event = v4l2_event_subdev_unsubscribe, 992#ifdef CONFIG_VIDEO_ADV_DEBUG 993 .g_register = gc0308_g_register, 994 .s_register = gc0308_s_register, 995#endif 996}; 997 998static int gc0308_enum_mbus_code(struct v4l2_subdev *sd, 999 struct v4l2_subdev_state *sd_state, 1000 struct v4l2_subdev_mbus_code_enum *code) 1001{ 1002 if (code->index >= ARRAY_SIZE(gc0308_formats)) 1003 return -EINVAL; 1004 1005 code->code = gc0308_formats[code->index].code; 1006 1007 return 0; 1008} 1009 1010static int gc0308_get_format_idx(u32 code) 1011{ 1012 int i; 1013 1014 for (i = 0; i < ARRAY_SIZE(gc0308_formats); i++) { 1015 if (gc0308_formats[i].code == code) 1016 return i; 1017 } 1018 1019 return -1; 1020} 1021 1022static int gc0308_enum_frame_size(struct v4l2_subdev *subdev, 1023 struct v4l2_subdev_state *sd_state, 1024 struct v4l2_subdev_frame_size_enum *fse) 1025{ 1026 if (fse->index >= ARRAY_SIZE(gc0308_frame_sizes)) 1027 return -EINVAL; 1028 1029 if (gc0308_get_format_idx(fse->code) < 0) 1030 return -EINVAL; 1031 1032 fse->min_width = gc0308_frame_sizes[fse->index].width; 1033 fse->max_width = gc0308_frame_sizes[fse->index].width; 1034 fse->min_height = gc0308_frame_sizes[fse->index].height; 1035 fse->max_height = gc0308_frame_sizes[fse->index].height; 1036 1037 return 0; 1038} 1039 1040static void gc0308_update_pad_format(const struct gc0308_frame_size *mode, 1041 struct v4l2_mbus_framefmt *fmt, u32 code) 1042{ 1043 fmt->width = mode->width; 1044 fmt->height = mode->height; 1045 fmt->code = code; 1046 fmt->field = V4L2_FIELD_NONE; 1047 fmt->colorspace = V4L2_COLORSPACE_SRGB; 1048} 1049 1050static int gc0308_set_format(struct v4l2_subdev *sd, 1051 struct v4l2_subdev_state *sd_state, 1052 struct v4l2_subdev_format *fmt) 1053{ 1054 struct gc0308 *gc0308 = to_gc0308(sd); 1055 const struct gc0308_frame_size *mode; 1056 int i = gc0308_get_format_idx(fmt->format.code); 1057 1058 if (i < 0) 1059 i = 0; 1060 1061 mode = v4l2_find_nearest_size(gc0308_frame_sizes, 1062 ARRAY_SIZE(gc0308_frame_sizes), width, 1063 height, fmt->format.width, 1064 fmt->format.height); 1065 1066 gc0308_update_pad_format(mode, &fmt->format, gc0308_formats[i].code); 1067 *v4l2_subdev_state_get_format(sd_state, 0) = fmt->format; 1068 1069 if (fmt->which == V4L2_SUBDEV_FORMAT_TRY) 1070 return 0; 1071 1072 gc0308->mode.out_format = gc0308_formats[i].regval; 1073 gc0308->mode.subsample = mode->subsample; 1074 gc0308->mode.width = mode->width; 1075 gc0308->mode.height = mode->height; 1076 1077 return 0; 1078} 1079 1080static int gc0308_init_state(struct v4l2_subdev *sd, 1081 struct v4l2_subdev_state *sd_state) 1082{ 1083 struct v4l2_mbus_framefmt *format = 1084 v4l2_subdev_state_get_format(sd_state, 0); 1085 1086 format->width = 640; 1087 format->height = 480; 1088 format->code = gc0308_formats[0].code; 1089 format->colorspace = V4L2_COLORSPACE_SRGB; 1090 format->field = V4L2_FIELD_NONE; 1091 format->ycbcr_enc = V4L2_YCBCR_ENC_DEFAULT; 1092 format->quantization = V4L2_QUANTIZATION_DEFAULT; 1093 format->xfer_func = V4L2_XFER_FUNC_DEFAULT; 1094 1095 return 0; 1096} 1097 1098static const struct v4l2_subdev_pad_ops gc0308_pad_ops = { 1099 .enum_mbus_code = gc0308_enum_mbus_code, 1100 .enum_frame_size = gc0308_enum_frame_size, 1101 .get_fmt = v4l2_subdev_get_fmt, 1102 .set_fmt = gc0308_set_format, 1103}; 1104 1105static int gc0308_set_resolution(struct gc0308 *gc0308, int *ret) 1106{ 1107 struct cci_reg_sequence resolution_regs[] = { 1108 {GC0308_SUBSAMPLE, gc0308->mode.subsample}, 1109 {GC0308_SUBMODE, 0x03}, 1110 {GC0308_SUB_ROW_N1, 0x00}, 1111 {GC0308_SUB_ROW_N2, 0x00}, 1112 {GC0308_SUB_COL_N1, 0x00}, 1113 {GC0308_SUB_COL_N2, 0x00}, 1114 {GC0308_CROP_WIN_MODE, 0x80}, 1115 {GC0308_CROP_WIN_Y1, 0x00}, 1116 {GC0308_CROP_WIN_X1, 0x00}, 1117 {GC0308_CROP_WIN_HEIGHT, gc0308->mode.height}, 1118 {GC0308_CROP_WIN_WIDTH, gc0308->mode.width}, 1119 }; 1120 1121 return cci_multi_reg_write(gc0308->regmap, resolution_regs, 1122 ARRAY_SIZE(resolution_regs), ret); 1123} 1124 1125static int gc0308_start_stream(struct gc0308 *gc0308) 1126{ 1127 int ret, sync_mode; 1128 1129 ret = pm_runtime_resume_and_get(gc0308->dev); 1130 if (ret < 0) 1131 return ret; 1132 1133 cci_multi_reg_write(gc0308->regmap, sensor_default_regs, 1134 ARRAY_SIZE(sensor_default_regs), &ret); 1135 cci_update_bits(gc0308->regmap, GC0308_OUT_FORMAT, 1136 GENMASK(4, 0), gc0308->mode.out_format, &ret); 1137 gc0308_set_resolution(gc0308, &ret); 1138 1139 if (ret) { 1140 dev_err(gc0308->dev, "failed to update registers: %d\n", ret); 1141 goto disable_pm; 1142 } 1143 1144 ret = __v4l2_ctrl_handler_setup(&gc0308->hdl); 1145 if (ret) { 1146 dev_err(gc0308->dev, "failed to setup controls\n"); 1147 goto disable_pm; 1148 } 1149 1150 /* HSYNC/VSYNC polarity */ 1151 sync_mode = 0x3; 1152 if (gc0308->mbus_config & V4L2_MBUS_VSYNC_ACTIVE_LOW) 1153 sync_mode &= ~BIT(0); 1154 if (gc0308->mbus_config & V4L2_MBUS_HSYNC_ACTIVE_LOW) 1155 sync_mode &= ~BIT(1); 1156 ret = cci_write(gc0308->regmap, GC0308_SYNC_MODE, sync_mode, NULL); 1157 if (ret) 1158 goto disable_pm; 1159 1160 return 0; 1161 1162disable_pm: 1163 pm_runtime_mark_last_busy(gc0308->dev); 1164 pm_runtime_put_autosuspend(gc0308->dev); 1165 return ret; 1166} 1167 1168static int gc0308_stop_stream(struct gc0308 *gc0308) 1169{ 1170 pm_runtime_mark_last_busy(gc0308->dev); 1171 pm_runtime_put_autosuspend(gc0308->dev); 1172 return 0; 1173} 1174 1175static int gc0308_s_stream(struct v4l2_subdev *sd, int enable) 1176{ 1177 struct gc0308 *gc0308 = to_gc0308(sd); 1178 struct v4l2_subdev_state *sd_state; 1179 int ret; 1180 1181 sd_state = v4l2_subdev_lock_and_get_active_state(sd); 1182 1183 if (enable) 1184 ret = gc0308_start_stream(gc0308); 1185 else 1186 ret = gc0308_stop_stream(gc0308); 1187 1188 v4l2_subdev_unlock_state(sd_state); 1189 return ret; 1190} 1191 1192static const struct v4l2_subdev_video_ops gc0308_video_ops = { 1193 .s_stream = gc0308_s_stream, 1194}; 1195 1196static const struct v4l2_subdev_ops gc0308_subdev_ops = { 1197 .core = &gc0308_core_ops, 1198 .pad = &gc0308_pad_ops, 1199 .video = &gc0308_video_ops, 1200}; 1201 1202static const struct v4l2_subdev_internal_ops gc0308_internal_ops = { 1203 .init_state = gc0308_init_state, 1204}; 1205 1206static int gc0308_bus_config(struct gc0308 *gc0308) 1207{ 1208 struct device *dev = gc0308->dev; 1209 struct v4l2_fwnode_endpoint bus_cfg = { 1210 .bus_type = V4L2_MBUS_PARALLEL 1211 }; 1212 struct fwnode_handle *ep; 1213 int ret; 1214 1215 ep = fwnode_graph_get_endpoint_by_id(dev_fwnode(dev), 0, 0, 0); 1216 if (!ep) 1217 return -EINVAL; 1218 1219 ret = v4l2_fwnode_endpoint_parse(ep, &bus_cfg); 1220 fwnode_handle_put(ep); 1221 if (ret) 1222 return ret; 1223 1224 gc0308->mbus_config = bus_cfg.bus.parallel.flags; 1225 1226 return 0; 1227} 1228 1229static const char * const gc0308_test_pattern_menu[] = { 1230 "Disabled", 1231 "Test Image 1", 1232 "Test Image 2", 1233}; 1234 1235static int gc0308_init_controls(struct gc0308 *gc0308) 1236{ 1237 int ret; 1238 1239 v4l2_ctrl_handler_init(&gc0308->hdl, 11); 1240 gc0308->hblank = v4l2_ctrl_new_std(&gc0308->hdl, &gc0308_ctrl_ops, 1241 V4L2_CID_HBLANK, GC0308_HBLANK_MIN, 1242 GC0308_HBLANK_MAX, 1, 1243 GC0308_HBLANK_DEF); 1244 gc0308->vblank = v4l2_ctrl_new_std(&gc0308->hdl, &gc0308_ctrl_ops, 1245 V4L2_CID_VBLANK, GC0308_VBLANK_MIN, 1246 GC0308_VBLANK_MAX, 1, 1247 GC0308_VBLANK_DEF); 1248 gc0308->hflip = v4l2_ctrl_new_std(&gc0308->hdl, &gc0308_ctrl_ops, 1249 V4L2_CID_HFLIP, 0, 1, 1, 0); 1250 gc0308->vflip = v4l2_ctrl_new_std(&gc0308->hdl, &gc0308_ctrl_ops, 1251 V4L2_CID_VFLIP, 0, 1, 1, 0); 1252 v4l2_ctrl_new_std(&gc0308->hdl, &gc0308_ctrl_ops, V4L2_CID_PIXEL_RATE, 1253 GC0308_PIXEL_RATE, GC0308_PIXEL_RATE, 1, 1254 GC0308_PIXEL_RATE); 1255 v4l2_ctrl_new_std(&gc0308->hdl, &gc0308_ctrl_ops, 1256 V4L2_CID_AUTO_WHITE_BALANCE, 0, 1, 1, 1); 1257 v4l2_ctrl_new_std_menu_items(&gc0308->hdl, &gc0308_ctrl_ops, 1258 V4L2_CID_TEST_PATTERN, 1259 ARRAY_SIZE(gc0308_test_pattern_menu) - 1, 1260 0, 0, gc0308_test_pattern_menu); 1261 v4l2_ctrl_new_std_menu(&gc0308->hdl, &gc0308_ctrl_ops, 1262 V4L2_CID_AUTO_N_PRESET_WHITE_BALANCE, 1263 8, ~0x14e, V4L2_WHITE_BALANCE_AUTO); 1264 v4l2_ctrl_new_std_menu(&gc0308->hdl, &gc0308_ctrl_ops, 1265 V4L2_CID_COLORFX, 8, 0, V4L2_COLORFX_NONE); 1266 v4l2_ctrl_new_std_menu(&gc0308->hdl, &gc0308_ctrl_ops, 1267 V4L2_CID_POWER_LINE_FREQUENCY, 1268 V4L2_CID_POWER_LINE_FREQUENCY_60HZ, 1269 ~0x6, V4L2_CID_POWER_LINE_FREQUENCY_50HZ); 1270 v4l2_ctrl_new_int_menu(&gc0308->hdl, &gc0308_ctrl_ops, 1271 V4L2_CID_AUTO_EXPOSURE_BIAS, 1272 ARRAY_SIZE(gc0308_exposure_menu) - 1, 1273 ARRAY_SIZE(gc0308_exposure_menu) / 2, 1274 gc0308_exposure_menu); 1275 1276 gc0308->sd.ctrl_handler = &gc0308->hdl; 1277 if (gc0308->hdl.error) { 1278 ret = gc0308->hdl.error; 1279 v4l2_ctrl_handler_free(&gc0308->hdl); 1280 return ret; 1281 } 1282 1283 v4l2_ctrl_cluster(2, &gc0308->hflip); 1284 v4l2_ctrl_cluster(2, &gc0308->hblank); 1285 1286 return 0; 1287} 1288 1289static int gc0308_probe(struct i2c_client *client) 1290{ 1291 struct device *dev = &client->dev; 1292 struct gc0308 *gc0308; 1293 unsigned long clkrate; 1294 u64 regval; 1295 int ret; 1296 1297 gc0308 = devm_kzalloc(dev, sizeof(*gc0308), GFP_KERNEL); 1298 if (!gc0308) 1299 return -ENOMEM; 1300 1301 gc0308->dev = dev; 1302 dev_set_drvdata(dev, gc0308); 1303 1304 ret = gc0308_bus_config(gc0308); 1305 if (ret) 1306 return dev_err_probe(dev, ret, "failed to get bus config\n"); 1307 1308 gc0308->clk = devm_clk_get_optional(dev, NULL); 1309 if (IS_ERR(gc0308->clk)) 1310 return dev_err_probe(dev, PTR_ERR(gc0308->clk), 1311 "could not get clk\n"); 1312 1313 gc0308->vdd = devm_regulator_get(dev, "vdd28"); 1314 if (IS_ERR(gc0308->vdd)) 1315 return dev_err_probe(dev, PTR_ERR(gc0308->vdd), 1316 "failed to get vdd28 regulator\n"); 1317 1318 gc0308->pwdn_gpio = devm_gpiod_get(dev, "powerdown", GPIOD_OUT_LOW); 1319 if (IS_ERR(gc0308->pwdn_gpio)) 1320 return dev_err_probe(dev, PTR_ERR(gc0308->pwdn_gpio), 1321 "failed to get powerdown gpio\n"); 1322 1323 gc0308->reset_gpio = devm_gpiod_get(dev, "reset", GPIOD_OUT_LOW); 1324 if (IS_ERR(gc0308->reset_gpio)) 1325 return dev_err_probe(dev, PTR_ERR(gc0308->reset_gpio), 1326 "failed to get reset gpio\n"); 1327 1328 /* 1329 * This is not using devm_cci_regmap_init_i2c(), because the driver 1330 * makes use of regmap's pagination feature. The chosen settings are 1331 * compatible with the CCI helpers. 1332 */ 1333 gc0308->regmap = devm_regmap_init_i2c(client, &gc0308_regmap_config); 1334 if (IS_ERR(gc0308->regmap)) 1335 return dev_err_probe(dev, PTR_ERR(gc0308->regmap), 1336 "failed to init regmap\n"); 1337 1338 v4l2_i2c_subdev_init(&gc0308->sd, client, &gc0308_subdev_ops); 1339 gc0308->sd.internal_ops = &gc0308_internal_ops; 1340 gc0308->sd.flags |= V4L2_SUBDEV_FL_HAS_DEVNODE; 1341 gc0308->sd.flags |= V4L2_SUBDEV_FL_HAS_EVENTS; 1342 1343 ret = gc0308_init_controls(gc0308); 1344 if (ret) 1345 return dev_err_probe(dev, ret, "failed to init controls\n"); 1346 1347 gc0308->sd.state_lock = gc0308->hdl.lock; 1348 gc0308->pad.flags = MEDIA_PAD_FL_SOURCE; 1349 gc0308->sd.entity.function = MEDIA_ENT_F_CAM_SENSOR; 1350 ret = media_entity_pads_init(&gc0308->sd.entity, 1, &gc0308->pad); 1351 if (ret < 0) 1352 goto fail_ctrl_hdl_cleanup; 1353 1354 ret = v4l2_subdev_init_finalize(&gc0308->sd); 1355 if (ret) 1356 goto fail_media_entity_cleanup; 1357 1358 ret = gc0308_power_on(dev); 1359 if (ret) 1360 goto fail_subdev_cleanup; 1361 1362 if (gc0308->clk) { 1363 clkrate = clk_get_rate(gc0308->clk); 1364 if (clkrate != 24000000) 1365 dev_warn(dev, "unexpected clock rate: %lu\n", clkrate); 1366 } 1367 1368 ret = cci_read(gc0308->regmap, GC0308_CHIP_ID, ®val, NULL); 1369 if (ret < 0) { 1370 dev_err_probe(dev, ret, "failed to read chip ID\n"); 1371 goto fail_power_off; 1372 } 1373 1374 if (regval != 0x9b) { 1375 ret = -EINVAL; 1376 dev_err_probe(dev, ret, "invalid chip ID (%02llx)\n", regval); 1377 goto fail_power_off; 1378 } 1379 1380 /* 1381 * Enable runtime PM with autosuspend. As the device has been powered 1382 * manually, mark it as active, and increase the usage count without 1383 * resuming the device. 1384 */ 1385 pm_runtime_set_active(dev); 1386 pm_runtime_get_noresume(dev); 1387 pm_runtime_enable(dev); 1388 pm_runtime_set_autosuspend_delay(dev, 1000); 1389 pm_runtime_use_autosuspend(dev); 1390 1391 ret = v4l2_async_register_subdev(&gc0308->sd); 1392 if (ret) { 1393 dev_err_probe(dev, ret, "failed to register v4l subdev\n"); 1394 goto fail_rpm; 1395 } 1396 1397 return 0; 1398 1399fail_rpm: 1400 pm_runtime_disable(dev); 1401 pm_runtime_put_noidle(dev); 1402fail_power_off: 1403 gc0308_power_off(dev); 1404fail_subdev_cleanup: 1405 v4l2_subdev_cleanup(&gc0308->sd); 1406fail_media_entity_cleanup: 1407 media_entity_cleanup(&gc0308->sd.entity); 1408fail_ctrl_hdl_cleanup: 1409 v4l2_ctrl_handler_free(&gc0308->hdl); 1410 return ret; 1411} 1412 1413static void gc0308_remove(struct i2c_client *client) 1414{ 1415 struct gc0308 *gc0308 = i2c_get_clientdata(client); 1416 struct device *dev = &client->dev; 1417 1418 v4l2_async_unregister_subdev(&gc0308->sd); 1419 v4l2_ctrl_handler_free(&gc0308->hdl); 1420 media_entity_cleanup(&gc0308->sd.entity); 1421 1422 pm_runtime_disable(dev); 1423 if (!pm_runtime_status_suspended(dev)) 1424 gc0308_power_off(dev); 1425 pm_runtime_set_suspended(dev); 1426} 1427 1428static const struct dev_pm_ops gc0308_pm_ops = { 1429 SET_RUNTIME_PM_OPS(gc0308_power_off, gc0308_power_on, NULL) 1430}; 1431 1432static const struct of_device_id gc0308_of_match[] = { 1433 { .compatible = "galaxycore,gc0308" }, 1434 { /* sentinel */ } 1435}; 1436MODULE_DEVICE_TABLE(of, gc0308_of_match); 1437 1438static struct i2c_driver gc0308_i2c_driver = { 1439 .driver = { 1440 .name = "gc0308", 1441 .pm = &gc0308_pm_ops, 1442 .of_match_table = gc0308_of_match, 1443 }, 1444 .probe = gc0308_probe, 1445 .remove = gc0308_remove, 1446}; 1447module_i2c_driver(gc0308_i2c_driver); 1448 1449MODULE_DESCRIPTION("GalaxyCore GC0308 Camera Driver"); 1450MODULE_AUTHOR("Sebastian Reichel <sre@kernel.org>"); 1451MODULE_LICENSE("GPL"); 1452