Searched refs:clk_sel (Results 1 - 24 of 24) sorted by relevance

/linux-master/drivers/gpu/drm/imx/ipuv3/
H A Dimx-ldb.c103 struct clk *clk_sel[4]; /* parent of display clock */ member in struct:imx_ldb
104 struct clk *clk_parent[4]; /* original parent of clk_sel */
189 ret = clk_set_parent(ldb->clk_sel[mux], ldb->clk[chno]);
203 if (mux < 0 || mux >= ARRAY_SIZE(ldb->clk_sel)) {
211 clk_set_parent(ldb->clk_sel[mux], ldb->clk[0]);
212 clk_set_parent(ldb->clk_sel[mux], ldb->clk[1]);
217 clk_set_parent(ldb->clk_sel[mux], ldb->clk[imx_ldb_ch->chno]);
266 if (mux < 0 || mux >= ARRAY_SIZE(ldb->clk_sel)) {
356 ret = clk_set_parent(ldb->clk_sel[mux], ldb->clk_parent[mux]);
659 imx_ldb->clk_sel[
[all...]
/linux-master/arch/mips/include/asm/octeon/
H A Dcvmx-gpio-defs.h53 uint64_t clk_sel:2; member in struct:cvmx_gpio_bit_cfgx::cvmx_gpio_bit_cfgx_s
67 uint64_t clk_sel:2;
97 uint64_t clk_sel:2; member in struct:cvmx_gpio_bit_cfgx::cvmx_gpio_bit_cfgx_cn52xx
111 uint64_t clk_sel:2;
360 uint64_t clk_sel:2; member in struct:cvmx_gpio_xbit_cfgx::cvmx_gpio_xbit_cfgx_s
374 uint64_t clk_sel:2;
/linux-master/drivers/gpu/drm/amd/display/dc/dcn20/
H A Ddcn20_dccg.c83 uint32_t clk_sel = 0; local
85 REG_GET_2(REFCLK_CNTL, REFCLK_CLOCK_EN, &clk_en, REFCLK_SRC_SEL, &clk_sel);
/linux-master/drivers/net/ethernet/atheros/atl1c/
H A Datl1c_hw.c274 void atl1c_start_phy_polling(struct atl1c_hw *hw, u16 clk_sel) argument
282 FIELDX(MDIO_CTRL_CLK_SEL, clk_sel) |
306 u16 clk_sel = MDIO_CTRL_CLK_25_4; local
315 clk_sel = MDIO_CTRL_CLK_25_128;
320 FIELDX(MDIO_CTRL_CLK_SEL, clk_sel) |
326 FIELDX(MDIO_CTRL_CLK_SEL, clk_sel) |
339 atl1c_start_phy_polling(hw, clk_sel);
355 u16 clk_sel = MDIO_CTRL_CLK_25_4; local
363 clk_sel = MDIO_CTRL_CLK_25_128;
369 FIELDX(MDIO_CTRL_CLK_SEL, clk_sel) |
[all...]
H A Datl1c_hw.h43 void atl1c_start_phy_polling(struct atl1c_hw *hw, u16 clk_sel);
/linux-master/drivers/video/fbdev/
H A Dgrvga.c42 int clk_sel; member in struct:grvga_par
112 par->clk_sel = i;
180 __raw_writel((par->clk_sel << 6) | (func << 4) | 1,
/linux-master/drivers/leds/rgb/
H A Dleds-qcom-lpg.c149 * @clk_sel: reference clock frequency selector
183 unsigned int clk_sel; member in struct:lpg_channel
416 unsigned int clk_sel, clk_len, best_clk = 0; local
480 for (clk_sel = 1; clk_sel < clk_len; clk_sel++) {
481 u64 numerator = period * clk_rate_arr[clk_sel];
498 clk_rate_arr[clk_sel]);
504 best_clk = clk_sel;
511 chan->clk_sel
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/linux-master/include/linux/
H A Dserial_s3c.h284 unsigned int clk_sel; member in struct:s3c2410_uartcfg
/linux-master/drivers/gpio/
H A Dgpio-npcm-sgpio.c53 unsigned int *clk_sel; member in struct:npcm_clk_cfg
297 iowrite8(clk_cfg->clk_sel[i] | tmp,
590 .clk_sel = npcm750_CLK_SEL,
596 .clk_sel = npcm845_CLK_SEL,
/linux-master/drivers/net/ethernet/atheros/alx/
H A Dhw.c64 u32 val, clk_sel; local
70 clk_sel = hw->link_speed != SPEED_UNKNOWN ?
81 clk_sel << ALX_MDIO_CLK_SEL_SHIFT;
84 clk_sel << ALX_MDIO_CLK_SEL_SHIFT |
101 u32 val, clk_sel; local
104 clk_sel = hw->link_speed != SPEED_UNKNOWN ?
114 clk_sel << ALX_MDIO_CLK_SEL_SHIFT |
119 clk_sel << ALX_MDIO_CLK_SEL_SHIFT |
/linux-master/drivers/iio/adc/
H A Dvf610_adc.c103 enum clk_sel { enum
141 enum clk_sel clk_sel; member in struct:vf610_adc_feature
238 adc_feature->clk_sel = VF610_ADCIOC_BUSCLK_SET;
258 switch (adc_feature->clk_sel) {
379 switch (adc_feature->clk_sel) {
H A Dstm32-adc-core.c68 * @clk_sel: clock selection routine
77 int (*clk_sel)(struct platform_device *, struct stm32_adc_priv *); member in struct:stm32_adc_priv_cfg
786 ret = priv->cfg->clk_sel(pdev, priv);
857 .clk_sel = stm32f4_adc_clk_sel,
865 .clk_sel = stm32h7_adc_clk_sel,
874 .clk_sel = stm32h7_adc_clk_sel,
883 .clk_sel = stm32h7_adc_clk_sel,
/linux-master/drivers/tty/serial/
H A Dsamsung_tty.c1355 static void s3c24xx_serial_setsource(struct uart_port *port, u8 clk_sel) argument
1364 if ((ucon & info->clksel_mask) >> info->clksel_shift == clk_sel)
1368 ucon |= clk_sel << info->clksel_shift;
1386 if (ourport->cfg->clk_sel &&
1387 !(ourport->cfg->clk_sel & (1 << cnt)))
1478 u8 clk_sel = 0; local
1491 quot = s3c24xx_serial_getclk(ourport, baud, &clk, &clk_sel);
1502 s3c24xx_serial_setsource(port, clk_sel);
1781 u8 clk_sel, clk_num; local
1783 clk_sel
2294 u8 clk_sel; local
[all...]
/linux-master/sound/soc/sti/
H A Duniperif_player.c957 if (player->clk_sel) {
958 ret = regmap_field_write(player->clk_sel, 1);
1031 player->clk_sel = regmap_field_alloc(regmap, regfield[0]);
1082 if (player->clk_sel) {
1083 ret = regmap_field_write(player->clk_sel, 1);
H A Duniperif.h1300 struct regmap_field *clk_sel; member in struct:uniperif
/linux-master/drivers/clk/ralink/
H A Dclk-mt7621.c261 u32 clkcfg, clk_sel, curclk, ffiv, ffrac; local
266 clk_sel = FIELD_GET(CPU_CLK_SEL_MASK, clkcfg);
272 switch (clk_sel) {
/linux-master/drivers/spi/
H A Dspi-sunplus-sp7021.c287 u32 clk_rate, clk_sel, div; local
292 clk_sel = (div / 2) - 1;
294 pspim->xfer_conf |= FIELD_PREP(SP7021_CLK_MASK, clk_sel);
H A Dspi-geni-qcom.c361 u32 clk_sel, m_clk_cfg, idx, div; local
383 clk_sel = idx & CLK_SEL_MSK;
385 writel(clk_sel, se->base + SE_GENI_CLK_SEL);
/linux-master/drivers/clk/imx/
H A Dclk-imx93.c18 enum clk_sel { enum
54 enum clk_sel sel;
/linux-master/drivers/clk/mvebu/
H A Darmada-37xx-periph.c67 u32 clk_sel; member in struct:clk_periph_driver_data
702 data->clk_sel = readl(data->reg + CLK_SEL);
718 writel(data->clk_sel, data->reg + CLK_SEL);
/linux-master/sound/soc/intel/atom/sst/
H A Dsst.h117 u64 clk_sel:3; member in struct:config_status_reg_mrfld::__anon4290
/linux-master/drivers/media/dvb-frontends/
H A Dstv0900_core.c287 u32 m_div, clk_sel; local
298 clk_sel = ((stv0900_get_bits(intp, F0900_SELX1RATIO) == 1) ? 4 : 6);
299 m_div = ((clk_sel * mclk) / intp->quartz) - 1;
H A Dstv090x.c4272 u32 reg, div, clk_sel; local
4275 clk_sel = ((STV090x_GETFIELD(reg, SELX1RATIO_FIELD) == 1) ? 4 : 6);
4277 div = ((clk_sel * mclk) / config->xtal) - 1;
/linux-master/drivers/gpu/drm/i915/display/
H A Dintel_ddi.c1482 u32 clk_sel_mask, u32 clk_sel, u32 clk_off)
1486 intel_de_rmw(i915, reg, clk_sel_mask, clk_sel);
1481 _icl_ddi_enable_clock(struct drm_i915_private *i915, i915_reg_t reg, u32 clk_sel_mask, u32 clk_sel, u32 clk_off) argument

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