1// SPDX-License-Identifier: GPL-2.0 2/* 3 * This file is part of STM32 ADC driver 4 * 5 * Copyright (C) 2016, STMicroelectronics - All Rights Reserved 6 * Author: Fabrice Gasnier <fabrice.gasnier@st.com>. 7 * 8 * Inspired from: fsl-imx25-tsadc 9 * 10 */ 11 12#include <linux/bitfield.h> 13#include <linux/clk.h> 14#include <linux/interrupt.h> 15#include <linux/irqchip/chained_irq.h> 16#include <linux/irqdesc.h> 17#include <linux/irqdomain.h> 18#include <linux/mfd/syscon.h> 19#include <linux/module.h> 20#include <linux/of.h> 21#include <linux/of_platform.h> 22#include <linux/platform_device.h> 23#include <linux/pm_runtime.h> 24#include <linux/property.h> 25#include <linux/regmap.h> 26#include <linux/regulator/consumer.h> 27#include <linux/slab.h> 28#include <linux/units.h> 29 30#include "stm32-adc-core.h" 31 32#define STM32_ADC_CORE_SLEEP_DELAY_MS 2000 33 34/* SYSCFG registers */ 35#define STM32MP1_SYSCFG_PMCSETR 0x04 36#define STM32MP1_SYSCFG_PMCCLRR 0x44 37 38/* SYSCFG bit fields */ 39#define STM32MP1_SYSCFG_ANASWVDD_MASK BIT(9) 40 41/* SYSCFG capability flags */ 42#define HAS_VBOOSTER BIT(0) 43#define HAS_ANASWVDD BIT(1) 44 45/** 46 * struct stm32_adc_common_regs - stm32 common registers 47 * @csr: common status register offset 48 * @ccr: common control register offset 49 * @eoc_msk: array of eoc (end of conversion flag) masks in csr for adc1..n 50 * @ovr_msk: array of ovr (overrun flag) masks in csr for adc1..n 51 * @ier: interrupt enable register offset for each adc 52 * @eocie_msk: end of conversion interrupt enable mask in @ier 53 */ 54struct stm32_adc_common_regs { 55 u32 csr; 56 u32 ccr; 57 u32 eoc_msk[STM32_ADC_MAX_ADCS]; 58 u32 ovr_msk[STM32_ADC_MAX_ADCS]; 59 u32 ier; 60 u32 eocie_msk; 61}; 62 63struct stm32_adc_priv; 64 65/** 66 * struct stm32_adc_priv_cfg - stm32 core compatible configuration data 67 * @regs: common registers for all instances 68 * @clk_sel: clock selection routine 69 * @max_clk_rate_hz: maximum analog clock rate (Hz, from datasheet) 70 * @ipid: adc identification number 71 * @has_syscfg: SYSCFG capability flags 72 * @num_irqs: number of interrupt lines 73 * @num_adcs: maximum number of ADC instances in the common registers 74 */ 75struct stm32_adc_priv_cfg { 76 const struct stm32_adc_common_regs *regs; 77 int (*clk_sel)(struct platform_device *, struct stm32_adc_priv *); 78 u32 max_clk_rate_hz; 79 u32 ipid; 80 unsigned int has_syscfg; 81 unsigned int num_irqs; 82 unsigned int num_adcs; 83}; 84 85/** 86 * struct stm32_adc_priv - stm32 ADC core private data 87 * @irq: irq(s) for ADC block 88 * @nb_adc_max: actual maximum number of instance per ADC block 89 * @domain: irq domain reference 90 * @aclk: clock reference for the analog circuitry 91 * @bclk: bus clock common for all ADCs, depends on part used 92 * @max_clk_rate: desired maximum clock rate 93 * @booster: booster supply reference 94 * @vdd: vdd supply reference 95 * @vdda: vdda analog supply reference 96 * @vref: regulator reference 97 * @vdd_uv: vdd supply voltage (microvolts) 98 * @vdda_uv: vdda supply voltage (microvolts) 99 * @cfg: compatible configuration data 100 * @common: common data for all ADC instances 101 * @ccr_bak: backup CCR in low power mode 102 * @syscfg: reference to syscon, system control registers 103 */ 104struct stm32_adc_priv { 105 int irq[STM32_ADC_MAX_ADCS]; 106 unsigned int nb_adc_max; 107 struct irq_domain *domain; 108 struct clk *aclk; 109 struct clk *bclk; 110 u32 max_clk_rate; 111 struct regulator *booster; 112 struct regulator *vdd; 113 struct regulator *vdda; 114 struct regulator *vref; 115 int vdd_uv; 116 int vdda_uv; 117 const struct stm32_adc_priv_cfg *cfg; 118 struct stm32_adc_common common; 119 u32 ccr_bak; 120 struct regmap *syscfg; 121}; 122 123static struct stm32_adc_priv *to_stm32_adc_priv(struct stm32_adc_common *com) 124{ 125 return container_of(com, struct stm32_adc_priv, common); 126} 127 128/* STM32F4 ADC internal common clock prescaler division ratios */ 129static int stm32f4_pclk_div[] = {2, 4, 6, 8}; 130 131/** 132 * stm32f4_adc_clk_sel() - Select stm32f4 ADC common clock prescaler 133 * @pdev: platform device 134 * @priv: stm32 ADC core private data 135 * Select clock prescaler used for analog conversions, before using ADC. 136 */ 137static int stm32f4_adc_clk_sel(struct platform_device *pdev, 138 struct stm32_adc_priv *priv) 139{ 140 unsigned long rate; 141 u32 val; 142 int i; 143 144 /* stm32f4 has one clk input for analog (mandatory), enforce it here */ 145 if (!priv->aclk) { 146 dev_err(&pdev->dev, "No 'adc' clock found\n"); 147 return -ENOENT; 148 } 149 150 rate = clk_get_rate(priv->aclk); 151 if (!rate) { 152 dev_err(&pdev->dev, "Invalid clock rate: 0\n"); 153 return -EINVAL; 154 } 155 156 for (i = 0; i < ARRAY_SIZE(stm32f4_pclk_div); i++) { 157 if ((rate / stm32f4_pclk_div[i]) <= priv->max_clk_rate) 158 break; 159 } 160 if (i >= ARRAY_SIZE(stm32f4_pclk_div)) { 161 dev_err(&pdev->dev, "adc clk selection failed\n"); 162 return -EINVAL; 163 } 164 165 priv->common.rate = rate / stm32f4_pclk_div[i]; 166 val = readl_relaxed(priv->common.base + STM32F4_ADC_CCR); 167 val &= ~STM32F4_ADC_ADCPRE_MASK; 168 val |= i << STM32F4_ADC_ADCPRE_SHIFT; 169 writel_relaxed(val, priv->common.base + STM32F4_ADC_CCR); 170 171 dev_dbg(&pdev->dev, "Using analog clock source at %ld kHz\n", 172 priv->common.rate / 1000); 173 174 return 0; 175} 176 177/** 178 * struct stm32h7_adc_ck_spec - specification for stm32h7 adc clock 179 * @ckmode: ADC clock mode, Async or sync with prescaler. 180 * @presc: prescaler bitfield for async clock mode 181 * @div: prescaler division ratio 182 */ 183struct stm32h7_adc_ck_spec { 184 u32 ckmode; 185 u32 presc; 186 int div; 187}; 188 189static const struct stm32h7_adc_ck_spec stm32h7_adc_ckmodes_spec[] = { 190 /* 00: CK_ADC[1..3]: Asynchronous clock modes */ 191 { 0, 0, 1 }, 192 { 0, 1, 2 }, 193 { 0, 2, 4 }, 194 { 0, 3, 6 }, 195 { 0, 4, 8 }, 196 { 0, 5, 10 }, 197 { 0, 6, 12 }, 198 { 0, 7, 16 }, 199 { 0, 8, 32 }, 200 { 0, 9, 64 }, 201 { 0, 10, 128 }, 202 { 0, 11, 256 }, 203 /* HCLK used: Synchronous clock modes (1, 2 or 4 prescaler) */ 204 { 1, 0, 1 }, 205 { 2, 0, 2 }, 206 { 3, 0, 4 }, 207}; 208 209static int stm32h7_adc_clk_sel(struct platform_device *pdev, 210 struct stm32_adc_priv *priv) 211{ 212 u32 ckmode, presc, val; 213 unsigned long rate; 214 int i, div, duty; 215 216 /* stm32h7 bus clock is common for all ADC instances (mandatory) */ 217 if (!priv->bclk) { 218 dev_err(&pdev->dev, "No 'bus' clock found\n"); 219 return -ENOENT; 220 } 221 222 /* 223 * stm32h7 can use either 'bus' or 'adc' clock for analog circuitry. 224 * So, choice is to have bus clock mandatory and adc clock optional. 225 * If optional 'adc' clock has been found, then try to use it first. 226 */ 227 if (priv->aclk) { 228 /* 229 * Asynchronous clock modes (e.g. ckmode == 0) 230 * From spec: PLL output musn't exceed max rate 231 */ 232 rate = clk_get_rate(priv->aclk); 233 if (!rate) { 234 dev_err(&pdev->dev, "Invalid adc clock rate: 0\n"); 235 return -EINVAL; 236 } 237 238 /* If duty is an error, kindly use at least /2 divider */ 239 duty = clk_get_scaled_duty_cycle(priv->aclk, 100); 240 if (duty < 0) 241 dev_warn(&pdev->dev, "adc clock duty: %d\n", duty); 242 243 for (i = 0; i < ARRAY_SIZE(stm32h7_adc_ckmodes_spec); i++) { 244 ckmode = stm32h7_adc_ckmodes_spec[i].ckmode; 245 presc = stm32h7_adc_ckmodes_spec[i].presc; 246 div = stm32h7_adc_ckmodes_spec[i].div; 247 248 if (ckmode) 249 continue; 250 251 /* 252 * For proper operation, clock duty cycle range is 49% 253 * to 51%. Apply at least /2 prescaler otherwise. 254 */ 255 if (div == 1 && (duty < 49 || duty > 51)) 256 continue; 257 258 if ((rate / div) <= priv->max_clk_rate) 259 goto out; 260 } 261 } 262 263 /* Synchronous clock modes (e.g. ckmode is 1, 2 or 3) */ 264 rate = clk_get_rate(priv->bclk); 265 if (!rate) { 266 dev_err(&pdev->dev, "Invalid bus clock rate: 0\n"); 267 return -EINVAL; 268 } 269 270 duty = clk_get_scaled_duty_cycle(priv->bclk, 100); 271 if (duty < 0) 272 dev_warn(&pdev->dev, "bus clock duty: %d\n", duty); 273 274 for (i = 0; i < ARRAY_SIZE(stm32h7_adc_ckmodes_spec); i++) { 275 ckmode = stm32h7_adc_ckmodes_spec[i].ckmode; 276 presc = stm32h7_adc_ckmodes_spec[i].presc; 277 div = stm32h7_adc_ckmodes_spec[i].div; 278 279 if (!ckmode) 280 continue; 281 282 if (div == 1 && (duty < 49 || duty > 51)) 283 continue; 284 285 if ((rate / div) <= priv->max_clk_rate) 286 goto out; 287 } 288 289 dev_err(&pdev->dev, "adc clk selection failed\n"); 290 return -EINVAL; 291 292out: 293 /* rate used later by each ADC instance to control BOOST mode */ 294 priv->common.rate = rate / div; 295 296 /* Set common clock mode and prescaler */ 297 val = readl_relaxed(priv->common.base + STM32H7_ADC_CCR); 298 val &= ~(STM32H7_CKMODE_MASK | STM32H7_PRESC_MASK); 299 val |= ckmode << STM32H7_CKMODE_SHIFT; 300 val |= presc << STM32H7_PRESC_SHIFT; 301 writel_relaxed(val, priv->common.base + STM32H7_ADC_CCR); 302 303 dev_dbg(&pdev->dev, "Using %s clock/%d source at %ld kHz\n", 304 ckmode ? "bus" : "adc", div, priv->common.rate / 1000); 305 306 return 0; 307} 308 309/* STM32F4 common registers definitions */ 310static const struct stm32_adc_common_regs stm32f4_adc_common_regs = { 311 .csr = STM32F4_ADC_CSR, 312 .ccr = STM32F4_ADC_CCR, 313 .eoc_msk = { STM32F4_EOC1, STM32F4_EOC2, STM32F4_EOC3 }, 314 .ovr_msk = { STM32F4_OVR1, STM32F4_OVR2, STM32F4_OVR3 }, 315 .ier = STM32F4_ADC_CR1, 316 .eocie_msk = STM32F4_EOCIE, 317}; 318 319/* STM32H7 common registers definitions */ 320static const struct stm32_adc_common_regs stm32h7_adc_common_regs = { 321 .csr = STM32H7_ADC_CSR, 322 .ccr = STM32H7_ADC_CCR, 323 .eoc_msk = { STM32H7_EOC_MST, STM32H7_EOC_SLV }, 324 .ovr_msk = { STM32H7_OVR_MST, STM32H7_OVR_SLV }, 325 .ier = STM32H7_ADC_IER, 326 .eocie_msk = STM32H7_EOCIE, 327}; 328 329/* STM32MP13 common registers definitions */ 330static const struct stm32_adc_common_regs stm32mp13_adc_common_regs = { 331 .csr = STM32H7_ADC_CSR, 332 .ccr = STM32H7_ADC_CCR, 333 .eoc_msk = { STM32H7_EOC_MST }, 334 .ovr_msk = { STM32H7_OVR_MST }, 335 .ier = STM32H7_ADC_IER, 336 .eocie_msk = STM32H7_EOCIE, 337}; 338 339static const unsigned int stm32_adc_offset[STM32_ADC_MAX_ADCS] = { 340 0, STM32_ADC_OFFSET, STM32_ADC_OFFSET * 2, 341}; 342 343static unsigned int stm32_adc_eoc_enabled(struct stm32_adc_priv *priv, 344 unsigned int adc) 345{ 346 u32 ier, offset = stm32_adc_offset[adc]; 347 348 ier = readl_relaxed(priv->common.base + offset + priv->cfg->regs->ier); 349 350 return ier & priv->cfg->regs->eocie_msk; 351} 352 353/* ADC common interrupt for all instances */ 354static void stm32_adc_irq_handler(struct irq_desc *desc) 355{ 356 struct stm32_adc_priv *priv = irq_desc_get_handler_data(desc); 357 struct irq_chip *chip = irq_desc_get_chip(desc); 358 int i; 359 u32 status; 360 361 chained_irq_enter(chip, desc); 362 status = readl_relaxed(priv->common.base + priv->cfg->regs->csr); 363 364 /* 365 * End of conversion may be handled by using IRQ or DMA. There may be a 366 * race here when two conversions complete at the same time on several 367 * ADCs. EOC may be read 'set' for several ADCs, with: 368 * - an ADC configured to use DMA (EOC triggers the DMA request, and 369 * is then automatically cleared by DR read in hardware) 370 * - an ADC configured to use IRQs (EOCIE bit is set. The handler must 371 * be called in this case) 372 * So both EOC status bit in CSR and EOCIE control bit must be checked 373 * before invoking the interrupt handler (e.g. call ISR only for 374 * IRQ-enabled ADCs). 375 */ 376 for (i = 0; i < priv->nb_adc_max; i++) { 377 if ((status & priv->cfg->regs->eoc_msk[i] && 378 stm32_adc_eoc_enabled(priv, i)) || 379 (status & priv->cfg->regs->ovr_msk[i])) 380 generic_handle_domain_irq(priv->domain, i); 381 } 382 383 chained_irq_exit(chip, desc); 384}; 385 386static int stm32_adc_domain_map(struct irq_domain *d, unsigned int irq, 387 irq_hw_number_t hwirq) 388{ 389 irq_set_chip_data(irq, d->host_data); 390 irq_set_chip_and_handler(irq, &dummy_irq_chip, handle_level_irq); 391 392 return 0; 393} 394 395static void stm32_adc_domain_unmap(struct irq_domain *d, unsigned int irq) 396{ 397 irq_set_chip_and_handler(irq, NULL, NULL); 398 irq_set_chip_data(irq, NULL); 399} 400 401static const struct irq_domain_ops stm32_adc_domain_ops = { 402 .map = stm32_adc_domain_map, 403 .unmap = stm32_adc_domain_unmap, 404 .xlate = irq_domain_xlate_onecell, 405}; 406 407static int stm32_adc_irq_probe(struct platform_device *pdev, 408 struct stm32_adc_priv *priv) 409{ 410 struct device_node *np = pdev->dev.of_node; 411 unsigned int i; 412 413 /* 414 * Interrupt(s) must be provided, depending on the compatible: 415 * - stm32f4/h7 shares a common interrupt line. 416 * - stm32mp1, has one line per ADC 417 */ 418 for (i = 0; i < priv->cfg->num_irqs; i++) { 419 priv->irq[i] = platform_get_irq(pdev, i); 420 if (priv->irq[i] < 0) 421 return priv->irq[i]; 422 } 423 424 priv->domain = irq_domain_add_simple(np, STM32_ADC_MAX_ADCS, 0, 425 &stm32_adc_domain_ops, 426 priv); 427 if (!priv->domain) { 428 dev_err(&pdev->dev, "Failed to add irq domain\n"); 429 return -ENOMEM; 430 } 431 432 for (i = 0; i < priv->cfg->num_irqs; i++) { 433 irq_set_chained_handler(priv->irq[i], stm32_adc_irq_handler); 434 irq_set_handler_data(priv->irq[i], priv); 435 } 436 437 return 0; 438} 439 440static void stm32_adc_irq_remove(struct platform_device *pdev, 441 struct stm32_adc_priv *priv) 442{ 443 int hwirq; 444 unsigned int i; 445 446 for (hwirq = 0; hwirq < priv->nb_adc_max; hwirq++) 447 irq_dispose_mapping(irq_find_mapping(priv->domain, hwirq)); 448 irq_domain_remove(priv->domain); 449 450 for (i = 0; i < priv->cfg->num_irqs; i++) 451 irq_set_chained_handler(priv->irq[i], NULL); 452} 453 454static int stm32_adc_core_switches_supply_en(struct stm32_adc_priv *priv, 455 struct device *dev) 456{ 457 int ret; 458 459 /* 460 * On STM32H7 and STM32MP1, the ADC inputs are multiplexed with analog 461 * switches (via PCSEL) which have reduced performances when their 462 * supply is below 2.7V (vdda by default): 463 * - Voltage booster can be used, to get full ADC performances 464 * (increases power consumption). 465 * - Vdd can be used to supply them, if above 2.7V (STM32MP1 only). 466 * 467 * Recommended settings for ANASWVDD and EN_BOOSTER: 468 * - vdda < 2.7V but vdd > 2.7V: ANASWVDD = 1, EN_BOOSTER = 0 (stm32mp1) 469 * - vdda < 2.7V and vdd < 2.7V: ANASWVDD = 0, EN_BOOSTER = 1 470 * - vdda >= 2.7V: ANASWVDD = 0, EN_BOOSTER = 0 (default) 471 */ 472 if (priv->vdda_uv < 2700000) { 473 if (priv->syscfg && priv->vdd_uv > 2700000) { 474 ret = regulator_enable(priv->vdd); 475 if (ret < 0) { 476 dev_err(dev, "vdd enable failed %d\n", ret); 477 return ret; 478 } 479 480 ret = regmap_write(priv->syscfg, 481 STM32MP1_SYSCFG_PMCSETR, 482 STM32MP1_SYSCFG_ANASWVDD_MASK); 483 if (ret < 0) { 484 regulator_disable(priv->vdd); 485 dev_err(dev, "vdd select failed, %d\n", ret); 486 return ret; 487 } 488 dev_dbg(dev, "analog switches supplied by vdd\n"); 489 490 return 0; 491 } 492 493 if (priv->booster) { 494 /* 495 * This is optional, as this is a trade-off between 496 * analog performance and power consumption. 497 */ 498 ret = regulator_enable(priv->booster); 499 if (ret < 0) { 500 dev_err(dev, "booster enable failed %d\n", ret); 501 return ret; 502 } 503 dev_dbg(dev, "analog switches supplied by booster\n"); 504 505 return 0; 506 } 507 } 508 509 /* Fallback using vdda (default), nothing to do */ 510 dev_dbg(dev, "analog switches supplied by vdda (%d uV)\n", 511 priv->vdda_uv); 512 513 return 0; 514} 515 516static void stm32_adc_core_switches_supply_dis(struct stm32_adc_priv *priv) 517{ 518 if (priv->vdda_uv < 2700000) { 519 if (priv->syscfg && priv->vdd_uv > 2700000) { 520 regmap_write(priv->syscfg, STM32MP1_SYSCFG_PMCCLRR, 521 STM32MP1_SYSCFG_ANASWVDD_MASK); 522 regulator_disable(priv->vdd); 523 return; 524 } 525 if (priv->booster) 526 regulator_disable(priv->booster); 527 } 528} 529 530static int stm32_adc_core_hw_start(struct device *dev) 531{ 532 struct stm32_adc_common *common = dev_get_drvdata(dev); 533 struct stm32_adc_priv *priv = to_stm32_adc_priv(common); 534 int ret; 535 536 ret = regulator_enable(priv->vdda); 537 if (ret < 0) { 538 dev_err(dev, "vdda enable failed %d\n", ret); 539 return ret; 540 } 541 542 ret = regulator_get_voltage(priv->vdda); 543 if (ret < 0) { 544 dev_err(dev, "vdda get voltage failed, %d\n", ret); 545 goto err_vdda_disable; 546 } 547 priv->vdda_uv = ret; 548 549 ret = stm32_adc_core_switches_supply_en(priv, dev); 550 if (ret < 0) 551 goto err_vdda_disable; 552 553 ret = regulator_enable(priv->vref); 554 if (ret < 0) { 555 dev_err(dev, "vref enable failed\n"); 556 goto err_switches_dis; 557 } 558 559 ret = clk_prepare_enable(priv->bclk); 560 if (ret < 0) { 561 dev_err(dev, "bus clk enable failed\n"); 562 goto err_regulator_disable; 563 } 564 565 ret = clk_prepare_enable(priv->aclk); 566 if (ret < 0) { 567 dev_err(dev, "adc clk enable failed\n"); 568 goto err_bclk_disable; 569 } 570 571 writel_relaxed(priv->ccr_bak, priv->common.base + priv->cfg->regs->ccr); 572 573 return 0; 574 575err_bclk_disable: 576 clk_disable_unprepare(priv->bclk); 577err_regulator_disable: 578 regulator_disable(priv->vref); 579err_switches_dis: 580 stm32_adc_core_switches_supply_dis(priv); 581err_vdda_disable: 582 regulator_disable(priv->vdda); 583 584 return ret; 585} 586 587static void stm32_adc_core_hw_stop(struct device *dev) 588{ 589 struct stm32_adc_common *common = dev_get_drvdata(dev); 590 struct stm32_adc_priv *priv = to_stm32_adc_priv(common); 591 592 /* Backup CCR that may be lost (depends on power state to achieve) */ 593 priv->ccr_bak = readl_relaxed(priv->common.base + priv->cfg->regs->ccr); 594 clk_disable_unprepare(priv->aclk); 595 clk_disable_unprepare(priv->bclk); 596 regulator_disable(priv->vref); 597 stm32_adc_core_switches_supply_dis(priv); 598 regulator_disable(priv->vdda); 599} 600 601static int stm32_adc_core_switches_probe(struct device *dev, 602 struct stm32_adc_priv *priv) 603{ 604 struct device_node *np = dev->of_node; 605 int ret; 606 607 /* Analog switches supply can be controlled by syscfg (optional) */ 608 priv->syscfg = syscon_regmap_lookup_by_phandle(np, "st,syscfg"); 609 if (IS_ERR(priv->syscfg)) { 610 ret = PTR_ERR(priv->syscfg); 611 if (ret != -ENODEV) 612 return dev_err_probe(dev, ret, "Can't probe syscfg\n"); 613 614 priv->syscfg = NULL; 615 } 616 617 /* Booster can be used to supply analog switches (optional) */ 618 if (priv->cfg->has_syscfg & HAS_VBOOSTER && 619 of_property_read_bool(np, "booster-supply")) { 620 priv->booster = devm_regulator_get_optional(dev, "booster"); 621 if (IS_ERR(priv->booster)) { 622 ret = PTR_ERR(priv->booster); 623 if (ret != -ENODEV) 624 return dev_err_probe(dev, ret, "can't get booster\n"); 625 626 priv->booster = NULL; 627 } 628 } 629 630 /* Vdd can be used to supply analog switches (optional) */ 631 if (priv->cfg->has_syscfg & HAS_ANASWVDD && 632 of_property_read_bool(np, "vdd-supply")) { 633 priv->vdd = devm_regulator_get_optional(dev, "vdd"); 634 if (IS_ERR(priv->vdd)) { 635 ret = PTR_ERR(priv->vdd); 636 if (ret != -ENODEV) 637 return dev_err_probe(dev, ret, "can't get vdd\n"); 638 639 priv->vdd = NULL; 640 } 641 } 642 643 if (priv->vdd) { 644 ret = regulator_enable(priv->vdd); 645 if (ret < 0) { 646 dev_err(dev, "vdd enable failed %d\n", ret); 647 return ret; 648 } 649 650 ret = regulator_get_voltage(priv->vdd); 651 if (ret < 0) { 652 dev_err(dev, "vdd get voltage failed %d\n", ret); 653 regulator_disable(priv->vdd); 654 return ret; 655 } 656 priv->vdd_uv = ret; 657 658 regulator_disable(priv->vdd); 659 } 660 661 return 0; 662} 663 664static int stm32_adc_probe_identification(struct platform_device *pdev, 665 struct stm32_adc_priv *priv) 666{ 667 struct device_node *np = pdev->dev.of_node; 668 struct device_node *child; 669 const char *compat; 670 int ret, count = 0; 671 u32 id, val; 672 673 if (!priv->cfg->ipid) 674 return 0; 675 676 id = FIELD_GET(STM32MP1_IPIDR_MASK, 677 readl_relaxed(priv->common.base + STM32MP1_ADC_IPDR)); 678 if (id != priv->cfg->ipid) { 679 dev_err(&pdev->dev, "Unexpected IP version: 0x%x", id); 680 return -EINVAL; 681 } 682 683 for_each_child_of_node(np, child) { 684 ret = of_property_read_string(child, "compatible", &compat); 685 if (ret) 686 continue; 687 /* Count child nodes with stm32 adc compatible */ 688 if (strstr(compat, "st,stm32") && strstr(compat, "adc")) 689 count++; 690 } 691 692 val = readl_relaxed(priv->common.base + STM32MP1_ADC_HWCFGR0); 693 priv->nb_adc_max = FIELD_GET(STM32MP1_ADCNUM_MASK, val); 694 if (count > priv->nb_adc_max) { 695 dev_err(&pdev->dev, "Unexpected child number: %d", count); 696 return -EINVAL; 697 } 698 699 val = readl_relaxed(priv->common.base + STM32MP1_ADC_VERR); 700 dev_dbg(&pdev->dev, "ADC version: %lu.%lu\n", 701 FIELD_GET(STM32MP1_MAJREV_MASK, val), 702 FIELD_GET(STM32MP1_MINREV_MASK, val)); 703 704 return 0; 705} 706 707static int stm32_adc_probe(struct platform_device *pdev) 708{ 709 struct stm32_adc_priv *priv; 710 struct device *dev = &pdev->dev; 711 struct device_node *np = pdev->dev.of_node; 712 struct resource *res; 713 u32 max_rate; 714 int ret; 715 716 if (!pdev->dev.of_node) 717 return -ENODEV; 718 719 priv = devm_kzalloc(&pdev->dev, sizeof(*priv), GFP_KERNEL); 720 if (!priv) 721 return -ENOMEM; 722 platform_set_drvdata(pdev, &priv->common); 723 724 priv->cfg = device_get_match_data(dev); 725 priv->nb_adc_max = priv->cfg->num_adcs; 726 spin_lock_init(&priv->common.lock); 727 728 priv->common.base = devm_platform_get_and_ioremap_resource(pdev, 0, &res); 729 if (IS_ERR(priv->common.base)) 730 return PTR_ERR(priv->common.base); 731 priv->common.phys_base = res->start; 732 733 priv->vdda = devm_regulator_get(&pdev->dev, "vdda"); 734 if (IS_ERR(priv->vdda)) 735 return dev_err_probe(&pdev->dev, PTR_ERR(priv->vdda), 736 "vdda get failed\n"); 737 738 priv->vref = devm_regulator_get(&pdev->dev, "vref"); 739 if (IS_ERR(priv->vref)) 740 return dev_err_probe(&pdev->dev, PTR_ERR(priv->vref), 741 "vref get failed\n"); 742 743 priv->aclk = devm_clk_get_optional(&pdev->dev, "adc"); 744 if (IS_ERR(priv->aclk)) 745 return dev_err_probe(&pdev->dev, PTR_ERR(priv->aclk), 746 "Can't get 'adc' clock\n"); 747 748 priv->bclk = devm_clk_get_optional(&pdev->dev, "bus"); 749 if (IS_ERR(priv->bclk)) 750 return dev_err_probe(&pdev->dev, PTR_ERR(priv->bclk), 751 "Can't get 'bus' clock\n"); 752 753 ret = stm32_adc_core_switches_probe(dev, priv); 754 if (ret) 755 return ret; 756 757 pm_runtime_get_noresume(dev); 758 pm_runtime_set_active(dev); 759 pm_runtime_set_autosuspend_delay(dev, STM32_ADC_CORE_SLEEP_DELAY_MS); 760 pm_runtime_use_autosuspend(dev); 761 pm_runtime_enable(dev); 762 763 ret = stm32_adc_core_hw_start(dev); 764 if (ret) 765 goto err_pm_stop; 766 767 ret = stm32_adc_probe_identification(pdev, priv); 768 if (ret < 0) 769 goto err_hw_stop; 770 771 ret = regulator_get_voltage(priv->vref); 772 if (ret < 0) { 773 dev_err(&pdev->dev, "vref get voltage failed, %d\n", ret); 774 goto err_hw_stop; 775 } 776 priv->common.vref_mv = ret / 1000; 777 dev_dbg(&pdev->dev, "vref+=%dmV\n", priv->common.vref_mv); 778 779 ret = of_property_read_u32(pdev->dev.of_node, "st,max-clk-rate-hz", 780 &max_rate); 781 if (!ret) 782 priv->max_clk_rate = min(max_rate, priv->cfg->max_clk_rate_hz); 783 else 784 priv->max_clk_rate = priv->cfg->max_clk_rate_hz; 785 786 ret = priv->cfg->clk_sel(pdev, priv); 787 if (ret < 0) 788 goto err_hw_stop; 789 790 ret = stm32_adc_irq_probe(pdev, priv); 791 if (ret < 0) 792 goto err_hw_stop; 793 794 ret = of_platform_populate(np, NULL, NULL, &pdev->dev); 795 if (ret < 0) { 796 dev_err(&pdev->dev, "failed to populate DT children\n"); 797 goto err_irq_remove; 798 } 799 800 pm_runtime_mark_last_busy(dev); 801 pm_runtime_put_autosuspend(dev); 802 803 return 0; 804 805err_irq_remove: 806 stm32_adc_irq_remove(pdev, priv); 807err_hw_stop: 808 stm32_adc_core_hw_stop(dev); 809err_pm_stop: 810 pm_runtime_disable(dev); 811 pm_runtime_set_suspended(dev); 812 pm_runtime_put_noidle(dev); 813 814 return ret; 815} 816 817static void stm32_adc_remove(struct platform_device *pdev) 818{ 819 struct stm32_adc_common *common = platform_get_drvdata(pdev); 820 struct stm32_adc_priv *priv = to_stm32_adc_priv(common); 821 822 pm_runtime_get_sync(&pdev->dev); 823 of_platform_depopulate(&pdev->dev); 824 stm32_adc_irq_remove(pdev, priv); 825 stm32_adc_core_hw_stop(&pdev->dev); 826 pm_runtime_disable(&pdev->dev); 827 pm_runtime_set_suspended(&pdev->dev); 828 pm_runtime_put_noidle(&pdev->dev); 829} 830 831static int stm32_adc_core_runtime_suspend(struct device *dev) 832{ 833 stm32_adc_core_hw_stop(dev); 834 835 return 0; 836} 837 838static int stm32_adc_core_runtime_resume(struct device *dev) 839{ 840 return stm32_adc_core_hw_start(dev); 841} 842 843static int stm32_adc_core_runtime_idle(struct device *dev) 844{ 845 pm_runtime_mark_last_busy(dev); 846 847 return 0; 848} 849 850static DEFINE_RUNTIME_DEV_PM_OPS(stm32_adc_core_pm_ops, 851 stm32_adc_core_runtime_suspend, 852 stm32_adc_core_runtime_resume, 853 stm32_adc_core_runtime_idle); 854 855static const struct stm32_adc_priv_cfg stm32f4_adc_priv_cfg = { 856 .regs = &stm32f4_adc_common_regs, 857 .clk_sel = stm32f4_adc_clk_sel, 858 .max_clk_rate_hz = 36000000, 859 .num_irqs = 1, 860 .num_adcs = 3, 861}; 862 863static const struct stm32_adc_priv_cfg stm32h7_adc_priv_cfg = { 864 .regs = &stm32h7_adc_common_regs, 865 .clk_sel = stm32h7_adc_clk_sel, 866 .max_clk_rate_hz = 36000000, 867 .has_syscfg = HAS_VBOOSTER, 868 .num_irqs = 1, 869 .num_adcs = 2, 870}; 871 872static const struct stm32_adc_priv_cfg stm32mp1_adc_priv_cfg = { 873 .regs = &stm32h7_adc_common_regs, 874 .clk_sel = stm32h7_adc_clk_sel, 875 .max_clk_rate_hz = 36000000, 876 .has_syscfg = HAS_VBOOSTER | HAS_ANASWVDD, 877 .ipid = STM32MP15_IPIDR_NUMBER, 878 .num_irqs = 2, 879}; 880 881static const struct stm32_adc_priv_cfg stm32mp13_adc_priv_cfg = { 882 .regs = &stm32mp13_adc_common_regs, 883 .clk_sel = stm32h7_adc_clk_sel, 884 .max_clk_rate_hz = 75 * HZ_PER_MHZ, 885 .ipid = STM32MP13_IPIDR_NUMBER, 886 .num_irqs = 1, 887}; 888 889static const struct of_device_id stm32_adc_of_match[] = { 890 { 891 .compatible = "st,stm32f4-adc-core", 892 .data = (void *)&stm32f4_adc_priv_cfg 893 }, { 894 .compatible = "st,stm32h7-adc-core", 895 .data = (void *)&stm32h7_adc_priv_cfg 896 }, { 897 .compatible = "st,stm32mp1-adc-core", 898 .data = (void *)&stm32mp1_adc_priv_cfg 899 }, { 900 .compatible = "st,stm32mp13-adc-core", 901 .data = (void *)&stm32mp13_adc_priv_cfg 902 }, { 903 }, 904}; 905MODULE_DEVICE_TABLE(of, stm32_adc_of_match); 906 907static struct platform_driver stm32_adc_driver = { 908 .probe = stm32_adc_probe, 909 .remove_new = stm32_adc_remove, 910 .driver = { 911 .name = "stm32-adc-core", 912 .of_match_table = stm32_adc_of_match, 913 .pm = pm_ptr(&stm32_adc_core_pm_ops), 914 }, 915}; 916module_platform_driver(stm32_adc_driver); 917 918MODULE_AUTHOR("Fabrice Gasnier <fabrice.gasnier@st.com>"); 919MODULE_DESCRIPTION("STMicroelectronics STM32 ADC core driver"); 920MODULE_LICENSE("GPL v2"); 921MODULE_ALIAS("platform:stm32-adc-core"); 922