Searched refs:ccm_base (Results 1 - 13 of 13) sorted by relevance

/linux-master/arch/arm/mach-imx/
H A Dpm-imx27.c20 void __iomem *ccm_base; local
25 ccm_base = of_iomap(np, 0);
26 BUG_ON(!ccm_base);
31 cscr = imx_readl(ccm_base);
33 imx_writel(cscr, ccm_base);
H A Dcpu-imx27.c25 void __iomem *ccm_base; local
30 ccm_base = of_iomap(np, 0);
32 BUG_ON(!ccm_base);
38 val = imx_readl(ccm_base + SYSCTRL_OFFSET + SYS_CHIP_ID);
H A Dpm-imx6.c64 static void __iomem *ccm_base; variable
227 struct imx6_pm_base ccm_base; member in struct:imx6_cpu_pm_info
236 u32 val = readl_relaxed(ccm_base + CGPR);
241 writel_relaxed(val, ccm_base + CGPR);
255 val = readl_relaxed(ccm_base + CCR);
258 writel_relaxed(val, ccm_base + CCR);
261 val = readl_relaxed(ccm_base + CCR);
264 writel(val, ccm_base + CCR);
282 val = readl_relaxed(ccm_base + CLPCR);
285 writel_relaxed(val, ccm_base
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H A Dpm-imx5.c134 static void __iomem *ccm_base; variable
153 ccm_clpcr = imx_readl(ccm_base + MXC_CCM_CLPCR) &
195 imx_writel(ccm_clpcr, ccm_base + MXC_CCM_CLPCR);
389 ccm_base = ioremap(data->ccm_addr, SZ_16K);
392 WARN_ON(!ccm_base || !cortex_base || !gpc_base);
/linux-master/drivers/clk/imx/
H A Dclk-imx8mp.c412 void __iomem *anatop_base, *ccm_base; local
422 ccm_base = devm_platform_ioremap_resource(pdev, 0);
423 if (WARN_ON(IS_ERR(ccm_base)))
424 return PTR_ERR(ccm_base);
516 hws[IMX8MP_CLK_A53_DIV] = imx8m_clk_hw_composite_core("arm_a53_div", imx8mp_a53_sels, ccm_base + 0x8000);
519 hws[IMX8MP_CLK_M7_CORE] = imx8m_clk_hw_composite_core("m7_core", imx8mp_m7_sels, ccm_base + 0x8080);
520 hws[IMX8MP_CLK_ML_CORE] = imx8m_clk_hw_composite_core("ml_core", imx8mp_ml_sels, ccm_base + 0x8100);
521 hws[IMX8MP_CLK_GPU3D_CORE] = imx8m_clk_hw_composite_core("gpu3d_core", imx8mp_gpu3d_core_sels, ccm_base + 0x8180);
522 hws[IMX8MP_CLK_GPU3D_SHADER_CORE] = imx8m_clk_hw_composite("gpu3d_shader_core", imx8mp_gpu3d_shader_sels, ccm_base + 0x8200);
523 hws[IMX8MP_CLK_GPU2D_CORE] = imx8m_clk_hw_composite("gpu2d_core", imx8mp_gpu2d_sels, ccm_base
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H A Dclk-imxrt1050.c38 void __iomem *ccm_base; local
108 ccm_base = devm_platform_ioremap_resource(pdev, 0);
109 if (WARN_ON(IS_ERR(ccm_base))) {
110 ret = PTR_ERR(ccm_base);
114 hws[IMXRT1050_CLK_ARM_PODF] = imx_clk_hw_divider("arm_podf", "pll1_arm", ccm_base + 0x10, 0, 3);
115 hws[IMXRT1050_CLK_PRE_PERIPH_SEL] = imx_clk_hw_mux("pre_periph_sel", ccm_base + 0x18, 18, 2,
117 hws[IMXRT1050_CLK_PERIPH_SEL] = imx_clk_hw_mux("periph_sel", ccm_base + 0x14, 25, 1,
119 hws[IMXRT1050_CLK_USDHC1_SEL] = imx_clk_hw_mux("usdhc1_sel", ccm_base + 0x1c, 16, 1,
121 hws[IMXRT1050_CLK_USDHC2_SEL] = imx_clk_hw_mux("usdhc2_sel", ccm_base + 0x1c, 17, 1,
123 hws[IMXRT1050_CLK_LPUART_SEL] = imx_clk_hw_mux("lpuart_sel", ccm_base
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H A Dclk-imx5.c30 #define MXC_CCM_CCR (ccm_base + 0x00)
31 #define MXC_CCM_CCDR (ccm_base + 0x04)
32 #define MXC_CCM_CSR (ccm_base + 0x08)
33 #define MXC_CCM_CCSR (ccm_base + 0x0c)
34 #define MXC_CCM_CACRR (ccm_base + 0x10)
35 #define MXC_CCM_CBCDR (ccm_base + 0x14)
36 #define MXC_CCM_CBCMR (ccm_base + 0x18)
37 #define MXC_CCM_CSCMR1 (ccm_base + 0x1c)
38 #define MXC_CCM_CSCMR2 (ccm_base + 0x20)
39 #define MXC_CCM_CSCDR1 (ccm_base
131 mx5_clocks_common_init(void __iomem *ccm_base) argument
282 void __iomem *ccm_base; local
367 void __iomem *ccm_base; local
473 void __iomem *ccm_base; local
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H A Dclk-vf610.c14 #define CCM_CCR (ccm_base + 0x00)
15 #define CCM_CSR (ccm_base + 0x04)
16 #define CCM_CCSR (ccm_base + 0x08)
17 #define CCM_CACRR (ccm_base + 0x0c)
18 #define CCM_CSCMR1 (ccm_base + 0x10)
19 #define CCM_CSCDR1 (ccm_base + 0x14)
20 #define CCM_CSCDR2 (ccm_base + 0x18)
21 #define CCM_CSCDR3 (ccm_base + 0x1c)
22 #define CCM_CSCMR2 (ccm_base + 0x20)
23 #define CCM_CSCDR4 (ccm_base
69 static void __iomem *ccm_base; variable
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H A Dclk.c32 void imx_mmdc_mask_handshake(void __iomem *ccm_base, argument
37 reg = readl_relaxed(ccm_base + CCM_CCDR);
39 writel_relaxed(reg, ccm_base + CCM_CCDR);
H A Dclk-imx6sl.c102 static void __iomem *ccm_base; variable
129 if (readl_relaxed(ccm_base + CCSR) & BM_CCSR_PLL1_SW_CLK_SEL) {
170 saved_arm_div = readl_relaxed(ccm_base + CACRR);
171 writel_relaxed(arm_div_for_wait, ccm_base + CACRR);
173 writel_relaxed(saved_arm_div, ccm_base + CACRR);
175 while (__raw_readl(ccm_base + CDHIPR) & BM_CDHIPR_ARM_PODF_BUSY)
291 ccm_base = base;
H A Dclk-imx6q.c271 static void mmdc_ch1_disable(void __iomem *ccm_base) argument
279 reg = readl_relaxed(ccm_base + CCM_CCSR);
281 writel_relaxed(reg, ccm_base + CCM_CCSR);
284 static void mmdc_ch1_reenable(void __iomem *ccm_base) argument
289 reg = readl_relaxed(ccm_base + CCM_CCSR);
291 writel_relaxed(reg, ccm_base + CCM_CCSR);
323 static void init_ldb_clks(struct device_node *np, void __iomem *ccm_base) argument
329 reg = readl_relaxed(ccm_base + CCM_CS2CDR);
371 mmdc_ch1_disable(ccm_base);
374 reg = readl_relaxed(ccm_base
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H A Dclk-imx25.c42 #define ccm(x) (ccm_base + (x))
77 static void __init __mx25_clocks_init(void __iomem *ccm_base) argument
79 BUG_ON(!ccm_base);
H A Dclk.h21 void imx_mmdc_mask_handshake(void __iomem *ccm_base, unsigned int chn);

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