1112158Sdas// SPDX-License-Identifier: GPL-2.0-or-later 2112158Sdas/* 3112158Sdas * Copyright 2011-2014 Freescale Semiconductor, Inc. 4112158Sdas * Copyright 2011 Linaro Ltd. 5112158Sdas */ 6112158Sdas 7112158Sdas#include <linux/clk/imx.h> 8112158Sdas#include <linux/delay.h> 9112158Sdas#include <linux/init.h> 10112158Sdas#include <linux/io.h> 11112158Sdas#include <linux/irq.h> 12112158Sdas#include <linux/genalloc.h> 13112158Sdas#include <linux/irqchip/arm-gic.h> 14112158Sdas#include <linux/mfd/syscon.h> 15112158Sdas#include <linux/mfd/syscon/imx6q-iomuxc-gpr.h> 16112158Sdas#include <linux/of.h> 17112158Sdas#include <linux/of_address.h> 18112158Sdas#include <linux/of_platform.h> 19112158Sdas#include <linux/platform_device.h> 20112158Sdas#include <linux/regmap.h> 21112158Sdas#include <linux/suspend.h> 22112158Sdas#include <asm/cacheflush.h> 23112158Sdas#include <asm/fncpy.h> 24112158Sdas#include <asm/proc-fns.h> 25112158Sdas#include <asm/suspend.h> 26112158Sdas#include <asm/tlb.h> 27112158Sdas 28112158Sdas#include "common.h" 29165743Sdas#include "hardware.h" 30165743Sdas 31112158Sdas#define CCR 0x0 32112158Sdas#define BM_CCR_WB_COUNT (0x7 << 16) 33112158Sdas#define BM_CCR_RBC_BYPASS_COUNT (0x3f << 21) 34112158Sdas#define BM_CCR_RBC_EN (0x1 << 27) 35112158Sdas 36112158Sdas#define CLPCR 0x54 37112158Sdas#define BP_CLPCR_LPM 0 38112158Sdas#define BM_CLPCR_LPM (0x3 << 0) 39112158Sdas#define BM_CLPCR_BYPASS_PMIC_READY (0x1 << 2) 40112158Sdas#define BM_CLPCR_ARM_CLK_DIS_ON_LPM (0x1 << 5) 41112158Sdas#define BM_CLPCR_SBYOS (0x1 << 6) 42112158Sdas#define BM_CLPCR_DIS_REF_OSC (0x1 << 7) 43112158Sdas#define BM_CLPCR_VSTBY (0x1 << 8) 44112158Sdas#define BP_CLPCR_STBY_COUNT 9 45112158Sdas#define BM_CLPCR_STBY_COUNT (0x3 << 9) 46112158Sdas#define BM_CLPCR_COSC_PWRDOWN (0x1 << 11) 47112158Sdas#define BM_CLPCR_WB_PER_AT_LPM (0x1 << 16) 48112158Sdas#define BM_CLPCR_WB_CORE_AT_LPM (0x1 << 17) 49112158Sdas#define BM_CLPCR_BYP_MMDC_CH0_LPM_HS (0x1 << 19) 50112158Sdas#define BM_CLPCR_BYP_MMDC_CH1_LPM_HS (0x1 << 21) 51112158Sdas#define BM_CLPCR_MASK_CORE0_WFI (0x1 << 22) 52112158Sdas#define BM_CLPCR_MASK_CORE1_WFI (0x1 << 23) 53112158Sdas#define BM_CLPCR_MASK_CORE2_WFI (0x1 << 24) 54112158Sdas#define BM_CLPCR_MASK_CORE3_WFI (0x1 << 25) 55112158Sdas#define BM_CLPCR_MASK_SCU_IDLE (0x1 << 26) 56112158Sdas#define BM_CLPCR_MASK_L2CC_IDLE (0x1 << 27) 57112158Sdas 58112158Sdas#define CGPR 0x64 59112158Sdas#define BM_CGPR_INT_MEM_CLK_LPM (0x1 << 17) 60112158Sdas 61112158Sdas#define MX6Q_SUSPEND_OCRAM_SIZE 0x1000 62112158Sdas#define MX6_MAX_MMDC_IO_NUM 33 63112158Sdas 64112158Sdasstatic void __iomem *ccm_base; 65112158Sdasstatic void __iomem *suspend_ocram_base; 66112158Sdasstatic void (*imx6_suspend_in_ocram_fn)(void __iomem *ocram_vbase); 67112158Sdas 68112158Sdas/* 69112158Sdas * suspend ocram space layout: 70112158Sdas * ======================== high address ====================== 71112158Sdas * . 72112158Sdas * . 73112158Sdas * . 74112158Sdas * ^ 75112158Sdas * ^ 76112158Sdas * ^ 77112158Sdas * imx6_suspend code 78112158Sdas * PM_INFO structure(imx6_cpu_pm_info) 79112158Sdas * ======================== low address ======================= 80112158Sdas */ 81112158Sdas 82112158Sdasstruct imx6_pm_base { 83112158Sdas phys_addr_t pbase; 84112158Sdas void __iomem *vbase; 85112158Sdas}; 86112158Sdas 87112158Sdasstruct imx6_pm_socdata { 88112158Sdas u32 ddr_type; 89112158Sdas const char *mmdc_compat; 90112158Sdas const char *src_compat; 91112158Sdas const char *iomuxc_compat; 92182709Sdas const char *gpc_compat; 93112158Sdas const char *pl310_compat; 94112158Sdas const u32 mmdc_io_num; 95112158Sdas const u32 *mmdc_io_offset; 96112158Sdas}; 97112158Sdas 98112158Sdasstatic const u32 imx6q_mmdc_io_offset[] __initconst = { 99112158Sdas 0x5ac, 0x5b4, 0x528, 0x520, /* DQM0 ~ DQM3 */ 100112158Sdas 0x514, 0x510, 0x5bc, 0x5c4, /* DQM4 ~ DQM7 */ 101112158Sdas 0x56c, 0x578, 0x588, 0x594, /* CAS, RAS, SDCLK_0, SDCLK_1 */ 102112158Sdas 0x5a8, 0x5b0, 0x524, 0x51c, /* SDQS0 ~ SDQS3 */ 103112158Sdas 0x518, 0x50c, 0x5b8, 0x5c0, /* SDQS4 ~ SDQS7 */ 104112158Sdas 0x784, 0x788, 0x794, 0x79c, /* GPR_B0DS ~ GPR_B3DS */ 105112158Sdas 0x7a0, 0x7a4, 0x7a8, 0x748, /* GPR_B4DS ~ GPR_B7DS */ 106112158Sdas 0x59c, 0x5a0, 0x750, 0x774, /* SODT0, SODT1, MODE_CTL, MODE */ 107112158Sdas 0x74c, /* GPR_ADDS */ 108112158Sdas}; 109112158Sdas 110112158Sdasstatic const u32 imx6dl_mmdc_io_offset[] __initconst = { 111112158Sdas 0x470, 0x474, 0x478, 0x47c, /* DQM0 ~ DQM3 */ 112112158Sdas 0x480, 0x484, 0x488, 0x48c, /* DQM4 ~ DQM7 */ 113112158Sdas 0x464, 0x490, 0x4ac, 0x4b0, /* CAS, RAS, SDCLK_0, SDCLK_1 */ 114112158Sdas 0x4bc, 0x4c0, 0x4c4, 0x4c8, /* DRAM_SDQS0 ~ DRAM_SDQS3 */ 115112158Sdas 0x4cc, 0x4d0, 0x4d4, 0x4d8, /* DRAM_SDQS4 ~ DRAM_SDQS7 */ 116112158Sdas 0x764, 0x770, 0x778, 0x77c, /* GPR_B0DS ~ GPR_B3DS */ 117112158Sdas 0x780, 0x784, 0x78c, 0x748, /* GPR_B4DS ~ GPR_B7DS */ 118112158Sdas 0x4b4, 0x4b8, 0x750, 0x760, /* SODT0, SODT1, MODE_CTL, MODE */ 119112158Sdas 0x74c, /* GPR_ADDS */ 120112158Sdas}; 121112158Sdas 122112158Sdasstatic const u32 imx6sl_mmdc_io_offset[] __initconst = { 123112158Sdas 0x30c, 0x310, 0x314, 0x318, /* DQM0 ~ DQM3 */ 124112158Sdas 0x5c4, 0x5cc, 0x5d4, 0x5d8, /* GPR_B0DS ~ GPR_B3DS */ 125112158Sdas 0x300, 0x31c, 0x338, 0x5ac, /* CAS, RAS, SDCLK_0, GPR_ADDS */ 126112158Sdas 0x33c, 0x340, 0x5b0, 0x5c0, /* SODT0, SODT1, MODE_CTL, MODE */ 127112158Sdas 0x330, 0x334, 0x320, /* SDCKE0, SDCKE1, RESET */ 128112158Sdas}; 129112158Sdas 130112158Sdasstatic const u32 imx6sll_mmdc_io_offset[] __initconst = { 131112158Sdas 0x294, 0x298, 0x29c, 0x2a0, /* DQM0 ~ DQM3 */ 132112158Sdas 0x544, 0x54c, 0x554, 0x558, /* GPR_B0DS ~ GPR_B3DS */ 133112158Sdas 0x530, 0x540, 0x2ac, 0x52c, /* MODE_CTL, MODE, SDCLK_0, GPR_ADDDS */ 134112158Sdas 0x2a4, 0x2a8, /* SDCKE0, SDCKE1*/ 135112158Sdas}; 136112158Sdas 137112158Sdasstatic const u32 imx6sx_mmdc_io_offset[] __initconst = { 138112158Sdas 0x2ec, 0x2f0, 0x2f4, 0x2f8, /* DQM0 ~ DQM3 */ 139112158Sdas 0x60c, 0x610, 0x61c, 0x620, /* GPR_B0DS ~ GPR_B3DS */ 140112158Sdas 0x300, 0x2fc, 0x32c, 0x5f4, /* CAS, RAS, SDCLK_0, GPR_ADDS */ 141112158Sdas 0x310, 0x314, 0x5f8, 0x608, /* SODT0, SODT1, MODE_CTL, MODE */ 142112158Sdas 0x330, 0x334, 0x338, 0x33c, /* SDQS0 ~ SDQS3 */ 143112158Sdas}; 144112158Sdas 145112158Sdasstatic const u32 imx6ul_mmdc_io_offset[] __initconst = { 146112158Sdas 0x244, 0x248, 0x24c, 0x250, /* DQM0, DQM1, RAS, CAS */ 147112158Sdas 0x27c, 0x498, 0x4a4, 0x490, /* SDCLK0, GPR_B0DS-B1DS, GPR_ADDS */ 148112158Sdas 0x280, 0x284, 0x260, 0x264, /* SDQS0~1, SODT0, SODT1 */ 149112158Sdas 0x494, 0x4b0, /* MODE_CTL, MODE, */ 150112158Sdas}; 151112158Sdas 152112158Sdasstatic const struct imx6_pm_socdata imx6q_pm_data __initconst = { 153112158Sdas .mmdc_compat = "fsl,imx6q-mmdc", 154112158Sdas .src_compat = "fsl,imx6q-src", 155112158Sdas .iomuxc_compat = "fsl,imx6q-iomuxc", 156112158Sdas .gpc_compat = "fsl,imx6q-gpc", 157112158Sdas .pl310_compat = "arm,pl310-cache", 158112158Sdas .mmdc_io_num = ARRAY_SIZE(imx6q_mmdc_io_offset), 159112158Sdas .mmdc_io_offset = imx6q_mmdc_io_offset, 160112158Sdas}; 161112158Sdas 162112158Sdasstatic const struct imx6_pm_socdata imx6dl_pm_data __initconst = { 163112158Sdas .mmdc_compat = "fsl,imx6q-mmdc", 164112158Sdas .src_compat = "fsl,imx6q-src", 165112158Sdas .iomuxc_compat = "fsl,imx6dl-iomuxc", 166112158Sdas .gpc_compat = "fsl,imx6q-gpc", 167112158Sdas .pl310_compat = "arm,pl310-cache", 168112158Sdas .mmdc_io_num = ARRAY_SIZE(imx6dl_mmdc_io_offset), 169112158Sdas .mmdc_io_offset = imx6dl_mmdc_io_offset, 170112158Sdas}; 171112158Sdas 172112158Sdasstatic const struct imx6_pm_socdata imx6sl_pm_data __initconst = { 173112158Sdas .mmdc_compat = "fsl,imx6sl-mmdc", 174112158Sdas .src_compat = "fsl,imx6sl-src", 175219557Sdas .iomuxc_compat = "fsl,imx6sl-iomuxc", 176112158Sdas .gpc_compat = "fsl,imx6sl-gpc", 177219557Sdas .pl310_compat = "arm,pl310-cache", 178112158Sdas .mmdc_io_num = ARRAY_SIZE(imx6sl_mmdc_io_offset), 179112158Sdas .mmdc_io_offset = imx6sl_mmdc_io_offset, 180112158Sdas}; 181112158Sdas 182112158Sdasstatic const struct imx6_pm_socdata imx6sll_pm_data __initconst = { 183112158Sdas .mmdc_compat = "fsl,imx6sll-mmdc", 184112158Sdas .src_compat = "fsl,imx6sll-src", 185219557Sdas .iomuxc_compat = "fsl,imx6sll-iomuxc", 186112158Sdas .gpc_compat = "fsl,imx6sll-gpc", 187112158Sdas .pl310_compat = "arm,pl310-cache", 188112158Sdas .mmdc_io_num = ARRAY_SIZE(imx6sll_mmdc_io_offset), 189112158Sdas .mmdc_io_offset = imx6sll_mmdc_io_offset, 190112158Sdas}; 191112158Sdas 192112158Sdasstatic const struct imx6_pm_socdata imx6sx_pm_data __initconst = { 193112158Sdas .mmdc_compat = "fsl,imx6sx-mmdc", 194112158Sdas .src_compat = "fsl,imx6sx-src", 195112158Sdas .iomuxc_compat = "fsl,imx6sx-iomuxc", 196112158Sdas .gpc_compat = "fsl,imx6sx-gpc", 197112158Sdas .pl310_compat = "arm,pl310-cache", 198112158Sdas .mmdc_io_num = ARRAY_SIZE(imx6sx_mmdc_io_offset), 199112158Sdas .mmdc_io_offset = imx6sx_mmdc_io_offset, 200112158Sdas}; 201112158Sdas 202112158Sdasstatic const struct imx6_pm_socdata imx6ul_pm_data __initconst = { 203112158Sdas .mmdc_compat = "fsl,imx6ul-mmdc", 204112158Sdas .src_compat = "fsl,imx6ul-src", 205112158Sdas .iomuxc_compat = "fsl,imx6ul-iomuxc", 206112158Sdas .gpc_compat = "fsl,imx6ul-gpc", 207112158Sdas .pl310_compat = NULL, 208182709Sdas .mmdc_io_num = ARRAY_SIZE(imx6ul_mmdc_io_offset), 209112158Sdas .mmdc_io_offset = imx6ul_mmdc_io_offset, 210182709Sdas}; 211112158Sdas 212112158Sdas/* 213112158Sdas * This structure is for passing necessary data for low level ocram 214112158Sdas * suspend code(arch/arm/mach-imx/suspend-imx6.S), if this struct 215112158Sdas * definition is changed, the offset definition in 216112158Sdas * arch/arm/mach-imx/suspend-imx6.S must be also changed accordingly, 217112158Sdas * otherwise, the suspend to ocram function will be broken! 218112158Sdas */ 219112158Sdasstruct imx6_cpu_pm_info { 220112158Sdas phys_addr_t pbase; /* The physical address of pm_info. */ 221112158Sdas phys_addr_t resume_addr; /* The physical resume address for asm code */ 222112158Sdas u32 ddr_type; 223112158Sdas u32 pm_info_size; /* Size of pm_info. */ 224112158Sdas struct imx6_pm_base mmdc_base; 225112158Sdas struct imx6_pm_base src_base; 226112158Sdas struct imx6_pm_base iomuxc_base; 227112158Sdas struct imx6_pm_base ccm_base; 228112158Sdas struct imx6_pm_base gpc_base; 229112158Sdas struct imx6_pm_base l2_base; 230112158Sdas u32 mmdc_io_num; /* Number of MMDC IOs which need saved/restored. */ 231112158Sdas u32 mmdc_io_val[MX6_MAX_MMDC_IO_NUM][2]; /* To save offset and value */ 232112158Sdas} __aligned(8); 233112158Sdas 234112158Sdasvoid imx6_set_int_mem_clk_lpm(bool enable) 235112158Sdas{ 236112158Sdas u32 val = readl_relaxed(ccm_base + CGPR); 237112158Sdas 238112158Sdas val &= ~BM_CGPR_INT_MEM_CLK_LPM; 239165743Sdas if (enable) 240112158Sdas val |= BM_CGPR_INT_MEM_CLK_LPM; 241112158Sdas writel_relaxed(val, ccm_base + CGPR); 242112158Sdas} 243112158Sdas 244112158Sdasvoid imx6_enable_rbc(bool enable) 245112158Sdas{ 246112158Sdas u32 val; 247112158Sdas 248112158Sdas /* 249112158Sdas * need to mask all interrupts in GPC before 250112158Sdas * operating RBC configurations 251112158Sdas */ 252112158Sdas imx_gpc_mask_all(); 253112158Sdas 254112158Sdas /* configure RBC enable bit */ 255112158Sdas val = readl_relaxed(ccm_base + CCR); 256112158Sdas val &= ~BM_CCR_RBC_EN; 257112158Sdas val |= enable ? BM_CCR_RBC_EN : 0; 258112158Sdas writel_relaxed(val, ccm_base + CCR); 259112158Sdas 260112158Sdas /* configure RBC count */ 261112158Sdas val = readl_relaxed(ccm_base + CCR); 262112158Sdas val &= ~BM_CCR_RBC_BYPASS_COUNT; 263112158Sdas val |= enable ? BM_CCR_RBC_BYPASS_COUNT : 0; 264112158Sdas writel(val, ccm_base + CCR); 265112158Sdas 266112158Sdas /* 267112158Sdas * need to delay at least 2 cycles of CKIL(32K) 268112158Sdas * due to hardware design requirement, which is 269112158Sdas * ~61us, here we use 65us for safe 270112158Sdas */ 271112158Sdas udelay(65); 272112158Sdas 273112158Sdas /* restore GPC interrupt mask settings */ 274112158Sdas imx_gpc_restore_all(); 275112158Sdas} 276112158Sdas 277112158Sdasstatic void imx6q_enable_wb(bool enable) 278112158Sdas{ 279112158Sdas u32 val; 280112158Sdas 281112158Sdas /* configure well bias enable bit */ 282112158Sdas val = readl_relaxed(ccm_base + CLPCR); 283112158Sdas val &= ~BM_CLPCR_WB_PER_AT_LPM; 284112158Sdas val |= enable ? BM_CLPCR_WB_PER_AT_LPM : 0; 285112158Sdas writel_relaxed(val, ccm_base + CLPCR); 286112158Sdas 287112158Sdas /* configure well bias count */ 288112158Sdas val = readl_relaxed(ccm_base + CCR); 289112158Sdas val &= ~BM_CCR_WB_COUNT; 290112158Sdas val |= enable ? BM_CCR_WB_COUNT : 0; 291112158Sdas writel_relaxed(val, ccm_base + CCR); 292112158Sdas} 293112158Sdas 294219557Sdasint imx6_set_lpm(enum mxc_cpu_pwr_mode mode) 295112158Sdas{ 296219557Sdas u32 val = readl_relaxed(ccm_base + CLPCR); 297112158Sdas 298112158Sdas val &= ~BM_CLPCR_LPM; 299112158Sdas switch (mode) { 300112158Sdas case WAIT_CLOCKED: 301112158Sdas break; 302112158Sdas case WAIT_UNCLOCKED: 303112158Sdas val |= 0x1 << BP_CLPCR_LPM; 304112158Sdas val |= BM_CLPCR_ARM_CLK_DIS_ON_LPM; 305112158Sdas break; 306112158Sdas case STOP_POWER_ON: 307112158Sdas val |= 0x2 << BP_CLPCR_LPM; 308112158Sdas val &= ~BM_CLPCR_VSTBY; 309112158Sdas val &= ~BM_CLPCR_SBYOS; 310112158Sdas if (cpu_is_imx6sl()) 311112158Sdas val |= BM_CLPCR_BYPASS_PMIC_READY; 312112158Sdas if (cpu_is_imx6sl() || cpu_is_imx6sx() || cpu_is_imx6ul() || 313112158Sdas cpu_is_imx6ull() || cpu_is_imx6sll() || cpu_is_imx6ulz()) 314112158Sdas val |= BM_CLPCR_BYP_MMDC_CH0_LPM_HS; 315112158Sdas else 316227753Stheraven val |= BM_CLPCR_BYP_MMDC_CH1_LPM_HS; 317112158Sdas break; 318227753Stheraven case WAIT_UNCLOCKED_POWER_OFF: 319227753Stheraven val |= 0x1 << BP_CLPCR_LPM; 320112158Sdas val &= ~BM_CLPCR_VSTBY; 321227753Stheraven val &= ~BM_CLPCR_SBYOS; 322112158Sdas break; 323112158Sdas case STOP_POWER_OFF: 324112158Sdas val |= 0x2 << BP_CLPCR_LPM; 325165743Sdas val |= 0x3 << BP_CLPCR_STBY_COUNT; 326165743Sdas val |= BM_CLPCR_VSTBY; 327112158Sdas val |= BM_CLPCR_SBYOS; 328112158Sdas if (cpu_is_imx6sl() || cpu_is_imx6sx()) 329112158Sdas val |= BM_CLPCR_BYPASS_PMIC_READY; 330219557Sdas if (cpu_is_imx6sl() || cpu_is_imx6sx() || cpu_is_imx6ul() || 331112158Sdas cpu_is_imx6ull() || cpu_is_imx6sll() || cpu_is_imx6ulz()) 332219557Sdas val |= BM_CLPCR_BYP_MMDC_CH0_LPM_HS; 333182709Sdas else 334112158Sdas val |= BM_CLPCR_BYP_MMDC_CH1_LPM_HS; 335187808Sdas break; 336187808Sdas default: 337227753Stheraven return -EINVAL; 338187808Sdas } 339187808Sdas 340187808Sdas /* 341187808Sdas * ERR007265: CCM: When improper low-power sequence is used, 342187808Sdas * the SoC enters low power mode before the ARM core executes WFI. 343187808Sdas * 344227753Stheraven * Software workaround: 345219557Sdas * 1) Software should trigger IRQ #32 (IOMUX) to be always pending 346187808Sdas * by setting IOMUX_GPR1_GINT. 347187808Sdas * 2) Software should then unmask IRQ #32 in GPC before setting CCM 348187808Sdas * Low-Power mode. 349187808Sdas * 3) Software should mask IRQ #32 right after CCM Low-Power mode 350187808Sdas * is set (set bits 0-1 of CCM_CLPCR). 351187808Sdas * 352187808Sdas * Note that IRQ #32 is GIC SPI #0. 353187808Sdas */ 354187808Sdas if (mode != WAIT_CLOCKED) 355187808Sdas imx_gpc_hwirq_unmask(0); 356112158Sdas writel_relaxed(val, ccm_base + CLPCR); 357112158Sdas if (mode != WAIT_CLOCKED) 358112158Sdas imx_gpc_hwirq_mask(0); 359219557Sdas 360112158Sdas return 0; 361112158Sdas} 362112158Sdas 363112158Sdasstatic int imx6q_suspend_finish(unsigned long val) 364112158Sdas{ 365112158Sdas if (!imx6_suspend_in_ocram_fn) { 366112158Sdas cpu_do_idle(); 367112158Sdas } else { 368112158Sdas /* 369112158Sdas * call low level suspend function in ocram, 370112158Sdas * as we need to float DDR IO. 371112158Sdas */ 372112158Sdas local_flush_tlb_all(); 373112158Sdas /* check if need to flush internal L2 cache */ 374112158Sdas if (!((struct imx6_cpu_pm_info *) 375112158Sdas suspend_ocram_base)->l2_base.vbase) 376112158Sdas flush_cache_all(); 377112158Sdas imx6_suspend_in_ocram_fn(suspend_ocram_base); 378112158Sdas } 379112158Sdas 380112158Sdas return 0; 381112158Sdas} 382112158Sdas 383112158Sdasstatic int imx6q_pm_enter(suspend_state_t state) 384112158Sdas{ 385112158Sdas switch (state) { 386112158Sdas case PM_SUSPEND_STANDBY: 387112158Sdas imx6_set_lpm(STOP_POWER_ON); 388112158Sdas imx6_set_int_mem_clk_lpm(true); 389112158Sdas imx_gpc_pre_suspend(false); 390112158Sdas if (cpu_is_imx6sl()) 391112158Sdas imx6sl_set_wait_clk(true); 392112158Sdas /* Zzz ... */ 393112158Sdas cpu_do_idle(); 394112158Sdas if (cpu_is_imx6sl()) 395112158Sdas imx6sl_set_wait_clk(false); 396112158Sdas imx_gpc_post_resume(); 397112158Sdas imx6_set_lpm(WAIT_CLOCKED); 398112158Sdas break; 399112158Sdas case PM_SUSPEND_MEM: 400112158Sdas imx6_set_lpm(STOP_POWER_OFF); 401112158Sdas imx6_set_int_mem_clk_lpm(false); 402112158Sdas imx6q_enable_wb(true); 403112158Sdas /* 404112158Sdas * For suspend into ocram, asm code already take care of 405112158Sdas * RBC setting, so we do NOT need to do that here. 406112158Sdas */ 407165743Sdas if (!imx6_suspend_in_ocram_fn) 408112158Sdas imx6_enable_rbc(true); 409112158Sdas imx_gpc_pre_suspend(true); 410112158Sdas imx_anatop_pre_suspend(); 411112158Sdas /* Zzz ... */ 412112158Sdas cpu_suspend(0, imx6q_suspend_finish); 413112158Sdas if (cpu_is_imx6q() || cpu_is_imx6dl()) 414187808Sdas imx_smp_prepare(); 415187808Sdas imx_anatop_post_resume(); 416187808Sdas imx_gpc_post_resume(); 417187808Sdas imx6_enable_rbc(false); 418187808Sdas imx6q_enable_wb(false); 419187808Sdas imx6_set_int_mem_clk_lpm(true); 420112415Sdas imx6_set_lpm(WAIT_CLOCKED); 421187808Sdas break; 422187808Sdas default: 423112158Sdas return -EINVAL; 424165743Sdas } 425112158Sdas 426112158Sdas return 0; 427112158Sdas} 428112158Sdas 429112158Sdasstatic int imx6q_pm_valid(suspend_state_t state) 430112158Sdas{ 431112158Sdas return (state == PM_SUSPEND_STANDBY || state == PM_SUSPEND_MEM); 432112158Sdas} 433112158Sdas 434112158Sdasstatic const struct platform_suspend_ops imx6q_pm_ops = { 435112158Sdas .enter = imx6q_pm_enter, 436112158Sdas .valid = imx6q_pm_valid, 437112158Sdas}; 438112158Sdas 439112158Sdasstatic int __init imx6_pm_get_base(struct imx6_pm_base *base, 440112158Sdas const char *compat) 441112158Sdas{ 442112158Sdas struct device_node *node; 443112158Sdas struct resource res; 444112158Sdas int ret = 0; 445112158Sdas 446112158Sdas node = of_find_compatible_node(NULL, NULL, compat); 447112158Sdas if (!node) 448112158Sdas return -ENODEV; 449112158Sdas 450112158Sdas ret = of_address_to_resource(node, 0, &res); 451112158Sdas if (ret) 452112158Sdas goto put_node; 453187808Sdas 454112158Sdas base->pbase = res.start; 455112158Sdas base->vbase = ioremap(res.start, resource_size(&res)); 456112158Sdas if (!base->vbase) 457112158Sdas ret = -ENOMEM; 458112158Sdas 459112158Sdasput_node: 460112158Sdas of_node_put(node); 461112158Sdas return ret; 462112158Sdas} 463112158Sdas 464112158Sdasstatic int __init imx6q_suspend_init(const struct imx6_pm_socdata *socdata) 465112158Sdas{ 466112158Sdas phys_addr_t ocram_pbase; 467112158Sdas struct device_node *node; 468112158Sdas struct platform_device *pdev; 469112158Sdas struct imx6_cpu_pm_info *pm_info; 470112158Sdas struct gen_pool *ocram_pool; 471112158Sdas unsigned long ocram_base; 472112158Sdas int i, ret = 0; 473112158Sdas const u32 *mmdc_offset_array; 474112158Sdas 475112158Sdas suspend_set_ops(&imx6q_pm_ops); 476112158Sdas 477112158Sdas if (!socdata) { 478112158Sdas pr_warn("%s: invalid argument!\n", __func__); 479112158Sdas return -EINVAL; 480112158Sdas } 481112158Sdas 482112158Sdas node = of_find_compatible_node(NULL, NULL, "mmio-sram"); 483112158Sdas if (!node) { 484112158Sdas pr_warn("%s: failed to find ocram node!\n", __func__); 485112158Sdas return -ENODEV; 486112158Sdas } 487112158Sdas 488112158Sdas pdev = of_find_device_by_node(node); 489112158Sdas if (!pdev) { 490112158Sdas pr_warn("%s: failed to find ocram device!\n", __func__); 491112158Sdas ret = -ENODEV; 492112158Sdas goto put_node; 493112158Sdas } 494112158Sdas 495112158Sdas ocram_pool = gen_pool_get(&pdev->dev, NULL); 496112158Sdas if (!ocram_pool) { 497112158Sdas pr_warn("%s: ocram pool unavailable!\n", __func__); 498165743Sdas ret = -ENODEV; 499165743Sdas goto put_device; 500112158Sdas } 501112158Sdas 502112158Sdas ocram_base = gen_pool_alloc(ocram_pool, MX6Q_SUSPEND_OCRAM_SIZE); 503112158Sdas if (!ocram_base) { 504112158Sdas pr_warn("%s: unable to alloc ocram!\n", __func__); 505112158Sdas ret = -ENOMEM; 506112158Sdas goto put_device; 507112158Sdas } 508112158Sdas 509112158Sdas ocram_pbase = gen_pool_virt_to_phys(ocram_pool, ocram_base); 510112158Sdas 511112158Sdas suspend_ocram_base = __arm_ioremap_exec(ocram_pbase, 512112158Sdas MX6Q_SUSPEND_OCRAM_SIZE, false); 513112158Sdas 514112158Sdas memset(suspend_ocram_base, 0, sizeof(*pm_info)); 515112158Sdas pm_info = suspend_ocram_base; 516112158Sdas pm_info->pbase = ocram_pbase; 517112158Sdas pm_info->resume_addr = __pa_symbol(v7_cpu_resume); 518112158Sdas pm_info->pm_info_size = sizeof(*pm_info); 519112158Sdas 520112158Sdas /* 521112158Sdas * ccm physical address is not used by asm code currently, 522112158Sdas * so get ccm virtual address directly. 523112158Sdas */ 524112158Sdas pm_info->ccm_base.vbase = ccm_base; 525112158Sdas 526112158Sdas ret = imx6_pm_get_base(&pm_info->mmdc_base, socdata->mmdc_compat); 527112158Sdas if (ret) { 528112158Sdas pr_warn("%s: failed to get mmdc base %d!\n", __func__, ret); 529112158Sdas goto put_device; 530112158Sdas } 531112158Sdas 532112158Sdas ret = imx6_pm_get_base(&pm_info->src_base, socdata->src_compat); 533112158Sdas if (ret) { 534112158Sdas pr_warn("%s: failed to get src base %d!\n", __func__, ret); 535112158Sdas goto src_map_failed; 536112158Sdas } 537112158Sdas 538112158Sdas ret = imx6_pm_get_base(&pm_info->iomuxc_base, socdata->iomuxc_compat); 539112158Sdas if (ret) { 540112158Sdas pr_warn("%s: failed to get iomuxc base %d!\n", __func__, ret); 541112158Sdas goto iomuxc_map_failed; 542112158Sdas } 543112158Sdas 544112158Sdas ret = imx6_pm_get_base(&pm_info->gpc_base, socdata->gpc_compat); 545112158Sdas if (ret) { 546112158Sdas pr_warn("%s: failed to get gpc base %d!\n", __func__, ret); 547112158Sdas goto gpc_map_failed; 548112158Sdas } 549112158Sdas 550112158Sdas if (socdata->pl310_compat) { 551219557Sdas ret = imx6_pm_get_base(&pm_info->l2_base, socdata->pl310_compat); 552112158Sdas if (ret) { 553219557Sdas pr_warn("%s: failed to get pl310-cache base %d!\n", 554112158Sdas __func__, ret); 555112158Sdas goto pl310_cache_map_failed; 556112158Sdas } 557219557Sdas } 558112158Sdas 559112158Sdas pm_info->ddr_type = imx_mmdc_get_ddr_type(); 560112158Sdas pm_info->mmdc_io_num = socdata->mmdc_io_num; 561112158Sdas mmdc_offset_array = socdata->mmdc_io_offset; 562112158Sdas 563112158Sdas for (i = 0; i < pm_info->mmdc_io_num; i++) { 564112158Sdas pm_info->mmdc_io_val[i][0] = 565219557Sdas mmdc_offset_array[i]; 566219557Sdas pm_info->mmdc_io_val[i][1] = 567219557Sdas readl_relaxed(pm_info->iomuxc_base.vbase + 568112158Sdas mmdc_offset_array[i]); 569112158Sdas } 570112158Sdas 571112158Sdas imx6_suspend_in_ocram_fn = fncpy( 572112158Sdas suspend_ocram_base + sizeof(*pm_info), 573112158Sdas &imx6_suspend, 574112158Sdas MX6Q_SUSPEND_OCRAM_SIZE - sizeof(*pm_info)); 575112158Sdas 576112158Sdas __arm_iomem_set_ro(suspend_ocram_base, MX6Q_SUSPEND_OCRAM_SIZE); 577112158Sdas 578112158Sdas goto put_device; 579112158Sdas 580219557Sdaspl310_cache_map_failed: 581112158Sdas iounmap(pm_info->gpc_base.vbase); 582112158Sdasgpc_map_failed: 583112158Sdas iounmap(pm_info->iomuxc_base.vbase); 584112158Sdasiomuxc_map_failed: 585112158Sdas iounmap(pm_info->src_base.vbase); 586219557Sdassrc_map_failed: 587219557Sdas iounmap(pm_info->mmdc_base.vbase); 588219557Sdasput_device: 589219557Sdas put_device(&pdev->dev); 590112158Sdasput_node: 591112158Sdas of_node_put(node); 592219557Sdas 593219557Sdas return ret; 594112158Sdas} 595219557Sdas 596112158Sdasstatic void __init imx6_pm_common_init(const struct imx6_pm_socdata 597219557Sdas *socdata) 598112158Sdas{ 599112158Sdas struct regmap *gpr; 600112158Sdas int ret; 601112158Sdas 602112158Sdas WARN_ON(!ccm_base); 603112158Sdas 604219557Sdas if (IS_ENABLED(CONFIG_SUSPEND)) { 605219557Sdas ret = imx6q_suspend_init(socdata); 606112158Sdas if (ret) 607112158Sdas pr_warn("%s: No DDR LPM support with suspend %d!\n", 608112158Sdas __func__, ret); 609112158Sdas } 610112158Sdas 611112158Sdas /* 612112158Sdas * This is for SW workaround step #1 of ERR007265, see comments 613112158Sdas * in imx6_set_lpm for details of this errata. 614112158Sdas * Force IOMUXC irq pending, so that the interrupt to GPC can be 615112158Sdas * used to deassert dsm_request signal when the signal gets 616112158Sdas * asserted unexpectedly. 617112158Sdas */ 618112158Sdas gpr = syscon_regmap_lookup_by_compatible("fsl,imx6q-iomuxc-gpr"); 619219557Sdas if (!IS_ERR(gpr)) 620112158Sdas regmap_update_bits(gpr, IOMUXC_GPR1, IMX6Q_GPR1_GINT, 621112158Sdas IMX6Q_GPR1_GINT); 622219557Sdas} 623219557Sdas 624112158Sdasstatic void imx6_pm_stby_poweroff(void) 625219557Sdas{ 626219557Sdas gic_cpu_if_down(0); 627219557Sdas imx6_set_lpm(STOP_POWER_OFF); 628219557Sdas imx6q_suspend_finish(0); 629112158Sdas 630219557Sdas mdelay(1000); 631219557Sdas 632219557Sdas pr_emerg("Unable to poweroff system\n"); 633112158Sdas} 634112158Sdas 635219557Sdasstatic int imx6_pm_stby_poweroff_probe(void) 636112158Sdas{ 637112158Sdas if (pm_power_off) { 638112158Sdas pr_warn("%s: pm_power_off already claimed %p %ps!\n", 639112158Sdas __func__, pm_power_off, pm_power_off); 640112158Sdas return -EBUSY; 641219557Sdas } 642112158Sdas 643112158Sdas pm_power_off = imx6_pm_stby_poweroff; 644219557Sdas return 0; 645219557Sdas} 646112158Sdas 647219557Sdasvoid __init imx6_pm_ccm_init(const char *ccm_compat) 648219557Sdas{ 649219557Sdas struct device_node *np; 650219557Sdas u32 val; 651112158Sdas 652219557Sdas np = of_find_compatible_node(NULL, NULL, ccm_compat); 653219557Sdas ccm_base = of_iomap(np, 0); 654219557Sdas BUG_ON(!ccm_base); 655112158Sdas 656112158Sdas /* 657219557Sdas * Initialize CCM_CLPCR_LPM into RUN mode to avoid ARM core 658112158Sdas * clock being shut down unexpectedly by WAIT mode. 659112158Sdas */ 660165743Sdas val = readl_relaxed(ccm_base + CLPCR); 661165743Sdas val &= ~BM_CLPCR_LPM; 662165743Sdas writel_relaxed(val, ccm_base + CLPCR); 663165743Sdas 664165743Sdas if (of_property_read_bool(np, "fsl,pmic-stby-poweroff")) 665165743Sdas imx6_pm_stby_poweroff_probe(); 666165743Sdas 667165743Sdas of_node_put(np); 668219557Sdas} 669112158Sdas 670112158Sdasvoid __init imx6q_pm_init(void) 671112158Sdas{ 672112158Sdas imx6_pm_common_init(&imx6q_pm_data); 673112158Sdas} 674112158Sdas 675112158Sdasvoid __init imx6dl_pm_init(void) 676112158Sdas{ 677165743Sdas imx6_pm_common_init(&imx6dl_pm_data); 678165743Sdas} 679112158Sdas 680112158Sdasvoid __init imx6sl_pm_init(void) 681112158Sdas{ 682112158Sdas struct regmap *gpr; 683112158Sdas 684112158Sdas if (cpu_is_imx6sl()) { 685112158Sdas imx6_pm_common_init(&imx6sl_pm_data); 686112158Sdas } else { 687112158Sdas imx6_pm_common_init(&imx6sll_pm_data); 688112158Sdas gpr = syscon_regmap_lookup_by_compatible("fsl,imx6q-iomuxc-gpr"); 689112158Sdas if (!IS_ERR(gpr)) 690112158Sdas regmap_update_bits(gpr, IOMUXC_GPR5, 691112158Sdas IMX6SLL_GPR5_AFCG_X_BYPASS_MASK, 0); 692112158Sdas } 693112158Sdas} 694112158Sdas 695112158Sdasvoid __init imx6sx_pm_init(void) 696112158Sdas{ 697112158Sdas imx6_pm_common_init(&imx6sx_pm_data); 698112158Sdas} 699112158Sdas 700112158Sdasvoid __init imx6ul_pm_init(void) 701112158Sdas{ 702112158Sdas imx6_pm_common_init(&imx6ul_pm_data); 703112158Sdas} 704112158Sdas