/linux-master/drivers/net/wireless/quantenna/qtnfmac/pcie/ |
H A D | pearl_pcie_regs.h | 8 #define PCIE_HDP_CTRL(base) ((base) + 0x2c00) 9 #define PCIE_HDP_AXI_CTRL(base) ((base) + 0x2c04) 10 #define PCIE_HDP_HOST_WR_DESC0(base) ((base) + 0x2c10) 11 #define PCIE_HDP_HOST_WR_DESC0_H(base) ((base) + 0x2c14) 12 #define PCIE_HDP_HOST_WR_DESC1(base) ((base) [all...] |
H A D | topaz_pcie_regs.h | 8 #define PCIE_DMA_WR_INTR_STATUS(base) ((base) + 0x9bc) 9 #define PCIE_DMA_WR_INTR_MASK(base) ((base) + 0x9c4) 10 #define PCIE_DMA_WR_INTR_CLR(base) ((base) + 0x9c8) 11 #define PCIE_DMA_WR_ERR_STATUS(base) ((base) + 0x9cc) 12 #define PCIE_DMA_WR_DONE_IMWR_ADDR_LOW(base) ((base) [all...] |
/linux-master/drivers/watchdog/ |
H A D | nv_tco.h | 30 #define TCO_RLD(base) ((base) + 0x00) /* TCO Timer Reload and Current Value */ 31 #define TCO_TMR(base) ((base) + 0x01) /* TCO Timer Initial Value */ 33 #define TCO_STS(base) ((base) + 0x04) /* TCO Status Register */ 49 #define TCO_CNT(base) ((base) + 0x08) /* TCO Control Register */ 56 * The SMI_EN register is at the base io address + 0x04, 59 #define MCP51_SMI_EN(base) ((bas [all...] |
/linux-master/arch/parisc/ |
H A D | install.sh | 22 base=vmlinuz 26 base=vmlinux 29 if [ -f $4/$base-$1 ]; then 30 mv $4/$base-$1 $4/$base-$1.old 32 cat $2 > $4/$base-$1
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/linux-master/arch/riscv/boot/ |
H A D | install.sh | 23 base=vmlinuz 27 base=vmlinux 30 if [ -f $4/$base-$1 ]; then 31 mv $4/$base-$1 $4/$base-$1.old 33 cat $2 > $4/$base-$1
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/linux-master/arch/arm64/boot/ |
H A D | install.sh | 24 base=vmlinuz 28 base=vmlinux 31 if [ -f $4/$base-$1 ]; then 32 mv $4/$base-$1 $4/$base-$1.old 34 cat $2 > $4/$base-$1
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/linux-master/drivers/gpu/drm/i915/gt/ |
H A D | intel_engine_regs.h | 11 #define RING_EXCC(base) _MMIO((base) + 0x28) 12 #define RING_TAIL(base) _MMIO((base) + 0x30) 14 #define RING_HEAD(base) _MMIO((base) + 0x34) 18 #define RING_START(base) _MMIO((base) + 0x38) 19 #define RING_CTL(base) _MMIO((base) [all...] |
/linux-master/drivers/gpu/drm/sun4i/ |
H A D | sun8i_vi_scaler.h | 30 #define SUN8I_SCALER_VSU_CTRL(base) ((base) + 0x0) 31 #define SUN50I_SCALER_VSU_SCALE_MODE(base) ((base) + 0x10) 32 #define SUN50I_SCALER_VSU_DIR_THR(base) ((base) + 0x20) 33 #define SUN50I_SCALER_VSU_EDGE_THR(base) ((base) + 0x24) 34 #define SUN50I_SCALER_VSU_EDSCL_CTRL(base) ((base) [all...] |
H A D | sun8i_ui_scaler.h | 26 #define SUN8I_SCALER_GSU_CTRL(base) ((base) + 0x0) 27 #define SUN8I_SCALER_GSU_OUTSIZE(base) ((base) + 0x40) 28 #define SUN8I_SCALER_GSU_INSIZE(base) ((base) + 0x80) 29 #define SUN8I_SCALER_GSU_HSTEP(base) ((base) + 0x88) 30 #define SUN8I_SCALER_GSU_VSTEP(base) ((base) [all...] |
H A D | sun8i_ui_layer.h | 17 #define SUN8I_MIXER_CHAN_UI_LAYER_ATTR(base, layer) \ 18 ((base) + 0x20 * (layer) + 0x0) 19 #define SUN8I_MIXER_CHAN_UI_LAYER_SIZE(base, layer) \ 20 ((base) + 0x20 * (layer) + 0x4) 21 #define SUN8I_MIXER_CHAN_UI_LAYER_COORD(base, layer) \ 22 ((base) + 0x20 * (layer) + 0x8) 23 #define SUN8I_MIXER_CHAN_UI_LAYER_PITCH(base, layer) \ 24 ((base) + 0x20 * (layer) + 0xc) 25 #define SUN8I_MIXER_CHAN_UI_LAYER_TOP_LADDR(base, layer) \ 26 ((base) [all...] |
H A D | sun8i_vi_layer.h | 11 #define SUN8I_MIXER_CHAN_VI_LAYER_ATTR(base, layer) \ 12 ((base) + 0x30 * (layer) + 0x0) 13 #define SUN8I_MIXER_CHAN_VI_LAYER_SIZE(base, layer) \ 14 ((base) + 0x30 * (layer) + 0x4) 15 #define SUN8I_MIXER_CHAN_VI_LAYER_COORD(base, layer) \ 16 ((base) + 0x30 * (layer) + 0x8) 17 #define SUN8I_MIXER_CHAN_VI_LAYER_PITCH(base, layer, plane) \ 18 ((base) + 0x30 * (layer) + 0xc + 4 * (plane)) 19 #define SUN8I_MIXER_CHAN_VI_LAYER_TOP_LADDR(base, layer, plane) \ 20 ((base) [all...] |
/linux-master/drivers/scsi/ |
H A D | nsp32_io.h | 12 static inline void nsp32_write1(unsigned int base, argument 16 outb(val, (base + index)); 19 static inline unsigned char nsp32_read1(unsigned int base, argument 22 return inb(base + index); 25 static inline void nsp32_write2(unsigned int base, argument 29 outw(val, (base + index)); 32 static inline unsigned short nsp32_read2(unsigned int base, argument 35 return inw(base + index); 38 static inline void nsp32_write4(unsigned int base, argument 42 outl(val, (base 45 nsp32_read4(unsigned int base, unsigned int index) argument 53 nsp32_mmio_write1(unsigned long base, unsigned int index, unsigned char val) argument 64 nsp32_mmio_read1(unsigned long base, unsigned int index) argument 74 nsp32_mmio_write2(unsigned long base, unsigned int index, unsigned short val) argument 85 nsp32_mmio_read2(unsigned long base, unsigned int index) argument 95 nsp32_mmio_write4(unsigned long base, unsigned int index, unsigned long val) argument 106 nsp32_mmio_read4(unsigned long base, unsigned int index) argument 118 nsp32_index_read1(unsigned int base, unsigned int reg) argument 125 nsp32_index_write1(unsigned int base, unsigned int reg, unsigned char val) argument 133 nsp32_index_read2(unsigned int base, unsigned int reg) argument 140 nsp32_index_write2(unsigned int base, unsigned int reg, unsigned short val) argument 148 nsp32_index_read4(unsigned int base, unsigned int reg) argument 160 nsp32_index_write4(unsigned int base, unsigned int reg, unsigned long val) argument 176 nsp32_mmio_index_read1(unsigned long base, unsigned int reg) argument 188 nsp32_mmio_index_write1(unsigned long base, unsigned int reg, unsigned char val) argument 201 nsp32_mmio_index_read2(unsigned long base, unsigned int reg) argument 213 nsp32_mmio_index_write2(unsigned long base, unsigned int reg, unsigned short val) argument 228 nsp32_multi_read4(unsigned int base, unsigned int reg, void *buf, unsigned long count) argument 236 nsp32_fifo_read(unsigned int base, void *buf, unsigned long count) argument 243 nsp32_multi_write4(unsigned int base, unsigned int reg, void *buf, unsigned long count) argument 251 nsp32_fifo_write(unsigned int base, void *buf, unsigned long count) argument [all...] |
H A D | aha1740.h | 19 #define HID0(base) (base + 0x0) 20 #define HID1(base) (base + 0x1) 21 #define HID2(base) (base + 0x2) 22 #define HID3(base) (base + 0x3) 23 #define EBCNTRL(base) (base [all...] |
/linux-master/include/linux/spi/ |
H A D | mc33880.h | 7 unsigned base; member in struct:mc33880_platform_data
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/linux-master/drivers/gpu/drm/i915/gem/selftests/ |
H A D | mock_gem_object.h | 13 struct drm_i915_gem_object base; member in struct:mock_object
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/linux-master/arch/mips/ath25/ |
H A D | early_printk.c | 18 static inline void prom_uart_wr(void __iomem *base, unsigned reg, argument 21 __raw_writel(ch, base + 4 * reg); 24 static inline unsigned char prom_uart_rr(void __iomem *base, unsigned reg) argument 26 return __raw_readl(base + 4 * reg); 31 static void __iomem *base; local 33 if (unlikely(base == NULL)) { 35 base = (void __iomem *)(KSEG1ADDR(AR2315_UART0_BASE)); 37 base = (void __iomem *)(KSEG1ADDR(AR5312_UART0_BASE)); 40 while ((prom_uart_rr(base, UART_LSR) & UART_LSR_THRE) == 0) 42 prom_uart_wr(base, UART_T [all...] |
/linux-master/arch/loongarch/lib/ |
H A D | xor_simd.c | 19 #define LD(reg, base, offset) \ 20 "vld $vr" #reg ", %[" #base "], " #offset "\n\t" 21 #define ST(reg, base, offset) \ 22 "vst $vr" #reg ", %[" #base "], " #offset "\n\t" 25 #define LD_INOUT_LINE(base) \ 26 LD(0, base, 0) \ 27 LD(1, base, 16) \ 28 LD(2, base, 32) \ 29 LD(3, base, 48) 31 #define LD_AND_XOR_LINE(base) \ [all...] |
/linux-master/drivers/gpu/drm/xe/regs/ |
H A D | xe_engine_regs.h | 46 #define RING_TAIL(base) XE_REG((base) + 0x30) 48 #define RING_HEAD(base) XE_REG((base) + 0x34) 51 #define RING_START(base) XE_REG((base) + 0x38) 53 #define RING_CTL(base) XE_REG((base) + 0x3c) 57 #define RING_PSMI_CTL(base) XE_REG((base) [all...] |
/linux-master/drivers/gpu/drm/i915/pxp/ |
H A D | intel_pxp_regs.h | 11 /* KCR subsystem register base address */ 16 #define KCR_INIT(base) _MMIO((base) + 0xf0) 22 #define KCR_SIP(base) _MMIO((base) + 0x260) 25 #define KCR_GLOBAL_TERMINATE(base) _MMIO((base) + 0xf8)
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/linux-master/drivers/media/platform/samsung/s5p-jpeg/ |
H A D | jpeg-hw-exynos4.h | 13 void exynos4_jpeg_sw_reset(void __iomem *base); 14 void exynos4_jpeg_set_enc_dec_mode(void __iomem *base, unsigned int mode); 15 void __exynos4_jpeg_set_img_fmt(void __iomem *base, unsigned int img_fmt, 17 void __exynos4_jpeg_set_enc_out_fmt(void __iomem *base, unsigned int out_fmt, 19 void exynos4_jpeg_set_enc_tbl(void __iomem *base); 20 void exynos4_jpeg_set_interrupt(void __iomem *base, unsigned int version); 21 unsigned int exynos4_jpeg_get_int_status(void __iomem *base); 22 void exynos4_jpeg_set_huf_table_enable(void __iomem *base, int value); 23 void exynos4_jpeg_set_sys_int_enable(void __iomem *base, int value); 24 void exynos4_jpeg_set_stream_buf_address(void __iomem *base, [all...] |
/linux-master/arch/arm/mach-aspeed/ |
H A D | platsmp.c | 17 void __iomem *base; local 19 base = of_iomap(secboot_node, 0); 20 if (!base) { 21 pr_err("could not map the secondary boot base!"); 25 writel_relaxed(0, base + BOOT_ADDR); 26 writel_relaxed(__pa_symbol(secondary_startup_arm), base + BOOT_ADDR); 27 writel_relaxed((0xABBAAB00 | (cpu & 0xff)), base + BOOT_SIG); 31 iounmap(base); 38 void __iomem *base; local 46 base [all...] |
/linux-master/lib/ |
H A D | kstrtox.h | 6 const char *_parse_integer_fixup_radix(const char *s, unsigned int *base); 7 unsigned int _parse_integer_limit(const char *s, unsigned int base, unsigned long long *res, 9 unsigned int _parse_integer(const char *s, unsigned int base, unsigned long long *res);
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/linux-master/arch/arm/boot/ |
H A D | install.sh | 23 base=vmlinuz 27 base=vmlinux 30 if [ -f $4/$base-$1 ]; then 31 mv $4/$base-$1 $4/$base-$1.old 33 cat $2 > $4/$base-$1
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/linux-master/arch/powerpc/boot/ |
H A D | stdlib.c | 12 /* Not currently supported: leading whitespace, sign, 0x prefix, zero base */ 13 unsigned long long int strtoull(const char *ptr, char **end, int base) argument 17 if (base > 36) 23 if (*ptr >= '0' && *ptr <= '9' && *ptr < '0' + base) 25 else if (*ptr >= 'A' && *ptr < 'A' + base - 10) 27 else if (*ptr >= 'a' && *ptr < 'a' + base - 10) 32 ret *= base;
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/linux-master/drivers/usb/dwc3/ |
H A D | io.h | 19 static inline u32 dwc3_readl(void __iomem *base, u32 offset) argument 28 value = readl(base + offset - DWC3_GLOBALS_REGS_START); 35 trace_dwc3_readl(base - DWC3_GLOBALS_REGS_START, offset, value); 40 static inline void dwc3_writel(void __iomem *base, u32 offset, u32 value) argument 47 writel(value, base + offset - DWC3_GLOBALS_REGS_START); 54 trace_dwc3_writel(base - DWC3_GLOBALS_REGS_START, offset, value);
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