1/* SPDX-License-Identifier: MIT */ 2/* 3 * Copyright �� 2022 Intel Corporation 4 */ 5 6#ifndef __INTEL_ENGINE_REGS__ 7#define __INTEL_ENGINE_REGS__ 8 9#include "i915_reg_defs.h" 10 11#define RING_EXCC(base) _MMIO((base) + 0x28) 12#define RING_TAIL(base) _MMIO((base) + 0x30) 13#define TAIL_ADDR 0x001FFFF8 14#define RING_HEAD(base) _MMIO((base) + 0x34) 15#define HEAD_WRAP_COUNT 0xFFE00000 16#define HEAD_WRAP_ONE 0x00200000 17#define HEAD_ADDR 0x001FFFFC 18#define RING_START(base) _MMIO((base) + 0x38) 19#define RING_CTL(base) _MMIO((base) + 0x3c) 20#define RING_CTL_SIZE(size) ((size) - PAGE_SIZE) /* in bytes -> pages */ 21#define RING_NR_PAGES 0x001FF000 22#define RING_REPORT_MASK 0x00000006 23#define RING_REPORT_64K 0x00000002 24#define RING_REPORT_128K 0x00000004 25#define RING_NO_REPORT 0x00000000 26#define RING_VALID_MASK 0x00000001 27#define RING_VALID 0x00000001 28#define RING_INVALID 0x00000000 29#define RING_WAIT_I8XX (1 << 0) /* gen2, PRBx_HEAD */ 30#define RING_WAIT (1 << 11) /* gen3+, PRBx_CTL */ 31#define RING_WAIT_SEMAPHORE (1 << 10) /* gen6+ */ 32#define RING_SYNC_0(base) _MMIO((base) + 0x40) 33#define RING_SYNC_1(base) _MMIO((base) + 0x44) 34#define RING_SYNC_2(base) _MMIO((base) + 0x48) 35#define GEN6_RVSYNC (RING_SYNC_0(RENDER_RING_BASE)) 36#define GEN6_RBSYNC (RING_SYNC_1(RENDER_RING_BASE)) 37#define GEN6_RVESYNC (RING_SYNC_2(RENDER_RING_BASE)) 38#define GEN6_VBSYNC (RING_SYNC_0(GEN6_BSD_RING_BASE)) 39#define GEN6_VRSYNC (RING_SYNC_1(GEN6_BSD_RING_BASE)) 40#define GEN6_VVESYNC (RING_SYNC_2(GEN6_BSD_RING_BASE)) 41#define GEN6_BRSYNC (RING_SYNC_0(BLT_RING_BASE)) 42#define GEN6_BVSYNC (RING_SYNC_1(BLT_RING_BASE)) 43#define GEN6_BVESYNC (RING_SYNC_2(BLT_RING_BASE)) 44#define GEN6_VEBSYNC (RING_SYNC_0(VEBOX_RING_BASE)) 45#define GEN6_VERSYNC (RING_SYNC_1(VEBOX_RING_BASE)) 46#define GEN6_VEVSYNC (RING_SYNC_2(VEBOX_RING_BASE)) 47#define RING_PSMI_CTL(base) _MMIO((base) + 0x50) 48#define GEN8_RC_SEMA_IDLE_MSG_DISABLE REG_BIT(12) 49#define GEN8_FF_DOP_CLOCK_GATE_DISABLE REG_BIT(10) 50#define GEN12_WAIT_FOR_EVENT_POWER_DOWN_DISABLE REG_BIT(7) 51#define GEN6_BSD_GO_INDICATOR REG_BIT(4) 52#define GEN6_BSD_SLEEP_INDICATOR REG_BIT(3) 53#define GEN6_BSD_SLEEP_FLUSH_DISABLE REG_BIT(2) 54#define GEN6_PSMI_SLEEP_MSG_DISABLE REG_BIT(0) 55#define RING_MAX_IDLE(base) _MMIO((base) + 0x54) 56#define PWRCTX_MAXCNT(base) _MMIO((base) + 0x54) 57#define IDLE_TIME_MASK 0xFFFFF 58#define RING_ACTHD_UDW(base) _MMIO((base) + 0x5c) 59#define RING_DMA_FADD_UDW(base) _MMIO((base) + 0x60) /* gen8+ */ 60#define RING_IPEIR(base) _MMIO((base) + 0x64) 61#define RING_IPEHR(base) _MMIO((base) + 0x68) 62#define RING_INSTDONE(base) _MMIO((base) + 0x6c) 63#define RING_INSTPS(base) _MMIO((base) + 0x70) 64#define RING_DMA_FADD(base) _MMIO((base) + 0x78) 65#define RING_ACTHD(base) _MMIO((base) + 0x74) 66#define RING_HWS_PGA(base) _MMIO((base) + 0x80) 67#define RING_CMD_BUF_CCTL(base) _MMIO((base) + 0x84) 68#define IPEIR(base) _MMIO((base) + 0x88) 69#define IPEHR(base) _MMIO((base) + 0x8c) 70#define RING_ID(base) _MMIO((base) + 0x8c) 71#define RING_NOPID(base) _MMIO((base) + 0x94) 72#define RING_HWSTAM(base) _MMIO((base) + 0x98) 73#define RING_MI_MODE(base) _MMIO((base) + 0x9c) 74#define ASYNC_FLIP_PERF_DISABLE REG_BIT(14) 75#define MI_FLUSH_ENABLE REG_BIT(12) 76#define TGL_NESTED_BB_EN REG_BIT(12) 77#define MODE_IDLE REG_BIT(9) 78#define STOP_RING REG_BIT(8) 79#define VS_TIMER_DISPATCH REG_BIT(6) 80#define RING_IMR(base) _MMIO((base) + 0xa8) 81#define RING_EIR(base) _MMIO((base) + 0xb0) 82#define RING_EMR(base) _MMIO((base) + 0xb4) 83#define RING_ESR(base) _MMIO((base) + 0xb8) 84#define GEN12_STATE_ACK_DEBUG(base) _MMIO((base) + 0xbc) 85#define RING_INSTPM(base) _MMIO((base) + 0xc0) 86#define RING_CMD_CCTL(base) _MMIO((base) + 0xc4) 87#define ACTHD(base) _MMIO((base) + 0xc8) 88#define GEN8_R_PWR_CLK_STATE(base) _MMIO((base) + 0xc8) 89#define GEN8_RPCS_ENABLE (1 << 31) 90#define GEN8_RPCS_S_CNT_ENABLE (1 << 18) 91#define GEN8_RPCS_S_CNT_SHIFT 15 92#define GEN8_RPCS_S_CNT_MASK (0x7 << GEN8_RPCS_S_CNT_SHIFT) 93#define GEN11_RPCS_S_CNT_SHIFT 12 94#define GEN11_RPCS_S_CNT_MASK (0x3f << GEN11_RPCS_S_CNT_SHIFT) 95#define GEN8_RPCS_SS_CNT_ENABLE (1 << 11) 96#define GEN8_RPCS_SS_CNT_SHIFT 8 97#define GEN8_RPCS_SS_CNT_MASK (0x7 << GEN8_RPCS_SS_CNT_SHIFT) 98#define GEN8_RPCS_EU_MAX_SHIFT 4 99#define GEN8_RPCS_EU_MAX_MASK (0xf << GEN8_RPCS_EU_MAX_SHIFT) 100#define GEN8_RPCS_EU_MIN_SHIFT 0 101#define GEN8_RPCS_EU_MIN_MASK (0xf << GEN8_RPCS_EU_MIN_SHIFT) 102 103#define RING_RESET_CTL(base) _MMIO((base) + 0xd0) 104#define RESET_CTL_CAT_ERROR REG_BIT(2) 105#define RESET_CTL_READY_TO_RESET REG_BIT(1) 106#define RESET_CTL_REQUEST_RESET REG_BIT(0) 107#define DMA_FADD_I8XX(base) _MMIO((base) + 0xd0) 108#define RING_BBSTATE(base) _MMIO((base) + 0x110) 109#define RING_BB_PPGTT (1 << 5) 110#define RING_SBBADDR(base) _MMIO((base) + 0x114) /* hsw+ */ 111#define RING_SBBSTATE(base) _MMIO((base) + 0x118) /* hsw+ */ 112#define RING_SBBADDR_UDW(base) _MMIO((base) + 0x11c) /* gen8+ */ 113#define RING_BBADDR(base) _MMIO((base) + 0x140) 114#define RING_BB_OFFSET(base) _MMIO((base) + 0x158) 115#define RING_BBADDR_UDW(base) _MMIO((base) + 0x168) /* gen8+ */ 116#define CCID(base) _MMIO((base) + 0x180) 117#define CCID_EN BIT(0) 118#define CCID_EXTENDED_STATE_RESTORE BIT(2) 119#define CCID_EXTENDED_STATE_SAVE BIT(3) 120#define RING_BB_PER_CTX_PTR(base) _MMIO((base) + 0x1c0) /* gen8+ */ 121#define PER_CTX_BB_FORCE BIT(2) 122#define PER_CTX_BB_VALID BIT(0) 123 124#define RING_INDIRECT_CTX(base) _MMIO((base) + 0x1c4) /* gen8+ */ 125#define RING_INDIRECT_CTX_OFFSET(base) _MMIO((base) + 0x1c8) /* gen8+ */ 126#define ECOSKPD(base) _MMIO((base) + 0x1d0) 127#define XEHP_BLITTER_SCHEDULING_MODE_MASK REG_GENMASK(12, 11) 128#define XEHP_BLITTER_ROUND_ROBIN_MODE \ 129 REG_FIELD_PREP(XEHP_BLITTER_SCHEDULING_MODE_MASK, 1) 130#define ECO_CONSTANT_BUFFER_SR_DISABLE REG_BIT(4) 131#define ECO_GATING_CX_ONLY REG_BIT(3) 132#define GEN6_BLITTER_FBC_NOTIFY REG_BIT(3) 133#define ECO_FLIP_DONE REG_BIT(0) 134#define GEN6_BLITTER_LOCK_SHIFT 16 135 136#define BLIT_CCTL(base) _MMIO((base) + 0x204) 137#define BLIT_CCTL_DST_MOCS_MASK REG_GENMASK(14, 8) 138#define BLIT_CCTL_SRC_MOCS_MASK REG_GENMASK(6, 0) 139#define BLIT_CCTL_MASK (BLIT_CCTL_DST_MOCS_MASK | \ 140 BLIT_CCTL_SRC_MOCS_MASK) 141#define BLIT_CCTL_MOCS(dst, src) \ 142 (REG_FIELD_PREP(BLIT_CCTL_DST_MOCS_MASK, (dst) << 1) | \ 143 REG_FIELD_PREP(BLIT_CCTL_SRC_MOCS_MASK, (src) << 1)) 144 145#define RING_CSCMDOP(base) _MMIO((base) + 0x20c) 146 147/* 148 * CMD_CCTL read/write fields take a MOCS value and _not_ a table index. 149 * The lsb of each can be considered a separate enabling bit for encryption. 150 * 6:0 == default MOCS value for reads => 6:1 == table index for reads. 151 * 13:7 == default MOCS value for writes => 13:8 == table index for writes. 152 * 15:14 == Reserved => 31:30 are set to 0. 153 */ 154#define CMD_CCTL_WRITE_OVERRIDE_MASK REG_GENMASK(13, 7) 155#define CMD_CCTL_READ_OVERRIDE_MASK REG_GENMASK(6, 0) 156#define CMD_CCTL_MOCS_MASK (CMD_CCTL_WRITE_OVERRIDE_MASK | \ 157 CMD_CCTL_READ_OVERRIDE_MASK) 158#define CMD_CCTL_MOCS_OVERRIDE(write, read) \ 159 (REG_FIELD_PREP(CMD_CCTL_WRITE_OVERRIDE_MASK, (write) << 1) | \ 160 REG_FIELD_PREP(CMD_CCTL_READ_OVERRIDE_MASK, (read) << 1)) 161 162#define RING_PREDICATE_RESULT(base) _MMIO((base) + 0x3b8) /* gen12+ */ 163 164#define MI_PREDICATE_RESULT_2(base) _MMIO((base) + 0x3bc) 165#define LOWER_SLICE_ENABLED (1 << 0) 166#define LOWER_SLICE_DISABLED (0 << 0) 167#define MI_PREDICATE_SRC0(base) _MMIO((base) + 0x400) 168#define MI_PREDICATE_SRC0_UDW(base) _MMIO((base) + 0x400 + 4) 169#define MI_PREDICATE_SRC1(base) _MMIO((base) + 0x408) 170#define MI_PREDICATE_SRC1_UDW(base) _MMIO((base) + 0x408 + 4) 171#define MI_PREDICATE_DATA(base) _MMIO((base) + 0x410) 172#define MI_PREDICATE_RESULT(base) _MMIO((base) + 0x418) 173#define MI_PREDICATE_RESULT_1(base) _MMIO((base) + 0x41c) 174 175#define RING_PP_DIR_DCLV(base) _MMIO((base) + 0x220) 176#define PP_DIR_DCLV_2G 0xffffffff 177#define RING_PP_DIR_BASE(base) _MMIO((base) + 0x228) 178#define RING_ELSP(base) _MMIO((base) + 0x230) 179#define RING_EXECLIST_STATUS_LO(base) _MMIO((base) + 0x234) 180#define RING_EXECLIST_STATUS_HI(base) _MMIO((base) + 0x234 + 4) 181#define RING_CONTEXT_CONTROL(base) _MMIO((base) + 0x244) 182#define CTX_CTRL_ENGINE_CTX_RESTORE_INHIBIT REG_BIT(0) 183#define CTX_CTRL_RS_CTX_ENABLE REG_BIT(1) 184#define CTX_CTRL_ENGINE_CTX_SAVE_INHIBIT REG_BIT(2) 185#define CTX_CTRL_INHIBIT_SYN_CTX_SWITCH REG_BIT(3) 186#define GEN12_CTX_CTRL_RUNALONE_MODE REG_BIT(7) 187#define GEN12_CTX_CTRL_OAR_CONTEXT_ENABLE REG_BIT(8) 188#define RING_CTX_SR_CTL(base) _MMIO((base) + 0x244) 189#define RING_SEMA_WAIT_POLL(base) _MMIO((base) + 0x24c) 190#define GEN8_RING_PDP_UDW(base, n) _MMIO((base) + 0x270 + (n) * 8 + 4) 191#define GEN8_RING_PDP_LDW(base, n) _MMIO((base) + 0x270 + (n) * 8) 192#define RING_MODE_GEN7(base) _MMIO((base) + 0x29c) 193#define GFX_RUN_LIST_ENABLE (1 << 15) 194#define GFX_INTERRUPT_STEERING (1 << 14) 195#define GFX_TLB_INVALIDATE_EXPLICIT (1 << 13) 196#define GFX_SURFACE_FAULT_ENABLE (1 << 12) 197#define GFX_REPLAY_MODE (1 << 11) 198#define GFX_PSMI_GRANULARITY (1 << 10) 199#define GEN12_GFX_PREFETCH_DISABLE REG_BIT(10) 200#define GFX_PPGTT_ENABLE (1 << 9) 201#define GEN8_GFX_PPGTT_48B (1 << 7) 202#define GFX_FORWARD_VBLANK_MASK (3 << 5) 203#define GFX_FORWARD_VBLANK_NEVER (0 << 5) 204#define GFX_FORWARD_VBLANK_ALWAYS (1 << 5) 205#define GFX_FORWARD_VBLANK_COND (2 << 5) 206#define GEN11_GFX_DISABLE_LEGACY_MODE (1 << 3) 207#define RING_TIMESTAMP(base) _MMIO((base) + 0x358) 208#define RING_TIMESTAMP_UDW(base) _MMIO((base) + 0x358 + 4) 209#define RING_CONTEXT_STATUS_PTR(base) _MMIO((base) + 0x3a0) 210#define RING_CTX_TIMESTAMP(base) _MMIO((base) + 0x3a8) /* gen8+ */ 211#define RING_PREDICATE_RESULT(base) _MMIO((base) + 0x3b8) 212#define MI_PREDICATE_RESULT_2_ENGINE(base) _MMIO((base) + 0x3bc) 213#define RING_FORCE_TO_NONPRIV(base, i) _MMIO(((base) + 0x4D0) + (i) * 4) 214#define RING_FORCE_TO_NONPRIV_DENY REG_BIT(30) 215#define RING_FORCE_TO_NONPRIV_ADDRESS_MASK REG_GENMASK(25, 2) 216#define RING_FORCE_TO_NONPRIV_ACCESS_RW (0 << 28) /* CFL+ & Gen11+ */ 217#define RING_FORCE_TO_NONPRIV_ACCESS_RD (1 << 28) 218#define RING_FORCE_TO_NONPRIV_ACCESS_WR (2 << 28) 219#define RING_FORCE_TO_NONPRIV_ACCESS_INVALID (3 << 28) 220#define RING_FORCE_TO_NONPRIV_ACCESS_MASK (3 << 28) 221#define RING_FORCE_TO_NONPRIV_RANGE_1 (0 << 0) /* CFL+ & Gen11+ */ 222#define RING_FORCE_TO_NONPRIV_RANGE_4 (1 << 0) 223#define RING_FORCE_TO_NONPRIV_RANGE_16 (2 << 0) 224#define RING_FORCE_TO_NONPRIV_RANGE_64 (3 << 0) 225#define RING_FORCE_TO_NONPRIV_RANGE_MASK (3 << 0) 226#define RING_FORCE_TO_NONPRIV_MASK_VALID \ 227 (RING_FORCE_TO_NONPRIV_RANGE_MASK | \ 228 RING_FORCE_TO_NONPRIV_ACCESS_MASK | \ 229 RING_FORCE_TO_NONPRIV_DENY) 230#define RING_MAX_NONPRIV_SLOTS 12 231 232#define RING_EXECLIST_SQ_CONTENTS(base) _MMIO((base) + 0x510) 233#define RING_PP_DIR_BASE_READ(base) _MMIO((base) + 0x518) 234#define RING_EXECLIST_CONTROL(base) _MMIO((base) + 0x550) 235#define EL_CTRL_LOAD REG_BIT(0) 236 237/* There are 16 64-bit CS General Purpose Registers per-engine on Gen8+ */ 238#define GEN8_RING_CS_GPR(base, n) _MMIO((base) + 0x600 + (n) * 8) 239#define GEN8_RING_CS_GPR_UDW(base, n) _MMIO((base) + 0x600 + (n) * 8 + 4) 240 241#define GEN11_VCS_SFC_FORCED_LOCK(base) _MMIO((base) + 0x88c) 242#define GEN11_VCS_SFC_FORCED_LOCK_BIT (1 << 0) 243#define GEN11_VCS_SFC_LOCK_STATUS(base) _MMIO((base) + 0x890) 244#define GEN11_VCS_SFC_USAGE_BIT (1 << 0) 245#define GEN11_VCS_SFC_LOCK_ACK_BIT (1 << 1) 246 247#define GEN11_VECS_SFC_FORCED_LOCK(base) _MMIO((base) + 0x201c) 248#define GEN11_VECS_SFC_FORCED_LOCK_BIT (1 << 0) 249#define GEN11_VECS_SFC_LOCK_ACK(base) _MMIO((base) + 0x2018) 250#define GEN11_VECS_SFC_LOCK_ACK_BIT (1 << 0) 251#define GEN11_VECS_SFC_USAGE(base) _MMIO((base) + 0x2014) 252#define GEN11_VECS_SFC_USAGE_BIT (1 << 0) 253 254#define RING_HWS_PGA_GEN6(base) _MMIO((base) + 0x2080) 255 256#define GEN12_HCP_SFC_LOCK_STATUS(base) _MMIO((base) + 0x2914) 257#define GEN12_HCP_SFC_LOCK_ACK_BIT REG_BIT(1) 258#define GEN12_HCP_SFC_USAGE_BIT REG_BIT(0) 259 260#define VDBOX_CGCTL3F10(base) _MMIO((base) + 0x3f10) 261#define IECPUNIT_CLKGATE_DIS REG_BIT(22) 262 263#define VDBOX_CGCTL3F18(base) _MMIO((base) + 0x3f18) 264#define ALNUNIT_CLKGATE_DIS REG_BIT(13) 265 266#define VDBOX_CGCTL3F1C(base) _MMIO((base) + 0x3f1c) 267#define MFXPIPE_CLKGATE_DIS REG_BIT(3) 268 269#endif /* __INTEL_ENGINE_REGS__ */ 270