Searched refs:WM_A (Results 1 - 14 of 14) sorted by relevance

/linux-master/drivers/gpu/drm/amd/display/dc/dml/dcn30/
H A Ddcn30_fpu.c370 if (dc->clk_mgr->bw_params->wm_table.nv_entries[WM_A].valid) {
373 context->bw_ctx.dml.soc.dram_clock_change_latency_us = dc->clk_mgr->bw_params->wm_table.nv_entries[WM_A].dml_input.pstate_latency_us;
374 context->bw_ctx.dml.soc.sr_enter_plus_exit_time_us = dc->clk_mgr->bw_params->wm_table.nv_entries[WM_A].dml_input.sr_enter_plus_exit_time_us;
375 context->bw_ctx.dml.soc.sr_exit_time_us = dc->clk_mgr->bw_params->wm_table.nv_entries[WM_A].dml_input.sr_exit_time_us;
413 context->bw_ctx.dml.soc.dram_clock_change_latency_us = dc->clk_mgr->bw_params->wm_table.nv_entries[WM_A].dml_input.pstate_latency_us;
587 dc->clk_mgr->bw_params->wm_table.nv_entries[WM_A].dml_input.pstate_latency_us;
739 base->bw_params->wm_table.nv_entries[WM_A].valid = true;
740 base->bw_params->wm_table.nv_entries[WM_A].dml_input.pstate_latency_us = pstate_latency_us;
741 base->bw_params->wm_table.nv_entries[WM_A].dml_input.sr_exit_time_us = sr_exit_time_us;
742 base->bw_params->wm_table.nv_entries[WM_A]
[all...]
/linux-master/drivers/gpu/drm/amd/display/dc/dml/dcn31/
H A Ddcn31_fpu.c458 if (dc->clk_mgr->bw_params->wm_table.entries[WM_A].valid) {
459 context->bw_ctx.dml.soc.dram_clock_change_latency_us = dc->clk_mgr->bw_params->wm_table.entries[WM_A].pstate_latency_us;
460 context->bw_ctx.dml.soc.sr_enter_plus_exit_time_us = dc->clk_mgr->bw_params->wm_table.entries[WM_A].sr_enter_plus_exit_time_us;
461 context->bw_ctx.dml.soc.sr_exit_time_us = dc->clk_mgr->bw_params->wm_table.entries[WM_A].sr_exit_time_us;
469 if (dc->clk_mgr->bw_params->wm_table.entries[WM_A].valid) {
474 context->bw_ctx.dml.soc.dram_clock_change_latency_us = dc->clk_mgr->bw_params->wm_table.entries[WM_A].pstate_latency_us;
476 dc->clk_mgr->bw_params->wm_table.entries[WM_A].sr_enter_plus_exit_time_us;
478 dc->clk_mgr->bw_params->wm_table.entries[WM_A].sr_exit_time_us;
/linux-master/drivers/gpu/drm/amd/display/dc/dml/dcn301/
H A Ddcn301_fpu.c221 .wm_inst = WM_A,
258 .wm_inst = WM_A,
448 table_entry = &bw_params->wm_table.entries[WM_A];
/linux-master/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn316/
H A Ddcn316_clk_mgr.c268 .wm_inst = WM_A,
305 .wm_inst = WM_A,
391 table->WatermarkRow[WM_SOCCLK][0].WmSetting = WM_A;
/linux-master/drivers/gpu/drm/amd/display/dc/inc/hw/
H A Dclk_mgr.h37 #define WM_A 0 macro
/linux-master/drivers/gpu/drm/amd/display/dc/dml/dcn32/
H A Ddcn32_fpu.c208 clk_mgr->base.bw_params->wm_table.nv_entries[WM_A].valid = true;
209 clk_mgr->base.bw_params->wm_table.nv_entries[WM_A].dml_input.pstate_latency_us = pstate_latency_us;
210 clk_mgr->base.bw_params->wm_table.nv_entries[WM_A].dml_input.fclk_change_latency_us = fclk_change_latency_us;
211 clk_mgr->base.bw_params->wm_table.nv_entries[WM_A].dml_input.sr_exit_time_us = sr_exit_time_us;
212 clk_mgr->base.bw_params->wm_table.nv_entries[WM_A].dml_input.sr_enter_plus_exit_time_us = sr_enter_plus_exit_time_us;
213 clk_mgr->base.bw_params->wm_table.nv_entries[WM_A].pmfw_breakdown.wm_type = WATERMARKS_CLOCK_RANGE;
214 clk_mgr->base.bw_params->wm_table.nv_entries[WM_A].pmfw_breakdown.min_dcfclk = min_dcfclk_mhz;
215 clk_mgr->base.bw_params->wm_table.nv_entries[WM_A].pmfw_breakdown.max_dcfclk = 0xFFFF;
216 clk_mgr->base.bw_params->wm_table.nv_entries[WM_A].pmfw_breakdown.min_uclk = min_uclk_mhz;
217 clk_mgr->base.bw_params->wm_table.nv_entries[WM_A]
[all...]
/linux-master/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn31/
H A Ddcn31_clk_mgr.c346 .wm_inst = WM_A,
383 .wm_inst = WM_A,
469 table->WatermarkRow[WM_SOCCLK][0].WmSetting = WM_A;
/linux-master/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn314/
H A Ddcn314_clk_mgr.c406 .wm_inst = WM_A,
443 .wm_inst = WM_A,
534 table->WatermarkRow[WM_SOCCLK][0].WmSetting = WM_A;
/linux-master/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn315/
H A Ddcn315_clk_mgr.c306 .wm_inst = WM_A,
343 .wm_inst = WM_A,
429 table->WatermarkRow[WM_SOCCLK][0].WmSetting = WM_A;
/linux-master/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn35/
H A Ddcn35_clk_mgr.c471 .wm_inst = WM_A,
508 .wm_inst = WM_A,
616 table->WatermarkRow[WM_SOCCLK][0].WmSetting = WM_A;
/linux-master/drivers/gpu/drm/amd/display/dc/dml/calcs/
H A Ddcn_calcs.c43 #define WM_A 0 macro
1525 ranges.reader_wm_sets[0].wm_inst = WM_A;
1530 ranges.writer_wm_sets[0].wm_inst = WM_A;
1537 ranges.reader_wm_sets[0].wm_inst = WM_A;
1542 ranges.writer_wm_sets[0].wm_inst = WM_A;
/linux-master/drivers/gpu/drm/amd/display/dc/dml/dcn20/
H A Ddcn20_fpu.c771 .wm_inst = WM_A,
808 .wm_inst = WM_A,
845 .wm_inst = WM_A,
882 .wm_inst = WM_A,
919 .wm_inst = WM_A,
956 .wm_inst = WM_A,
2309 table_entry = &bw_params->wm_table.entries[WM_A];
/linux-master/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn301/
H A Dvg_clk_mgr.c434 table->WatermarkRow[WM_SOCCLK][0].WmSetting = WM_A;
/linux-master/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn21/
H A Drn_clk_mgr.c503 ranges->writer_wm_sets[0].wm_inst = WM_A;

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